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CY62148EV30
Specification Sheet
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Cypress Semiconductor CY62148EV30 Specification Sheet

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MoBL® CY62148EV30
4-Mbit (512K x 8) Static RAM
Features
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER DOWN
CE
WE
OE
A
13
A
14
A
15
A16A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
10
A
11
A
12
A
18
■ Temperature ranges ❐ Industrial: –40°C to +85°C ❐ Automotive-A: –40°C to +85°C
■ Pin compatible with CY62148DV30
■ Ultra low standby power ❐ Typical standby current: 1 μA ❐ Maximum standby current: 7 μA (Industrial)
■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin
SOIC
[1]
packages
Logic Block Diagram
Functional Description
The CY62148EV30 organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE
HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE
To write to the device, take Chip Enable (CE (WE
) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A through A18).
To read from the device, take Chip Enable (CE Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins.
[2]
is a high performance CMOS static RAM
LOW and WE LOW).
®
) in portable
) and Write Enable
) and Output
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05576 Rev. *G Revised August 4, 2008
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MoBL® CY62148EV30
Pin Configuration
A
15
V
CC
A
13
A
12
A
5
NC
WE
A
7
IO
4
IO
5
A
4
IO
6
IO
7
V
ss
A
11
A
10
A
1
V
SS
IO
0
A
2
A
8
A
6
A
3
A
0
V
cc
IO
1
IO
2
IO
3
A
17
A
18
A
16
CE
OE
A
9
A
14
D
E
B
A
C
F
G
H
NC
36-Ball VFBGA Pinout
Top View
1
2 3
4
5 6
7
8
9 10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC/TSOP II Pinout
Top Vi ew
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
A
18
WE
OE
CE
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Product Portfolio
[1, 3]
Power Dissipation
Product Range VCC Range (V)
Min Typ
[4]
Max Typ
Speed
(ns)
Operating ICC (mA)
f = 1 MHz f = f
[4]
Max Typ
[4]
max
Max Typ
Standby I
(µA)
[4]
Max
CY62148EV30LL VFBGA Ind’l 2.2 3.0 3.6 45 2 2.5 15 20 1 7
TSOP II Ind’l/Auto-A
SOIC Ind’l 2.2 3.0 3.6 55 2 2.5 15 20 1 7
SB2
Document #: 38-05576 Rev. *G Page 2 of 12
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MoBL® CY62148EV30
Maximum Ratings
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC(min)
and 200 μs wait time after V
CC
stabilization.
8. Under DC conditions the device meets a V
IL
of 0.8V (for VCC range of 2.7V to 3.6V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to AN13470 for details.
9. Only chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to V
DC Voltage Applied to Outputs in High-Z State
[5, 6]
........................–0.3V to V
CC(max)
CC(max)
+ 0.3V
+ 0.3V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[9]
Output HIGH Vol tage
Output LOW Vol tage
Input HIGH Vol tage
Input LOW Vol tage
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
Automatic CE Power Down Current — CMOS Inputs
Automatic CE Power Down Current — CMOS Inputs
IOH = –0.1 mA 2.0 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 2.4 V
CC
IOL = 0.1 mA 0.4 0.2 V
IOL = 2.1 mA, V
V
= 2.2V to 2.7V 1.8 V
CC
> 2.70V 0.4 0.4 V
CC
VCC= 2.7V to 3.6V 2.2 V
V
= 2.2V to 2.7V For VFBGA and
CC
TSOP II package
For SOIC package –0.3 0.4
= 2.7V to 3.6V For VFBGA and
V
CC
TSOP II package
For SOIC package –0.3 0.6
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –1 +1 μA
f = f
= 1/t
max
f = 1 MHz 2 2.5 2 2.5
CE > V V
IN
f = f f = 0 (OE
– 0.2V,
CC
> V
– 0.2V, VIN < 0.2V
CC
(Address and Data Only),
max
and WE), V
RC
VCC = V I
OUT
CC(max),
= 0 mA,
CMOS levels
= 3.60V
CC
CE > VCC – 0.2V, V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
DC Input Voltage
[5, 6]
.....................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Product Range
Ambient
Temperature
CY62148EV30 Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
- 45 (Ind’l/Auto-A) - 55
Min Typ
[4]
Max Min Typ
+ 0.3V 1.8 V
CC
+ 0.3V 2.2 V
CC
[1]
[4]
Max
+ 0.3V V
CC
+ 0.3V V
CC
–0.3 0.6 V
[8]
–0.3 0.8 V
[8]
–1 +1 –1 +1 μA
15 20 15 20 mA
17 17μA
17 17μA
V
Unit
CC
V
[7]
Document #: 38-05576 Rev. *G Page 3 of 12
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MoBL® CY62148EV30
Capacitance (For All packages)
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
[10]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
[10]
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board
AC Test Loads and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
VFBGA
Package
TSOP II
Package
SOIC
Package
72 75.13 55 °C/W
8.86 8.95 22 °C/W
Unit
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[11]
t
R
[10]
VCC for Data Retention 1.5 V
[9]
Data Retention Current VCC = 1.5V, CE > VCC – 0.2V,
> VCC – 0.2V or VIN <
V
IN
0.2V
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
Data Retention Waveform
Document #: 38-05576 Rev. *G Page 4 of 12
Ind’l/Auto-A 0.8 7 μA
[4]
Max Unit
RC
ns
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MoBL® CY62148EV30
Switching Characteristics
Notes
12. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
13. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
14. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
15. The internal write time of the memory is defined by the overlap of WE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
(Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[15]
[12]
Read Cycle Time 45 55 ns
Address to Data Valid 45 55 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid 45 55 ns
OE LOW to Data Valid 22 25 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up 0 0 ns
CE HIGH to Power Up 45 55 ns
Write Cycle Time 45 55 ns
CE LOW to Write End 35 40 ns
Address Setup to Write End 35 40 ns
Address Hold from Write End 0 0 ns
Address Setup to Write Start 0 0 ns
WE Pulse Width 35 40 ns
Data Setup to Write End 25 25 ns
Data Hold from Write End 0 0 ns
WE LOW to High Z
WE HIGH to Low Z
[13]
[13, 14]
[13]
[13, 14]
[13, 14]
[13]
- 45 (Ind’l/Auto-A) - 55
[1]
Unit
Min Max Min Max
55ns
18 20 ns
10 10 ns
18 20 ns
18 20 ns
10 10 ns
Document #: 38-05576 Rev. *G Page 5 of 12
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MoBL® CY62148EV30
Switching Waveforms
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
21
Notes
16. Device is continuously selected. OE
, CE = VIL.
17. WE
is HIGH for read cycles.
18. Address valid before or similar to CE
transition LOW.
19. Data IO is high impedance if OE
= VIH.
20. If CE
goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state. Do not apply input signals.
Figure 1. Read Cycle No. 1 (Address Transition Controlled)
[16, 17]
Figure 2. Read Cycle No. 2 (OE Controlled)
[17, 18]
Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[19, 20]
Document #: 38-05576 Rev. *G Page 6 of 12
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MoBL® CY62148EV30
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA IO
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA IO
NOTE
21
Figure 4. Write Cycle No. 2 (CE Controlled)
[19, 20]
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power down Standby (ISB)
L H L Data Out Read Active (I
L H H High Z Output Disabled Active (I
L L X Data in Write Active (ICC)
Document #: 38-05576 Rev. *G Page 7 of 12
[20]
)
CC
)
CC
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MoBL® CY62148EV30
Ordering Information
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(36X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85149-*C
Speed
(ns)
Ordering Code
45 CY62148EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
CY62148EV30LL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)
CY62148EV30LL-45ZSXA 51-85095 32-pin Thin Small Outline Package II (Pb-free) Automotive-A
55 CY62148EV30LL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial
Contact your local Cypress sales representative for availability of these parts.
Package Diagram
Package Type
Package Diagrams
Figure 6. 36-ball VFBGA (6 x 8 x 1 mm) (51-85149)
Operating
Range
Document #: 38-05576 Rev. *G Page 8 of 12
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MoBL® CY62148EV30
Package Diagrams (continued)
51-85095-**
Figure 7. 32-pin TSOP II (51-85095)
Document #: 38-05576 Rev. *G Page 9 of 12
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MoBL® CY62148EV30
Package Diagrams (continued)
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
51-85081-*B
Figure 8. 32-pin (450 MIL) Molded SOIC (51-85081)
Document #: 38-05576 Rev. *G Page 10 of 12
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MoBL® CY62148EV30
Document History Page
Document Title: CY62148EV30 MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 38-05576
Revision ECN Submission
Date
** 223225 See ECN AJU New data sheet
*A 247373 See ECN SYT Changed from Advance Information to Preliminary
*B 414807 See ECN ZSD Changed from Preliminary information to Final
*C 464503 See ECN NXR Included Automotive Range in product offering
*D 833080 See ECN VKN Added footnote 8
*E 890962 See ECN VKN Removed Automotive part and its related information
Orig. of Change
Description of Change
Moved Product Portfolio to Page 2 Changed V Changed I Changed typo in Data Retention Characteristics (t Changed t Changed t 45 ns Speed Bin Changed t Speed Bin Changed t Speed Bin
stabilization time in footnote #7 from 100 μs to 200 μs
CC
from 2.0 μA to 2.5 μA
CCDR
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
HZOE
from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns
SCE
HZCE
from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for
HZWE
from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed t Changed Ordering Information to include Pb-Free Packages
from 15 to 18 ns for 35 ns Speed Bin
DOE
Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62148EV30 Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Changed ICC (max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz Changed I Changed I μA to 7 μA.
(Typ) value from 12 mA to 15 mA at f = f
CC
SB1
and I
Typ values from 0.7 μA to 1 μA and Max values from 2.5
SB2
Changed the AC test load capacitance value from 50pF to 30pF. Changed I Added I Changed t
CCDR
Changed t Changed t Changed t Changed t Updated the package diagram 36-pin VFBGA from *B to *C
from 2.5 μA to 7 μA.
CCDR
typical value.
from 3 ns to 5 ns
LZOE
and t
LZCE HZCE PWE
from 22 ns to 25 ns.
SD
LZWE
from 22 ns to 18 ns
from 30 ns to 35 ns.
from 6 ns to 10 ns
Added 32-pin SOIC package diagram and pin diagram Updated the ordering information table and replaced the Package Name column with Package Diagram.
Updated Thermal Resistance table Updated the Ordering Information
Added V
spec for SOIC package
IL
Added footnote 2 related to SOIC package Added footnote 9 related to I Added AC values for 55 ns Industrial-SOIC range
SB2
Updated Ordering Information table
) from 100 μs to t
R
max
RC
ns
Document #: 38-05576 Rev. *G Page 11 of 12
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MoBL® CY62148EV30
Document Title: CY62148EV30 MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 38-05576
Revision ECN Submission
Date
*F 987940 See ECN VKN Changed V
Orig. of Change
Description of Change
spec from 0.4V to 0.2V for SOIC package at IOL = 0.1 mA
OL
Changed V Updated footnote 8
spec from 0.6V to 0.4V for SOIC package at VCC = 2.2V to 2.7V
IL
Made footnote 9 applicable for both I
SB2
and I
CCDR
*G 2548575 08/05/08 NXR Added Auto-A information.
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05576 Rev. *G Revised August 4, 2008 Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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