CY62148ESL MoBL
®
4-Mbit (512K x 8) Static RAM
Features
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A
13
A
14
A
15
A16A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
10
A
11
A
12
A
18
Logic Block Diagram
■
Very high speed: 55 ns
■
Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
■
Ultra low standby power
❐
Typical standby current: 1 μA
❐
Maximum standby current: 7 μA
■
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 32-pin STSOP package
Functional Description
The CY62148ESL is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE
HIGH). The eight input and output pins (IO0 through IO7) are
placed in a high impedance state when the device is deselected
(CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
) inputs LOW. Data on the eight IO pins (IO0 through IO7) is
(WE
then written into the location specified on the add ress pins (A
through A18).
To read from the device, take Chip Enable (CE
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
®
) in portable
) and Output
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-50045 Rev. ** Revised January 21, 2009
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CY62148ESL MoBL
®
Pin Configuration
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
A
11
A
9
A
8
A
13
A
17
A
15
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
WE
V
CC
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
A
0
A
1
A
2
A
3
A
10
OE
CE
1
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
GND
STSOP
Top View
(not to scale)
Notes
1. Data sheet specifications are not guaranteed for V
CC
in the range of 3.6V to 4.5V.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Figure 1. 32-Pin STSOP (Top View)
Product Portfolio
Power Dissipation
Product Range VCC Range (V)
[1]
Speed
(ns)
CY62148ESL Industrial 2.2V to 3.6V and 4.5V to 5.5V 55 2 2.5 15 20 1 7
Operating ICC, (mA)
f = 1 MHz f = f
[2]
Typ
Max Typ
max
[2]
Standby, I
Max Typ
(μA)
[2]
SB2
Max
Document #: 001-50045 Rev. ** Page 2 of 10
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CY62148ESL MoBL
®
Maximum Ratings
Notes
3. V
IL
(min) = –2.0V for pulse durations less than 20 ns.
4. V
IH
(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after VCC stabilization.
6. Under DC conditions the device meets a V
IL
of 0.8V (for VCC range of 2.7V to 3.6V and 4.5V to 5.5V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic
conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. Refer to AN13470 for details.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current....................................................> 200 mA
Operating Range
Power Applied ..............................................55°C to +125°C
Supply Voltage to Ground
Potential ........................... ................................–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
[3, 4]
..........................................–0.5V to 6.0V
[3, 4]
.......................................–0.5V to 6.0V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[6]
Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4
4.5 < VCC < 5.5 IOH = –1.0 mA 2.4
Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V
2.7 < VCC < 3.6 IOL = 2.1 mA 0.4
4.5 < VCC < 5.5 IOL = 2.1 mA 0.4
Input HIGH Voltage 2.2 < VCC < 2.7 1.8 V
2.7 < VCC < 3.6 2.2 V
4.5 < VCC < 5.5 2.2 V
Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.4 V
2.7 < VCC < 3.6 –0.3 0.6
4.5 < VCC < 5.5 –0.5 0.6
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA
VCC Operating Supply
Current
Automatic CE Power
Down Current — CMOS
Inputs
Automatic CE Power
Down Current — CMOS
f = f
= 1/t
max
RC
f = 1 MHz 2 2.5
CE
> V
− 0.2V, V
CC
f = f
V
CE
f = 0, V
(Address and Data Only), f = 0 (OE and WE),
max
= V
CC
CC(max)
> VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
V
=
CC
IN
CC(max)
>
V
VCC = V
I
OUT
– 0.2V or V
CC
Inputs
Device Range
Ambient
T emperature
[5]
V
CC
CY62148ESL Industrial –40°C to +85°C 2.2V to 3.6V,
and
4.5V to 5.5V
55 ns
[2]
Max
+ 0.3 V
CC
+ 0.3
CC
+ 0.5
CC
UnitMin Typ
–1 +1 μA
CCmax
15 20 mA
= 0 mA, CMOS levels
< 0.2V,
IN
17μA
17μA
Document #: 001-50045 Rev. ** Page 3 of 10
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CY62148ESL MoBL
®
Capacitance
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalentto:
THEVENIN
EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions STSOP Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch, two layer printed
circuit board
Figure 2. AC Test Loads and Waveforms
49.02 °C/W
14.07 °C/W
Parameters 2.50V 3.0V 5.0V Unit
R1 16667 1103 1800 Ω
R2 15385 1554 990 Ω
R
V
TH
TH
8000 645 639 Ω
1.20 1.75 1.77 V
Document #: 001-50045 Rev. ** Page 4 of 10
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CY62148ESL MoBL
®
Data Retention Characteristics
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
t
R
[7]
[8]
VCC for Data Retention 1.5 V
Data Retention Current CE > VCC – 0.2V,
> VCC – 0.2V or VIN < 0.2V
V
IN
Chip Deselect to Data
V
= 1.5V 1 7 μA
CC
0ns
Retention Time
Operation Recovery Time t
RC
Data Retention Waveform
[2]
Max Unit
ns
Document #: 001-50045 Rev. ** Page 5 of 10
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CY62148ESL MoBL
®
Switching Characteristics
Notes
9. T est conditions for all p arameters other than t ri-state p arameters assume signal transit ion time of 3 ns or less (1 V/ns), ti ming reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4.
10.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
11. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
12.The internal write time of the memory is defined by the overlap of WE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Over the Operating Range
[9]
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time 55 ns
Address to Data Valid 55 ns
Data Hold from Address Change 10 ns
CE LOW to Data Valid 55 ns
OE LOW to Data Valid 25 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[10]
[10, 11]
[10]
[10, 1 1]
CE LOW to Power Up 0 ns
CE HIGH to Power Up 55 ns
[12]
Write Cycle Time 55 ns
CE LOW to Write End 40 ns
Address Setup to Write End 40 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 40 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High Z
WE HIGH to Low Z
[10, 11 ]
[10]
55 ns
Unit
Min Max
5ns
20 ns
10 ns
20 ns
20 ns
10 ns
Document #: 001-50045 Rev. ** Page 6 of 10
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CY62148ESL MoBL
®
Switching Waveforms
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
t
RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
18
Notes
13.Device is continuously selected. OE
, CE = VIL.
14.WE
is HIGH for read cycles.
15.Address valid before or similar to CE
transition LOW.
16.Data IO is high impedance if OE
= VIH.
17.If CE
goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18.During this period, the IOs are in output state. Do not apply input signals.
Figure 3. Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled)
[14, 15]
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
[16, 17]
Document #: 001-50045 Rev. ** Page 7 of 10
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CY62148ESL MoBL
®
Switching Waveforms
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA IO
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA IO
NOTE
18
(continued)
Figure 6. Write Cycle No. 2 (CE Controlled)
[16, 17]
T ruth Table
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power Down Standby (I
L H L Data Out Read Active (I
L H H High Z Output Disabled Active (I
L L X Data in Write Active (I
CC
CC
CC
SB
)
)
)
)
Document #: 001-50045 Rev. ** Page 8 of 10
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CY62148ESL MoBL
®
Ordering Information
51-85094-*D
Speed
(ns)
55 CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-Free) Industrial
Ordering Code
Package
Diagram
Package Type
Package Diagram
Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
Operating
Range
Document #: 001-50045 Rev. ** Page 9 of 10
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CY62148ESL MoBL
®
Document History Page
Document Title: CY62148ESL MoBL® 4-Mbit (512K x 8) Static RAM
Document Number: 001-50045
Rev. ECN No. Orig. of
Change
Submission
Date
Description of Change
** 2612938 VKN/PYRS 01/21/09 New data sheet
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied i n a Cypress product. Nor do es it convey or imply a ny license under pa tent or other right s. Cypress product s are not warra nted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/ or firm ware) i s own ed by Cypre ss Se micond ucto r Corp oratio n (Cy press ) and is pr otec ted by and s ubj ect to worldwide patent protection (United States and foreign),
United States co pyri ght la ws and inte rnati ona l t reaty p rovis ions. Cyp ress he reby gr ant s to licensee a per sonal , non- exclu siv e, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpos e of creating custom sof tware and or firm ware in support of li censee product to be use d only in conjuncti on with a Cypress
integrated circuit as specified i n the applicable agreement. Any reproductio n, modification, translation , compilation, o r represent ation of this So urce Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the ap plic ation or use o f an y product o r c ircuit describe d her ein. Cypress d oes not aut hori ze it s product s fo r use as critical component s in life-sup port systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-50045 Rev. ** Revised January 21, 2009 Page 10 of 10
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
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