CY62148E MoBL
®
4-Mbit (512K x 8) Static RAM
Features
• Very high speed: 45 ns
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62148B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA (Industrial)
• Ultra low active power
— Typical active current: 2.0 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin TSOP II and 32-pin SOIC
packages
, and OE features
[2]
Functional Description
[1]
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
The eight input and output pins (IO
through IO7) are placed
0
HIGH).
in a high impedance state when:
• Deselected (CE
HIGH)
• Outputs are disabled (OE HIGH)
• Write operation is active (CE
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. Data on the eight IO pins (IO0 through IO7)
LOW and WE LOW)
) and Write Enable
is then written into the location specified on the address pins
(A
through A18).
0
To read from the device, take Chip Enable (CE) and Output
Enable (OE
) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Product Portfolio
Power Dissipation
Product Range VCC Range (V)
Min Typ
[3]
Max Typ
CY62148ELL TSOP II Ind’l 4.5 5.0 5.5 45 2 2.5 15 20 1 7
CY62148ELL SOIC Ind’l/Auto-A 4.5 5.0 5.5 55 2 2.5 15 20 1 7
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
2. SOIC package is available only in 55 ns speed bin.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Speed
(ns)
Operating ICC (mA)
f = 1MHz f = f
[3]
Max Typ
CC
= V
[3]
CC(typ)
Standby I
max
Max Typ
, TA = 25°C.
SB2
[3]
(µA)
Max
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05442 Rev. *F Revised March 28, 2007
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Logic Block Diagram
CE
WE
OE
CY62148E MoBL
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
A
A
9
10
11
12
ROW DECODER
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
15
13
14
A
A
A16A
A
SENSE AMPS
POWER
DOWN
17
18
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
®
Pin Configuration
[2, 4]
32-pin SOIC/TSOP II Pinout
Top View
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
A
30
18
29
WE
A
28
13
A
8
27
A
26
9
A
25
11
24
OE
A
23
10
22
CE
21
IO
7
IO
20
6
IO
19
5
18
IO
4
17
IO
3
Note
4. NC pins are not connected on the die.
Document #: 38-05442 Rev. *F Page 2 of 10
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CY62148E MoBL
[5, 6]
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ......................................................>200mA
Operating Range
Supply Voltage to Ground
Potential.................................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
................–0.5V to 6.0V (V
CCmax
CCmax
+ 0.5V)
+ 0.5V)
Device Range
CY62148E Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
Output HIGH
Volta ge
Output LOW Voltage IOL = 2.1 mA 0.4 0.4 V
Input HIGH Voltage V
Input LOW voltage V
IOH = –1 mA 2.4 2.4 V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V For TSOPII
CC
package
For SOIC
package
I
IX
I
OZ
I
CC
[9]
I
SB2
Capacitance (For All Packages)
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE Power
down Current —
CMOS Inputs
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
f = f
= 1/t
max
RC
f = 1 MHz 2 2.5 2 2.5
CE
> VCC – 0.2V
V
> VCC – 0.2V or V
IN
f = 0, V
[10]
CC
= V
CC(max)
VCC = V
I
CMOS levels
OUT
IN
CC(max)
= 0 mA
< 0.2V,
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
CC(typ)
Min Typ
–0.5 0.8 V
–1 +1 –1 +1 µA
............ –0.5V to 6.0V (V
Ambient
Tem per atu re
45 ns 55 ns
[3]
Max Min Typ
+ 0.5 2.2 V
CC
[2]
[3]
–0.5 0.6
15 20 15 20 mA
17 17µA
10 pF
CCmax
Max
+ 0.5 V
CC
[8]
+ 0.5V)
V
CC
®
[7]
Unit
Notes
5. V
6. V
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
8. Under DC conditions the device meets a V
9. Only chip enable (CE
10. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= VCC+0.75V for pulse durations less than 20 ns.
IH(max)
of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This
is applicable to SOIC package only. Refer to AN13470 for details.
) must be HIGH at CMOS level to meet the I
IL
Document #: 38-05442 Rev. *F Page 3 of 10
(min) and 200 µs wait time after V
CC
spec. Other inputs can be left floating.
SB2
stabilization.
CC
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CY62148E MoBL
®
Thermal Resistance
[10]
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
SCOPE
Parameters 5.0V Unit
R1
3.0V
30 pF
R2
GND
Rise Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
R
OUTPUT V
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
639 Ω
1.77 V
ALL INPUT PULSES
10%
TH
90%
SOIC
Package
TSOP II
Package
75 77 °C/W
10 13 °C/W
90%
10%
Fall Time = 1 V/ns
Unit
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
t
R
[10]
[11]
VCC for Data Retention 2 V
Data Retention Current VCC= VDR, CE > VCC – 0.2V,
> VCC – 0.2V or VIN < 0.2V
V
IN
Ind’l/Auto-A 1 7 µA
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
RC
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
Note
11. Full device operation requires linear V
ramp from V
CC
V
CC(min)
t
CDR
DR
to V
> 100 µs or stable at V
CC(min)
VDR> 2.0V
CC(min)
> 100 µs.
V
CC(min)
t
R
[3]
Max Unit
ns
Document #: 38-05442 Rev. *F Page 4 of 10
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CY62148E MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[15]
Read Cycle Time 45 55 ns
Address to Data Valid 45 55 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[13]
[13, 14]
[13]
[13, 14]
CE LOW to Power up
CE HIGH to Power down
Write Cycle Time 45 55 ns
CE LOW to Write End
Address Setup to Write End 35 40 ns
Address Hold from Write End 0 0 ns
Address Setup to Write Start 0 0 ns
WE Pulse Width
Data Setup to Write End 25 25 ns
Data Hold from Write End 0 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[13, 14]
[13]
[12]
45 ns 55 ns
[2]
Unit
Min Max Min Max
45 55 ns
22 25 ns
55ns
18 20 ns
10 10 ns
18 20 ns
00ns
45 55 ns
35 40 ns
35 40 ns
18 20 ns
10 10 ns
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0 to 3V, and output loading of the specified I
13. At any given temperature and voltage condition, t
, t
14. t
HZOE
15. The internal write time of the memory is defined by the overlap of WE
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZCE
, and t
transitions are measured when the outputs enter a high impedance state.
HZWE
Document #: 38-05442 Rev. *F Page 5 of 10
as shown in the “AC Test Loads and Waveforms” on page 4.
OL/IOH
is less than t
HZCE
, t
LZCE
is less than t
HZOE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
LZOE
, and t
is less than t
HZWE
for any given device.
LZWE
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[16, 17]
t
AA
CY62148E MoBL
tRC
RC
®
Read Cycle No. 2 (OE Controlled)
[17, 18]
ADDRESS
t
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZCE
t
PU
50%
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
ADDRESS
t
SCE
CE
RC
[19, 20]
t
WC
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
I
CC
50%
I
SB
t
SA
WE
OE
21
DATA IO
Notes:
16. Device is continuously selected. OE
is HIGH for read cycles.
17. WE
18. Address valid before or similar to CE
19. Data IO is high impedance if OE
goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
20. If CE
21. During this period, the IOs are in output state and input signals must not be applied.
NOTE
t
HZOE
, CE = VIL.
transition LOW.
= VIH.
Document #: 38-05442 Rev. *F Page 6 of 10
t
AW
t
PWE
t
SD
t
HA
t
HD
DATA VALID
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
[19, 20]
CY62148E MoBL
t
WC
t
SCE
t
SA
t
AW
t
PWE
t
HA
®
DATA IO
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
t
SA
WE
21
DATA IO
NOTE
t
HZWE
Truth Table
[20]
t
SD
DATA VALID
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HD
t
HA
t
LZWE
t
HD
CE WE OE IO’s Mode Power
H X X High Z Deselect/Power down Standby (I
L H L Data Out Read Active (I
L L X Data In Write Active (I
L H H High Z Selected, Outputs Disabled Active (I
Document #: 38-05442 Rev. *F Page 7 of 10
CC
CC
CC
SB
)
)
)
)
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CY62148E MoBL
Ordering Information
Speed
(ns)
45 CY62148ELL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free) Industrial
55 CY62148ELL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial
55 CY62148ELL-55SXA 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Ordering Code
Package Diagrams
Figure 1. 32-pin TSOP II, 51-85095
Package
Diagram
Package Type
Operating
®
Range
Document #: 38-05442 Rev. *F Page 8 of 10
51-85095-**
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Package Diagrams (continued)
Figure 2. 32-pin (450 MIL) Molded SOIC, 51-85081
17 32
116
0.440[11.176]
0.450[11.430]
0.546[13.868]
0.566[14.376]
CY62148E MoBL
®
0.101[2.565]
0.111[2.819]
0.050[1.270]
BSC.
0.793[20.142]
0.817[20.751]
0.014[0.355]
0.020[0.508]
0.004[0.102]
SEATING PLANE
MIN.
0.118[2.997]
MAX.
0.004[0.102]
0.006[0.152]
0.012[0.304]
0.023[0.584]
0.039[0.990]
0.047[1.193]
0.063[1.600]
51-85081-*B
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05442 Rev. *F Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY62148E MoBL®, 4-Mbit (512K x 8) Static RAM
Document Number: 38-05442
REV. ECN NO.
Issue
Date
** 201580 01/08/04 AJU New Data Sheet
*A 249276 See ECN SYT Changed from Advance Information to Preliminary
*B 414820 See ECN ZSD Changed from Preliminary to Final
*C 464503 See ECN NXR Included Automotive Range in product offering
*D 485639 See ECN VKN Corrected the operating range to 4.5V - 5.5V on page# 3
*E 833080 See ECN VKN Added footnote #8
*F 890962 See ECN VKN Added Automotive-A part and its related information
Orig. of
Change
Description of Change
Moved Product Portfolio to Page 2
Added RTSOP II and Removed FBGA Package
Changed V
Changed I
Changed typo in Data Retention Characteristics(t
Changed t
Changed t
ns Speed Bin
Changed t
Bin
Changed t
Speed Bin
Changed t
45 ns Speed Bin
Changed t
Corrected typo in Package Name
stabilization time in footnote #7 from 100 µs to 200 µs
CC
from 2.0 µA to 2.5 µA
CCDR
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
HZOE
from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed
SCE
HZCE
from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
SD
from 15 to 18 ns for 35 ns Speed Bin
DOE
from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45
HZWE
from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Changed Ordering Information to include Pb-Free Packages
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62148E
Changed I
Changed I
Changed I
Removed I
Changed I
Modified footnote #4 to include current limit
(Typ) value from 1.5 mA to 2 mA at f=1 MHz
CC
(Max) value from 2 mA to 2.5 mA at f=1 MHz
CC
(Typ) value from 12 mA to 15 mA at f=f
CC
spec from the Electrical characteristics table
SB1
Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA
SB2
Removed redundant footnote on DNU pins
Changed the AC testload capacitance from 100 pF to 30 pF on page #4
Changed test load parameters R1, R2, R
645 Ω and 1.75V to 1800 Ω, 990 Ω, 639 Ω and 1.77V
Changed I
Added I
Changed t
CCDR
Changed t
Changed t
Changed t
Changed t
Updated the ordering information table and replaced Package Name column with
from 2.5 µA to 7 µA
CCDR
typical value
from 3 ns to 5 ns
LZOE
and t
LZCE
HZCE
PWE
from 22 ns to 25 ns
SD
LZWE
from 22 ns to 18 ns
from 30 ns to 35 ns
from 6 ns to 10 ns
and VTH from 1838 Ω, 994 Ω,
TH
Package Diagram
Updated the Ordering Information
Added V
spec for SOIC package
IL
Removed Automotive-E part and its related information
Added footnote #2 related to SOIC package
Added footnote #9 related to I
Added AC values for 55 ns Industrial-SOIC range
SB2
Updated Ordering Information table
CY62148E MoBL
) from 100 µs to t
R
max
RC
ns
®
Document #: 38-05442 Rev. *F Page 10 of 10
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