CY62147EV30 MoBL
®
4-Mbit (256K x 16) Static RAM
Features
256K x 16
RAM Array
IO0–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
CE
[1]
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE
refers to the internal logical combination of CE1 and
CE
2
such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
■
Very high speed: 45 ns
■
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive-A: –40°C to +85°C
❐
Automotive-E: –40°C to +125°C
■
Wide voltage range: 2.20V to 3.60V
■
Pin compatible with CY62147DV30
■
Ultra low standby power
❐
Typical standby current: 1 μA
❐
Maximum standby current: 7 μA (Industrial)
■
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 48-ball VFBGA (single/dual CE option) and
[1]
and OE features
44-pin TSOPII packages
■
Byte power down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
®
ideal for providing More Battery Life™ (MoBL
) in portable applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE
HIGH). The input and output pins (IO
in a high impedance state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
HIGH or both BLE and BHE are
through IO15) are placed
0
To write to the device, take Chip Enable (CE) and Write Enable
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
(WE
from IO pins (IO
specified on the address pins (A
Enable (BHE
through IO7) is written into the location
0
) is LOW, then data from IO pins (IO8 through IO15)
through A17). If Byte High
0
is written into the location specified on the address pins (A
through A17).
To read from the device, take Chip Enable (CE
Enable (OE
Byte Low Enable (BLE
) LOW while forcing the Write Enable (WE) HIGH. If
) is LOW, then data from the memory
location specified by the address pins appear on IO
Byte High Enable (BHE
appears on IO
complete description of read and write modes.
to IO15. See the Truth Table on page 9 for a
8
) is LOW, then data from memory
) and Output
to IO7. If
0
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05440 Rev. *G Revised March 31, 2009
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CY62147EV30 MoBL
®
Product Portfolio
WE
A
11
A
10
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
NC
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
CE
2
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC
NC
326
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°.
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Product Range VCC Range (V)
Min Typ
[2]
Max Typ
Speed
(ns)
Operating ICC (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
max
Max Typ
Standby I
[2]
SB2
CY62147EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Auto-E 2.2 3.0 3.6 55 ns 2 3 15 25 1 20
Pin Configuration
Power Dissipation
Figure 1. 48-Ball VFBGA (Single Chip Enable)
[3, 4]
Figure 2. 48-Ball VFBGA (Dual Chip Enable)
[3, 4]
(μA)
Max
Figure 3. 44-Pin TSOP II
Document #: 38-05440 Rev. *G Page 2 of 13
[3]
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CY62147EV30 MoBL
®
Maximum Ratings
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
8. Only chip enable (CE
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Teste d i nitially and after any design or process changes that may affect these parameters.
Exceeding the maximum ratings may imp air the usef ul life of the
device. User guidelines are not tested .
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ..........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
...............–0.3V to 3.9V (V
CCmax
CCmax
+ 0.3V)
+ 0.3V)
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[8]
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power Down
Current —
CMOS Inputs
Automatic CE
Power Down
Current —
CMOS Inputs
IOH = –0.1 mA 2.0 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 2.4 V
CC
IOL = 0.1 mA 0.4 0.4 V
I
= 2.1 mA, V
OL
V
= 2.2V to 2.7V 1.8 V
CC
V
= 2.7V to 3.6V 2.2 V
CC
V
= 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
V
CC
GND < VI < V
= 2.70V 0.4 0.4 V
CC
CC
GND < VO < VCC, Output Disabled –1 +1 –4 +4 μA
f = f
= 1/tRCVCC = V
max
f = 1 MHz 2 2.5 2 3
I
OUT
CMOS levels
CC(max)
= 0 mA
CE > VCC – 0.2V
> V
V
IN
f = f
f = 0 (OE
V
CC
CE
> VCC – 0.2V
V
IN
f = 0, V
– 0.2V, VIN < 0.2V
CC
(Address and Data Only),
max
, BHE, BLE and WE),
= 3.60V
> VCC – 0.2V or VIN < 0.2V,
= 3.60V
CC
DC Input Voltage
............–0.3V to 3.9V (V
CCmax
+ 0.3V)
[5, 6]
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Device Range
Ambient
Temperature
CY62147EV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to
Auto-E –40°C to +125°C
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[2]
Max Min Typ
+ 0.3 1.8 V
CC
+ 0.3 2.2 V
CC
[2]
Max
+ 0.3 V
CC
+ 0.3 V
CC
–1 +1 –4 +4 μA
15 20 15 25 mA
17 120μA
17 120μA
V
CC
3.6V
[7]
Unit
Capacitance
For all packages.
[9]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document #: 38-05440 Rev. *G Page 3 of 13
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
10 pF
V
= V
CC
CC(typ)
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CY62147EV30 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
ALL INPUT PULSES
R
TH
R1
Equivalent to: THEVENIN EQUIVALENT
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE
.BLE
Notes
10.Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
[9]
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
Figure 4. AC Test Load and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
VFBGA
Package
TSOP II
Package
75 77 °C/W
10 13 °C/W
Unit
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
[8]
I
CCDR
[9]
t
CDR
[10]
t
R
Document #: 38-05440 Rev. *G Page 4 of 13
VCC for Data Retention 1.5 V
Data Retention Current VCC= 1.5V , CE > VCC – 0.2V ,
V
> VCC – 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
[1, 11]
Figure 5. Data Retention Waveform
[2]
Max Unit
Ind’l/Auto-A 0.8 7 μA
Auto-E 12
RC
ns
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CY62147EV30 MoBL
®
Switching Characteristics
Notes
12.Test conditions for all parameters other than tri-st ate p arameters assume signal tr ansition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 4.
13.AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14.At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
16.The internal write time of the memory is defined by the overlap of WE
, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Over the Operating Range
[12, 13]
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[16]
Read Cycle Time 45 55 ns
Address to Data Valid 45 55 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid 45 55 ns
OE LOW to Data Valid 22 25 ns
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up 0 0 ns
CE HIGH to Power Down 45 55 ns
BLE/BHE LOW to Data V alid 45 55 ns
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write Cycle Time 45 55 ns
CE LOW to Write End 35 40 ns
Address Setup to Write End 35 40 ns
Address Hold from Write End 0 0 ns
Address Setup to Write Start 0 0 ns
WE Pulse Width 35 40 ns
BLE/BHE LOW to Write End 35 40 ns
Data Setup to Write End 25 25 ns
Data Hold from Write End 0 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[14]
[14, 15]
[14]
[14, 15]
[14, 15]
[14]
[14]
[14, 15]
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Unit
Min Max Min Max
55ns
18 20 ns
10 10 ns
18 20 ns
10 10 ns
18 20 ns
18 20 ns
10 10 ns
Document #: 38-05440 Rev. *G Page 5 of 13
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CY62147EV30 MoBL
®
Switching Waveforms
PREVIOUS DATA VALID DA TA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE
/BLE
ADDRESS
Notes
17.The device is continuously selected. OE
, CE = VIL, BHE, BLE, or both = VIL.
18.WE
is HIGH for read cycle.
19.Address valid before or similar to CE
and BHE, BLE transition LOW.
Figure 6. Read Cycle No. 1 (Address Transition Controlled)
[17, 18]
Figure 7. Read Cycle No. 2 (OE Controlled)
[1, 18, 19]
Document #: 38-05440 Rev. *G Page 6 of 13
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CY62147EV30 MoBL
®
Switching Waveforms
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
t
HZOE
DATA
IN
NOTE 22
t
BW
t
SCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
t
BW
t
SA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 22
(continued)
Figure 8. Write Cycle No. 1 (WE
Controlled)
[1, 16, 20, 21]
Figure 9. Write Cycle No. 2 (CE Controlled)
[1, 16, 20, 21]
Document #: 38-05440 Rev. *G Page 7 of 13
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CY62147EV30 MoBL
®
Switching Waveforms
DATAIN
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 22
CE
ADDRESS
WE
DATA IO
BHE
/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA
IN
t
BW
t
SCE
t
PWE
t
HZWE
t
LZWE
NOTE 22
DATA IO
ADDRESS
CE
WE
BHE/BLE
Notes
20.Data I/O is high impedance if OE
= VIH.
21.If CE
goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
22.During this period, the IOs are in output state. Do not apply input signals.
(continued)
Figure 10. Write Cycle No. 3 (WE
Controlled, OE LOW)
[1, 21]
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
Document #: 38-05440 Rev. *G Page 8 of 13
[1, 21]
[+] Feedback
CY62147EV30 MoBL
®
Truth Table
Notes
23.This BGA package is offered with single chip enable.
24.This BGA package is offered with dual chip enable.
[1]
CE
WE OE BHE BLE
H X X X X High Z Deselect/Power Down Standby (I
L X X H H High Z Deselect/Power Down Standby (ISB)
L H L L L Data Out (IO0–IO15) Read Active (ICC)
L H L H L Data Out (IO0–IO7);
–IO
IO
8
L H L L H Data Out (IO
IO
–IO7 in High Z
0
L H H L L High Z Output Disabled Active (I
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (IO
L L X H L Data In (IO0–IO7);
IO
–IO
8
L L X L H Data In (IO
IO
–IO7 in High Z
0
IOs Mode Power
Read Active (I
in High Z
15
–IO15);
8
–IO15) Write Active (ICC)
0
Read Active (I
Write Active (I
in High Z
15
–IO15);
8
Write Active (I
CC
CC
CC
CC
CC
SB
)
)
)
)
)
)
Ordering Information
Speed
(ns)
Ordering Code
45 CY62147EV30LL-45BVI 51-85150 48-Ball Very Fine Pitch Ball Grid Array
CY62147EV30LL-45BVXI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
CY62147EV30LL-45B2XI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
CY62147EV30LL-45ZSXI 51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
CY62147EV30LL-45BVXA 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
CY62147EV30LL-45ZSXA 51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
55 CY62147EV30LL-55ZSXE 51-85087 44-Pin Thin Small Ou tline Package II (Pb-Free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package
Diagram
Package Type
[23]
[23]
[24]
[23]
Operating
Range
Industrial
Automotive-A
Document #: 38-05440 Rev. *G Page 9 of 13
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CY62147EV30 MoBL
®
Package Diagrams
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
Document #: 38-05440 Rev. *G Page 10 of 13
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CY62147EV30 MoBL
®
Package Diagrams
51-85087-*A
(continued)
Figure 13. 44-Pin TSOP II, 51-85087
Document #: 38-05440 Rev. *G Page 11 of 13
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CY62147EV30 MoBL
®
Document History Page
Document Title: CY62147EV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05440
Rev . ECN No.
Orig. of
Change
** 201861 AJU 01/13/04 New Data Sheet
*A 247009 SYT See ECN Changed from Advanced Information to Preliminary
*B 414807 ZSD See ECN Changed from Preliminary information to Final
*C 464503 NXR See ECN Included Automotive Range in product offering
*D 925501 VKN See ECN Added Preliminary Automotive-A information
*E 1045701 VKN See ECN Converted Automotive-A and Automotive -E specs from preliminary to final
*F 2577505 VKN/PYRS 10/03/08 Added -45B2XI part (Dual CE option)
*G 2681901 VKN/PYRS 04/01/09 Added CY62147EV30LL-45ZSXA in the ordering information table
Submission
Date
Description of Change
Moved Product Portfolio to Page 2
Changed Vcc stabilization time in footnote #8 from 100 μs to 200 μs
Removed Footnote #15(t
Changed I
Changed typo in Data Retention Characteristics(t
Changed t
Changed t
18 ns for 45 ns Speed Bin
Changed t
for 45 ns Speed Bin
Changed t
Speed Bin
from 2.0 μA to 2.5 μA
CCDR
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
HZOE
HZBE
and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
SCE
from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
HZCE
) from Previous Revision
LZBE
) from 100 μs to t
R
, t
from 12 to 15 ns for 35 ns Speed Bin and 15 to
HZWE
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed t
Changed Ordering Information to include Pb-Free Packages
from 15 to 18 ns for 35 ns Speed Bin
DOE
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62147EV30
Changed ball E3 from DNU to NC.
Removed redundant foot note on DNU.
Changed I
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = f
Changed I
2.5 μA to 7 μA.
Changed I
Added I
Changed AC test load capacitance from 50 pF to 30 pF on Page #4.
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the package diagram 48-pin VFBGA from *B to *D
(Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
CC
and I
SB1
CCDR
CCDR
LZOE
LZCE
HZCE
PWE
SD
SB2
from 2.5 μA to 7 μA.
typical value.
from 3 ns to 5 ns
, t
LZBE
from 22 ns to 18 ns
from 30 ns to 35 ns.
from 22 ns to 25 ns.
Typ values from 0.7 μA to 1 μA and Max values from
and t
from 6 ns to 10 ns
LZWE
max
Updated the ordering information table and replaced the Package Name column
with Package Diagram.
Updated the Ordering Information
Added footnote #9 related to I
Added footnote #14 related AC timing parameters
SB2
and I
CCDR
RC
ns
Document #: 38-05440 Rev. *G Page 12 of 13
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Document #: 38-05440 Rev. *G Revised March 31, 2009 Page 13 of 13
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