CY62146EV30 MoBL
®
4-Mbit (256K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
, and OE features
[1]
®
) in
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE
IO
) are placed in a high impedance state when:
15
HIGH). The input and output pins (IO0 through
• Deselected (CE HIGH)
• Outputs are disabled (OE
HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH)
• Write operation is active (CE
LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE
then data from IO pins (IO
location specified on the address pins (A
High Enable (BHE
) inputs LOW. If Byte Low Enable (BLE) is LOW,
through IO7), is written into the
0
through A17). If Byte
0
) is LOW, then data from IO pins (IO
through IO15) is written into the location specified on the
address pins (A
Read from the device by taking Chip Enable (CE
Enable (OE
If Byte Low Enable (BLE
location specified by the address pins appear on IO
Byte High Enable (BHE
appears on IO
through A17).
0
) and Output
) LOW while forcing the Write Enable (WE) HIGH.
) is LOW, then data from the memory
to IO7. If
0
) is LOW, then data from memory
to IO15. See the “Truth Table” on page 9 for a
8
complete description of read and write modes.
8
Product Portfolio
Power Dissipation
Product VCC Range (V)
Min Typ
[2]
Max Typ
CY62146EV30LL 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05567 Rev. *C Revised March 26, 2007
Speed
(ns)
Operating ICC (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
CC
max
Max Typ
= V
CC(typ)
Standby I
, TA = 25°C.
(µA)
SB2
[2]
Max
Logic Block Diagram
CY62146EV30 MoBL
®
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
IO
–IO
0
IO8–IO
7
15
COLUMN DECODER
BHE
WE
11
13
15
A12A
14
A
A
17
16
A
A
A
CE
OE
BLE
Pin Configurations
BLE
IO
IO
V
SS
V
CC
IO
IO
NC
[3, 4]
48-ball VFBGA
OE
BHE
8
IO
10
9
IO
11
IO
12
IO
13
14
NC
15
A
8
Top Vi e w
41
326
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
5
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
IO
IO
IO
IO
WE
A
NC
2
IO
IO
1
V
3
V
4
IO
5
11
CC
IO
NC
SS
A
B
0
C
2
D
E
F
6
G
7
H
44-pin TSOP II
A
1
4
A
2
3
A
3
2
A
4
1
A
5
0
6
CE
IO
7
0
IO
8
1
IO
9
2
IO
10
3
V
11
CC
V
12
SS
IO
13
4
IO
14
5
IO
15
6
IO
16
7
17
WE
A
18
17
A
16
19
A
15
20
A
14
21
A
13
22
Top Vi e w
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
IO
14
IO
IO
V
SS
V
CC
IO
11
IO
IO
IO
8
NC
A
8
A
9
A
10
A
11
A
12
15
13
12
10
9
Notes:
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
Document #: 38-05567 Rev. *C Page 2 of 12
CY62146EV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
................–0.3V to 3.9V (V
CCmax
CCmax
+ 0.3V)
+ 0.3V)
Device Range
CY62146EV30 Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1 mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
V
= 2.7V to 3.6V 2.2 V
CC
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current f = f
Automatic CE Power down
Current — CMOS Inputs
= 1/t
max
f = 1 MHz 2 2.5
> VCC−0.2V,
CE
V
> VCC–0.2V or V
IN
f = f
f = 0 (OE
(Address and Data Only),
max
, BHE, BLE and WE), V
RC
VCC = V
I
= 0 mA
OUT
CMOS levels
< 0.2V
IN
CC(max),
CC
[5, 6]
........... –0.3V to 3.9V (V
Temperature V
–1 +1 µA
= 3.60V
CC max
Ambient
45 ns
[2]
Max
+ 0.3 V
CC
+ 0.3 V
CC
15 20 mA
17µA
+ 0.3V)
[7]
CC
UnitMin Typ
I
SB2
[8]
Automatic CE Power down
Current — CMOS Inputs
Notes:
5. V
6. V
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
8. Only chip enable (CE
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V
IH(max)
+ 0.75V for pulse durations less than 20 ns.
CC
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
Document #: 38-05567 Rev. *C Page 3 of 12
CE
> VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
(min) and 200 µs wait time after V
cc
SB2
17µA
stabilization.
cc
/ I
spec. Other inputs can be left floating.
CCDR
CY62146EV30 MoBL
®
Capacitance (For All Packages)
[9]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Thermal Resistance
Parameter Description Test Conditions
Θ
Θ
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
[9]
CC(typ)
VFBGA
Package
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 °C/W
10 13 °C/W
10 pF
TSOP II
Package Unit
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
SCOPE
30 pF
R1
VCC
10%
R2
Rise Time = 1 V/ns
GND
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[10]
t
R
[9]
VCC for Data Retention 1.5 V
[8]
Data Retention Current V
= 1.5V, CE > VCC – 0.2V,
CC
V
> VCC – 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
RC
Data Retention Waveform
DATA RETENTION MODE
V
V
CC
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device operation requires linear V
ramp from V
CC
CC(min)
t
CDR
DR
to V
> 100 µs or stable at V
CC(min)
VDR> 1.5V
CC(min)
> 100 µs.
V
CC(min)
t
R
[2]
Max Unit
0.8 7 µA
ns
Document #: 38-05567 Rev. *C Page 4 of 12
CY62146EV30 MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[15]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
[13]
[13, 14]
[13]
[13, 14]
CE LOW to Power Up
CE HIGH to Power Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low-Z
BLE / BHE HIGH to High-Z
[13]
[13, 14]
Write Cycle Time 45 ns
CE LOW to Write End
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width
BLE / BHE LOW to Write End
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[13, 14]
[13]
[11, 12]
45 ns
UnitMin Max
45 ns
22 ns
5ns
18 ns
10 ns
18 ns
0ns
45 ns
22 ns
5ns
18 ns
35 ns
35 ns
35 ns
18 ns
10 ns
otes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
pulse levels of 0 to V
12. AC timing parameters are subject to byte enable signals (BHE
clarification.
13. At any given temperature and voltage condition, t
given device.
14. t
, t
HZCE
, t
HZBE
HZOE
15. The internal write time of the memory is defined by the overlap of WE
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
CC(typ)
, and t
transitions are measured when the outputs enter a high impedence state.
HZWE
Document #: 38-05567 Rev. *C Page 5 of 12
is less than t
HZCE
/2, input
CC(typ)
or BLE) not switching when chip is disabled. Please see application note AN13842 for further
, t
LZCE
, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
is less than t
HZBE
LZBE
, t
HZOE
is less than t
LZOE
, and t
is less than t
HZWE
LZWE
for any
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[16, 17]
CY62146EV30 MoBL
t
RC
t
AA
®
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
/BLE
BHE
DATA OUT
V
CC
HIGH IMPEDANCE
t
LZCE
t
PU
SUPPLY
CURRENT
t
LZBE
[17, 18]
t
ACE
t
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZOE
t
HZBE
HIGH
IMPEDANCE
DATA VALID
I
50%
CC
I
SB
Notes:
16. The device is continuously selected. OE
is HIGH for read cycle.
17. WE
18. Address valid before or similar to CE
, CE = VIL, BHE and/or BLE = VIL.
and BHE, BLE transition LOW.
Document #: 38-05567 Rev. *C Page 6 of 12
Switching Waveforms (continued)
Write Cycle No. 1 (WE
ADDRESS
CE
Controlled)
[15, 19, 20]
t
SCE
t
WC
CY62146EV30 MoBL
®
WE
BHE/BLE
OE
DATA IO
NOTE 21
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
t
SA
t
HZOE
[15, 19, 20]
t
AW
t
PWE
t
BW
t
SD
DATA
IN
t
WC
t
SCE
t
SA
t
AW
t
PWE
t
HA
t
HD
t
HA
BHE/BLE
OE
DATA IO
Notes:
19. Data IO is high impedance if OE
20. If CE
goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
21. During this period, the IOs are in output state and input signals must not be applied.
NOTE 21
= VIH.
t
HZOE
Document #: 38-05567 Rev. *C Page 7 of 12
t
BW
t
SD
DATA
t
HD
IN
Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
BHE
/BLE
Controlled, OE LOW)
[20]
t
t
SCE
BW
CY62146EV30 MoBL
t
WC
®
t
SA
WE
DATA IO
NOTE 21
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
BHE/BLE
t
SA
WE
t
HZWE
DATA IO
NOTE 21
[20]
t
AW
t
PWE
t
SD
t
HA
t
HD
DATAIN
t
LZWE
t
WC
t
SCE
t
AW
t
BW
t
PWE
t
SD
DATA
IN
t
HA
t
HD
Document #: 38-05567 Rev. *C Page 8 of 12
t
LZWE
CY62146EV30 MoBL
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power down Standby (I
L X X H H High-Z Output Disabled Active (I
L H L L L Data Out (IO
L H L H L Data Out (IO
IO
–IO
8
L H L L H Data Out (IO8–IO15);
IO
–IO7 in High-Z
0
L H H L L High-Z Output Disabled Active (ICC)
L H H H L High-Z Output Disabled Active (I
L H H L H High-Z Output Disabled Active (I
L L X L L Data In (IO
L L X H L Data In (IO
–IO
IO
8
L L X L H Data In (IO
IO
–IO7 in High-Z
0
Ordering Information
Speed
(ns) Ordering Code
45 CY62146EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62146EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of other parts
Package
Diagram Package Type
–IO15) Read Active (ICC)
0
in High-Z
15
–IO7);
0
Read Active (I
Read Active (I
–IO15) Write Active (ICC)
0
0
in High-Z
15
8
–IO7);
–IO15);
Write Active (I
Write Active (I
)
SB
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
Operating
Range
®
Document #: 38-05567 Rev. *C Page 9 of 12
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
CY62146EV30 MoBL
®
0.25 C
8.00±0.10
A
0.55 MAX.
0.26 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
A
B
SEATING PLANE
C
6.00±0.10
0.21±0.05
0.10 C
0.75
5.25
8.00±0.10
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
6.00±0.10
3.75
A1 CORNER
234
1
A
B
C
D
E
F
G
H
51-85150-*D
1.00 MAX
Document #: 38-05567 Rev. *C Page 10 of 12
Package Diagrams (continued)
Figure 2. 44-pin TSOP II, 51-85087
CY62146EV30 MoBL
®
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05567 Rev. *C Page 11 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Document History Page
Document Title:CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
REV. ECN NO. Issue Date
** 223225 See ECN AJU New Data Sheet
*A 247373 See ECN SYT Changed Advance Information to Preliminary
*B 414807 See ECN ZSD Changed from Preliminary information to Final
*C 925501 See ECN VKN Added footnote #8 related to I
Orig. of
Change Description of Change
Moved Product Portfolio to Page 2
Changed V
Removed Footnote #14(t
Changed I
Changed typo in Data Retention Characteristics(t
Changed t
Changed t
18 ns for 45 ns Speed Bin
Changed t
for 45 ns Speed Bin
Changed t
ns Speed Bin
stabilization time in footnote #8 from 100 µs to 200 µs
CC
from 2.0 µA to 2.5 µA
CCDR
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
HZOE
HZBE
and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
SCE
from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45
HZCE
) from Previous revision
LZBE
, t
from 12 to 15 ns for 35 ns Speed Bin and 15 to
HZWE
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed t
Changed t
Changed Ordering Information to include Pb-Free Packages
from 15 to 18 ns for 35 ns Speed Bin
DOE
from 15 to 18 ns for 35 ns Speed Bin
DBE
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed I
1.5 mA to 2 mA at f=1 MHz
(Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
CC
Changed ICC (Typ) value from 12 mA to 15 mA at f = f
Changed I
2.5 µA to 7 µA.
SB1
and I
Typ values from 0.7 µA to 1 µA and Max values from
SB2
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed I
Added I
Changed t
CCDR
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the package diagram 48-ball VFBGA from *B to *D
from 2.5 µA to 7 µA.
CCDR
typical value.
from 3 ns to 5 ns
LZOE
and t
LZCE
from 6 ns to 5 ns
LZBE
from 22 ns to 18 ns
HZCE
from 30 ns to 35 ns.
PWE
from 22 ns to 25 ns.
SD
from 6 ns to 10 ns
LZWE
Updated the ordering information table and replaced the Package Name
column with Package Diagram.
Added footnote #12 related AC timing parameters
SB2
CY62146EV30 MoBL
) from 100 µs to t
R
max
and I
CCDR
RC
®
ns
Document #: 38-05567 Rev. *C Page 12 of 12
Loading...