CY62138F MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Logic Block Diagram
Functional Description
[1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
LOW).
or CE
2
HIGH
1
To write to the device, take Chip Enable (CE1 LOW and CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
specified on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE
through IO7) is then written into the location
0
through A17).
0
LOW and CE
1
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
through IO7) are placed
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW).
LOW and CE2 HIGH and WE
1
2
2
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
CE
1
CE
2
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
11
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-13194 Rev. *A Revised March 26, 2007
DATA IN DRIVERS
ROW DECODER
COLUMN DECODER
A
12
256K x 8
ARRAY
14
13
A
A
A15A
IO
0
IO
1
IO
2
IO
3
IO
SENSE AMPS
POWER
DOWN
16
17
A
4
IO
5
IO
6
IO
7
[+] Feedback
CY62138F MoBL
®
Pin Configuration
Product Portfolio
Product
[2]
VCC Range (V)
Min Typ
32-Pin SOIC/TSOP II Pinout
Top View
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
CE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
A
A
A
A
OE
A
CE
IO
IO
IO
IO
IO
2
13
8
9
11
10
1
7
6
5
4
3
Power Dissipation
Speed
(ns)
[3]
Max Typ
Operating ICC (mA)
f = 1MHz f = f
[3]
Max Typ
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
CY62138FLL 4.5V 5.0V 5.5V 45 1.6 2.5 13 18 1 5
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Document #: 001-13194 Rev. *A Page 2 of 10
CC
= V
CC(typ)
, TA = 25°C.
[+] Feedback
CY62138F MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z state
[4, 5]
................–0.5V to 6.0V (V
CCmax
CCmax
+ 0.5V)
+ 0.5V)
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage IOH = –1.0 mA 2.4 V
Output LOW Voltage IOL = 2.1 mA 0.4 V
Input HIGH Voltage V
Input LOW Voltage V
Input Leakage Current GND < VI < V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V –0.5 0.8 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply
Current
Automatic CE Power Down
Current CMOS inputs
f = f
= 1/t
max
RC
f = 1 MHz 1.6 2.5
CE1 > VCC – 0.2V or CE2 < 0.2V
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, VCC = V
CC(max)
[4, 5]
............ –0.5V to 6.0V (V
Device Range
Ambient
Temperature
CCmax
+ 0.5V)
V
CC
[6]
CY62138FLL Industrial –40°C to +85°C 4.5V to 5.5V
45 ns
Min Typ
[3]
Max
+ 0.5 V
CC
Unit
–1 +1 µA
VCC = V
I
OUT
CMOS levels
CC(max)
= 0 mA
13 18 mA
15µA
Capacitance (For all packages)
[8]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input capacitance TA = 25°C, f = 1 MHz,
Output capacitance 10 pF
Thermal Resistance
= V
V
CC
CC(typ)
[8]
10 pF
Parameter Description Test Conditions SOIC TSOP II Unit
Θ
JA
Θ
JC
Notes
4. V
5. V
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
7. Only chip enables (CE
8. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= VCC+0.75V for pulse durations less than 20ns.
IH(max)
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
Thermal Resistance
(Junction to Case)
and CE2) must be at CMOS level to meet the I
1
(min) and 200 µs wait time after V
CC
/ I
SB2
spec. Other inputs can be left floating.
CCDR
44.53 44.16 °C/W
24.05 11.97 °C/W
stabilization.
CC
Document #: 001-13194 Rev. *A Page 3 of 10
[+] Feedback
AC Test Loads and Waveforms
CY62138F MoBL
®
V
CC
OUTPUT
30 pF
R1
R2
3.0V
GND
ALL INPUT PULSES
10%
90%
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT V
Parameters 5.0V Unit
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
639 Ω
1.77 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[9]
t
R
[7]
[8]
VCC for Data Retention 2.0 V
Data Retention Current VCC= VDR, CE1 > VCC − 0.2V or CE2 < 0.2V,
V
> VCC - 0.2V or VIN < 0.2V
IN
Chip Deselect to Data
0ns
Retention Time
Operation Recovery Time t
RC
90%
10%
Fall Time = 1 V/ns
[3]
15µA
Max Unit
ns
Data Retention Waveform
V
CC
CE
Notes:
9. Full device AC operation requires linear V
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
10. CE
[10]
ramp from V
CC
V
CC(min)
t
CDR
DR
to V
DATA RETENTION MODE
VDR> 2.0V
> 100 µs or stable at V
CC(min)
CC(min)
> 100 µs.
V
CC(min)
t
R
Document #: 001-13194 Rev. *A Page 4 of 10
[+] Feedback
CY62138F MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[14]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid 22 ns
OE LOW to Low-Z
OE HIGH to High-Z
[12]
[12, 13]
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH or CE2 LOW to High-Z
CE1 LOW and CE2 HIGH
CE1 HIGH or CE2 LOW
to power up 0 ns
to power down 45 ns
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH
to Write End 35 ns
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
Data Setup to Write end 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[12, 13]
[12]
[11]
[12]
[12, 13]
45 ns
Unit
Min Max
45 ns
5ns
18 ns
10 ns
18 ns
18 ns
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
pulse levels of 0 to V
12. At any given temperature and voltage condition, t
, t
13. t
HZOE
14. The internal write time of the memory is defined by the overlap of WE
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
HZCE
, and t
, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
CC(typ)
transitions are measured when the outputs enter a high impedance state.
HZWE
Document #: 001-13194 Rev. *A Page 5 of 10
is less than t
HZCE
/2, input
CC(typ)
, t
LZCE
, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
is less than t
HZOE
LZOE
, and t
is less than t
HZWE
for any given device.
LZWE
[+] Feedback
Switching Waveforms
Read Cycle 1 (Address transition controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[15, 16]
CY62138F MoBL
tRC
RC
t
AA
®
Read Cycle No. 2 (OE controlled)
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
t
LZCE
t
PU
CURRENT
Write Cycle No. 1 (WE controlled)
ADDRESS
CE
[10, 16, 17]
t
ACE
t
DOE
t
LZOE
50%
[10, 14, 18, 19]
t
t
SCE
RC
t
WC
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
I
CC
50%
I
SB
t
SA
WE
OE
20
DATA IO
Notes:
15. The device is continuously selected. OE
is HIGH for read cycle.
16. WE
17. Address valid before or similar to CE
18. Data IO is high impedance if OE
goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
19. If CE
1
20. During this period, the IOs are in output state. Do not apply input signals.
NOTE
t
HZOE
, CE1 = VIL, CE2 = VIH.
transition LOW and CE2 transition HIGH.
1
= VIH.
Document #: 001-13194 Rev. *A Page 6 of 10
t
AW
t
PWE
t
SD
t
HA
t
HD
DATA VALID
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 controlled)
ADDRESS
CE
t
SA
WE
[10, 14, 18, 19]
t
AW
t
WC
t
PWE
t
SCE
CY62138F MoBL
t
HA
®
DATA IO
Write Cycle No. 3 (WE controlled, OE LOW)
ADDRESS
CE
t
SA
WE
20
DATA IO
NOTE
t
HZWE
[10, 19]
t
SD
DATA VALID
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HD
t
t
HA
LZWE
t
HD
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power Down Standby (I
L H L Data Out Read Active (I
L L X Data In Write Active (I
L H H High Z Selected, Outputs Disabled Active (I
Ordering Information
Speed
(ns) Ordering Code
45 CY62138FLL-45SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial
CY62138FLL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Document #: 001-13194 Rev. *A Page 7 of 10
Package
Diagram
Package Type
CC
CC
CC
SB
)
)
)
)
Operating
Range
[+] Feedback
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
17 32
116
0.440[11.176]
0.450[11.430]
0.546[13.868]
0.566[14.376]
CY62138F MoBL
®
0.101[2.565]
0.111[2.819]
0.050[1.270]
BSC.
0.793[20.142]
0.817[20.751]
0.014[0.355]
0.020[0.508]
0.004[0.102]
SEATING PLANE
MIN.
0.118[2.997]
MAX.
0.004[0.102]
0.006[0.152]
0.012[0.304]
0.023[0.584]
0.039[0.990]
0.047[1.193]
0.063[1.600]
51-85081-*B
Document #: 001-13194 Rev. *A Page 8 of 10
[+] Feedback
Package Diagrams (continued)
Figure 2. 32-Pin TSOP II, 51-85095
CY62138F MoBL
®
51-85095-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 001-13194 Rev. *A Page 9 of 10
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
Document History Page
Document Title: CY62138F MoBL® 2-Mbit (256K x 8) Static RAM
Document Number: 001-13194
REV. ECN NO. Issue Date
** 797956 See ECN VKN New Data Sheet
*A 940341 See ECN VKN Added footnote #7 related to I
Orig. of
Change Description of Change
SB2
and I
CY62138F MoBL
CCDR
®
Document #: 001-13194 Rev. *A Page 10 of 10
[+] Feedback
Loading...