Cypress Semiconductor CY62128VLL-70ZCT, CY62128VLL-70ZC, CY62128VLL-70SCT, CY62128VLL-70SC, CY62128VL-70ZCT Datasheet
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128K x 8 Static RAM
CY62128V Family
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2000
amily
Features
• Low volt age range:
—2.7V–3.6V (CY62128V)
—2.3V–2.7V (CY62128V25)
—1.6V–2.0V (CY62128V18)
• Low active power and standby power
• Easy memory expansion wit h CE
and OE fe atures
• TTL-compatible inputs and outputs
• Autom atic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62128V f ami ly i s com posed of three high- per formanc e
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enabl e (C E
1
), an active HIGH Chip Enable (CE2), an active
LOW Output Enable (OE
) and three-state drivers. These devices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eig ht I/O pins (I/O
0
through I/O7) is then written into the location specified on the
address pins (A
0
through A16).
Reading from the device is accomplished by taking Chip Enable one (CE
1
) and Output Enable (OE) LOW whil e forcing
Write Enable (WE
) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O7) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write oper ation ( CE
1
LOW , CE2 HIGH, and W E LOW) .
14
15
Logic Block Diagram
Pin
Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O1
I/O
2
I/O
3
512x256x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A13A
12
A
A
10
CE
1
A
A
16
A
9
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
151718
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I / STSOP
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
(not to scale)
Top View
Rever se Pinout
62128V-3
62128V-4
CY62128V Family
2
Maximum Ratings
(Above which the useful life may be impaired. For use r gui delines, not tested.)
Storage Temperature ............... .......... .. ......–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +1 2 5 °C
Supply Voltage to Ground Potential
(Pin 28 to Pi n 14 ) ........ ... .. ............ ............. ..... –0.5V to +4.6V
DC V oltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to VCC + 0.5V
DC Input Voltage
[1]
.................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .. .......... .. .......... .......... .. ... >200 mA
Operating Range
Range Ambient Tem perature V
CC
Commercial 0°C to +70°C 1.6V to 3.6V
Industrial –40°C to +85°C 1.6V to 3.6V
Product Portfolio
VCC Range
Po wer Diss ipation (Commercial)
Operating (ICC) Standby (I
SB2
)
Product Min. Typ.
[2]
Max. Speed Typ.
[2]
Maximum Typ.
[2]
Maximum
CY62128V 2.7V 3.0V 3.6V 55, 70 ns 20 mA 40 mA 0.4 µA 100 µA (XL = 10 µA)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 µA 50 µA (LL = 12 µA)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 µA 30 µA (LL = 10 µA)
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Unit
V
OH
Outp ut HIGH Volta ge VCC = Min., IOH = –1.0 mA 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
V
IH
Input HIGH Voltage 2 V
CC
+0.5V
V
V
IL
Input LOW Voltage –0.5 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1 ±1 +1
µA
I
OZ
Output Leakage Current GND < VO < VCC, Output Disabled –1 ±1 +1
µA
I
CC
VCC Operating Suppl y
Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l,
70 ns
L 20 40 mA
LL, XL 20 40
Ind’l,
55 ns
LL 23 50
Ind’l,
70 ns
L 20 40
LL 20 40
I
SB1
Auto matic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
Com’l,
70 ns
L 15 300
µA
LL, XL 15 300
Coml,
55 ns
LL 17 350
Ind’l L 15 300
LL 15 300
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= VCC Typ., TA = 25°C.
CY62128V Family
3
I
SB2
Auto matic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V
V
IN
> VCC – 0.3V
or V
IN
< 0.3V, f = 0
Com’l L 0.4 100
µA
LL 15
µA
XL 10
µA
Ind’l L 100
µA
LL 30
µA
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Unit
Electrical Characteristics
Over the Operating Range
CY62128V25-100 CY62128V18-200
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Min. Typ.
[2]
Max. Unit
V
OH
Outp ut HIGH Volta ge VCC = Min. , IOH = –0.1 mA 2.4 0.8*
V
CC
V
V
OL
Output LOW Voltage VCC = Min. , IOL = 0.1 mA 0.4 0.2 V
V
IH
Input HIGH Voltage 2 V
CC
+0.5
0.7*
V
CC
V
CC
+0.3
V
V
IL
Input LOW Voltage –0.5 0.8 –0.5 0.3*
V
CC
V
I
IX
Input Load Current GND < VI < V
CC
–1 ±1 +1 –1 ±0.1 +1
µA
I
OZ
Output Leakage Current GND < VO < VCC, Output
Disabled
–1 ±1 +1 –1 ±0.1 +1
µA
I
CC
VCC Operating Suppl y
Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
L 15 20 10 15 mA
LL
I
SB1
Auto matic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
L 15 300 5 100
µA
LL
I
SB2
Auto matic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V
V
IN
> VCC – 0.3V
or V
IN
< 0.3V, f = 0
L 0.4 50 0.4 30
µA
LL 12 10
µA
Indust’l Temp Range LL 24 20
µA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 3.0V
6 pF
C
OUT
Output Capacitance 8 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
CY62128V Family
4
AC Test Loads and Waveforms
1.8V
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
62128V–5
62128V–6
R
TH
R1
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
R
TH
645 3500 3000 Ohms
V
TH
1.75V 0.55V 0.50V Volts
Data Rete n ti o n C h ar acteristics
(Over the Operating Range)
Parameter Description Conditions
[4]
Min. Typ.
[2]
Max. Unit
V
DR
VCC for Da ta Rete ntion 1.6 V
I
CCDR
Data Retention Current Com’l L VCC = 2V
CE
> VCC – 0.3V,
V
IN
> VCC – 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
0.4 10
µA
LL,
XL
10
µA
Ind’l L 20
µA
LL 20
µA
t
CDR
[3]
Chip Deselect to Dat a Retention Time 0 ns
t
R
Operation Recov ery Time t
RC
ns
Data Retention Waveform
Note:
4. No input may exceed V
CC
+0.3V.
C62128V–7
1.8V1.8V
t
CDR
VDR> 1.6 V
DATA RETENTION MODE
t
R
CE
V
CC
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