Datasheet CY62128VLL-70ZCT, CY62128VLL-70ZC, CY62128VLL-70SCT, CY62128VLL-70SC, CY62128VL-70ZCT Datasheet (Cypress Semiconductor)
...
128K x 8 Static RAM
CY62128V Family
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2000
amily
Features
• Low volt age range:
—2.7V–3.6V (CY62128V)
—2.3V–2.7V (CY62128V25)
—1.6V–2.0V (CY62128V18)
• Low active power and standby power
• Easy memory expansion wit h CE
and OE fe atures
• TTL-compatible inputs and outputs
• Autom atic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62128V f ami ly i s com posed of three high- per formanc e
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enabl e (C E
1
), an active HIGH Chip Enable (CE2), an active
LOW Output Enable (OE
) and three-state drivers. These devices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eig ht I/O pins (I/O
0
through I/O7) is then written into the location specified on the
address pins (A
0
through A16).
Reading from the device is accomplished by taking Chip Enable one (CE
1
) and Output Enable (OE) LOW whil e forcing
Write Enable (WE
) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O7) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write oper ation ( CE
1
LOW , CE2 HIGH, and W E LOW) .
14
15
Logic Block Diagram
Pin
Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O1
I/O
2
I/O
3
512x256x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A13A
12
A
A
10
CE
1
A
A
16
A
9
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
151718
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I / STSOP
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
(not to scale)
Top View
Rever se Pinout
62128V-3
62128V-4
CY62128V Family
2
Maximum Ratings
(Above which the useful life may be impaired. For use r gui delines, not tested.)
Storage Temperature ............... .......... .. ......–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +1 2 5 °C
Supply Voltage to Ground Potential
(Pin 28 to Pi n 14 ) ........ ... .. ............ ............. ..... –0.5V to +4.6V
DC V oltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to VCC + 0.5V
DC Input Voltage
[1]
.................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .. .......... .. .......... .......... .. ... >200 mA
Operating Range
Range Ambient Tem perature V
CC
Commercial 0°C to +70°C 1.6V to 3.6V
Industrial –40°C to +85°C 1.6V to 3.6V
Product Portfolio
VCC Range
Po wer Diss ipation (Commercial)
Operating (ICC) Standby (I
SB2
)
Product Min. Typ.
[2]
Max. Speed Typ.
[2]
Maximum Typ.
[2]
Maximum
CY62128V 2.7V 3.0V 3.6V 55, 70 ns 20 mA 40 mA 0.4 µA 100 µA (XL = 10 µA)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 µA 50 µA (LL = 12 µA)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 µA 30 µA (LL = 10 µA)
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Unit
V
OH
Outp ut HIGH Volta ge VCC = Min., IOH = –1.0 mA 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
V
IH
Input HIGH Voltage 2 V
CC
+0.5V
V
V
IL
Input LOW Voltage –0.5 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1 ±1 +1
µA
I
OZ
Output Leakage Current GND < VO < VCC, Output Disabled –1 ±1 +1
µA
I
CC
VCC Operating Suppl y
Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l,
70 ns
L 20 40 mA
LL, XL 20 40
Ind’l,
55 ns
LL 23 50
Ind’l,
70 ns
L 20 40
LL 20 40
I
SB1
Auto matic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
Com’l,
70 ns
L 15 300
µA
LL, XL 15 300
Coml,
55 ns
LL 17 350
Ind’l L 15 300
LL 15 300
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= VCC Typ., TA = 25°C.
CY62128V Family
3
I
SB2
Auto matic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V
V
IN
> VCC – 0.3V
or V
IN
< 0.3V, f = 0
Com’l L 0.4 100
µA
LL 15
µA
XL 10
µA
Ind’l L 100
µA
LL 30
µA
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Unit
Electrical Characteristics
Over the Operating Range
CY62128V25-100 CY62128V18-200
Parameter Description Test Condi tions Min. Typ.
[2]
Max. Min. Typ.
[2]
Max. Unit
V
OH
Outp ut HIGH Volta ge VCC = Min. , IOH = –0.1 mA 2.4 0.8*
V
CC
V
V
OL
Output LOW Voltage VCC = Min. , IOL = 0.1 mA 0.4 0.2 V
V
IH
Input HIGH Voltage 2 V
CC
+0.5
0.7*
V
CC
V
CC
+0.3
V
V
IL
Input LOW Voltage –0.5 0.8 –0.5 0.3*
V
CC
V
I
IX
Input Load Current GND < VI < V
CC
–1 ±1 +1 –1 ±0.1 +1
µA
I
OZ
Output Leakage Current GND < VO < VCC, Output
Disabled
–1 ±1 +1 –1 ±0.1 +1
µA
I
CC
VCC Operating Suppl y
Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
L 15 20 10 15 mA
LL
I
SB1
Auto matic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
L 15 300 5 100
µA
LL
I
SB2
Auto matic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V
V
IN
> VCC – 0.3V
or V
IN
< 0.3V, f = 0
L 0.4 50 0.4 30
µA
LL 12 10
µA
Indust’l Temp Range LL 24 20
µA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 3.0V
6 pF
C
OUT
Output Capacitance 8 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
CY62128V Family
4
AC Test Loads and Waveforms
1.8V
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
62128V–5
62128V–6
R
TH
R1
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
R
TH
645 3500 3000 Ohms
V
TH
1.75V 0.55V 0.50V Volts
Data Rete n ti o n C h ar acteristics
(Over the Operating Range)
Parameter Description Conditions
[4]
Min. Typ.
[2]
Max. Unit
V
DR
VCC for Da ta Rete ntion 1.6 V
I
CCDR
Data Retention Current Com’l L VCC = 2V
CE
> VCC – 0.3V,
V
IN
> VCC – 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
0.4 10
µA
LL,
XL
10
µA
Ind’l L 20
µA
LL 20
µA
t
CDR
[3]
Chip Deselect to Dat a Retention Time 0 ns
t
R
Operation Recov ery Time t
RC
ns
Data Retention Waveform
Note:
4. No input may exceed V
CC
+0.3V.
C62128V–7
1.8V1.8V
t
CDR
VDR> 1.6 V
DATA RETENTION MODE
t
R
CE
V
CC
CY62128V Family
5
Data Retention Current Graph
(for “L” version only)
Switching Characteristics
Over the Operating Range
[5]
62128V-55 62128V-70 62128V25-100 62128V18-200
Parameter Description Mi n . Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 55 70 100 200 ns
t
AA
Address to Data Valid 55 70 100 200 ns
t
OHA
Data Hold from Address Change 5 10 10 10 ns
t
ACE
CE LOW to Data Valid 55 70 100 200 ns
t
DOE
OE LOW to Data Valid 20 35 75 125 ns
t
LZOE
OE LOW to Low Z
[6]
10 10 10 10 ns
t
HZOE
OE HIGH to High Z
[6, 7]
20 25 50 75 ns
t
LZCE
CE LOW to Low Z
[6]
10 10 10 10 ns
t
HZCE
CE HIGH to High Z
[6, 7]
20 25 50 75 ns
t
PU
CE LOW to Po wer-Up 0 0 0 0 ns
t
PD
CE HIGH to Power-Down 55 70 100 200 ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time 55 70 100 200 ns
t
SCE
CE LOW to Write End 45 60 100 190 ns
t
AW
Address Set-Up to Write End 45 60 100 190 ns
t
HA
Address Hold from Write End 0 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 0 ns
t
PWE
WE Pu lse Widt h 45 55 90 125 ns
t
SD
Data Set -U p to Write End 25 30 60 100 ns
t
HD
Data Hold from Write End 0 0 0 0 ns
t
HZWE
WE LOW to High Z
[6, 7]
20 25 50 100 ns
t
LZWE
WE HIGH to Low Z
[6]
5 5 10 15 ns
5. Tes t conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capa citan ce.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with CL = 5 pF as in pa rt (b) of A C Test Loads. Transition is measured ±200 mV from s teady-st ate v oltage .
8. The internal write time of the memory is defined by the overlap of CE1 LOW , CE2 HIGH, and WE LOW . CE1 and WE signals must be LOW and CE2 HIGH to initiate a
write and either signal c an terminate a write by goin g HIGH. The data i nput set- up and hold timing should be r eferenc ed to the rising edge of the signal t hat terminates the write.
9. The minimum write cycle time for write cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.
SUPPLY VOLTAGE (V)
DATA RETENTION
CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
T
=25°C
1.6
2.6
3.6
(
µ
A)
40
30
20
10
0
50
60
70
80
A
CY62128V Family
6
Switching Waveforms
Read Cycle No. 2 (OE Controll ed)
[11, 12]
Write Cycle No. 1 (CE1 or CE2 Controlled)
[13,14]
Notes:
10. Device is continuously selected. OE
, CE = V
IL, CE2=VIH
.
11. WE
is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE2 transition HIGH.
13. Data I/O is high impedance if OE
= VIH.
14. If CE
1
goes HIGH or CE2 goes LOW simul tane ously w ith WE HI GH, the output rem ains in a high- impedance st ate.
Read Cycle No.1
ADDRESS
DATA OUT PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
62128V–8
[10, 11]
62128V-9
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
62128V-10
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
CY62128V Family
7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[13, 14]
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued )
62128V-11
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
SCE
t
WC
t
HZOE
DATAINVALID
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
NOTE
15
Truth Table
CE
1
CE
2
OE WE I/O0–I/O
7
Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
CY62128V Family
8
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
55 CY62128VLL-55ZAI ZA32 32-Lead STSOP Type 1 Industrial
70 CY62128VL-70SC S34 32-Lead 450-M il SO IC Commercial
CY62128VLL-70SC S34
CY62128VL-70ZC Z32 32-Lead TSOP Type 1
CY62128VLL-70ZC Z32
CY62128VXL-70ZC Z32
CY62128VL-70ZAC ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAC ZA32
CY62128VL-70ZRC ZR32 32-Lead Reverse TSOP 1
CY62128VLL-70ZRC ZR32
70 CY62128VL-70SI S34 32- Lead 450-Mil SOIC Industrial
CY62128VLL-70SI S34
CY62128VL-70ZI Z32 32-Lead TSOP Type 1
CY62128VLL-70ZI Z32
CY62128VL-70ZAI ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAI ZA32
CY62128VL-70ZRI ZR32 32-Lead Reverse TSOP 1
CY62128VLL-70ZRI ZR32
100 CY62128V25L-100SC S34 32-Lead 450-Mil SOIC Commercial
CY62128V25LL-100SC S34
CY62128V25L-100ZC Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZC Z32
CY62128V25L-100ZAC ZA32 32-Lead STSOP Type 1
CY62128V25LL-100ZAC ZA32
CY62128V25L-100ZRC ZR32 32-Lead Reverse TSOP 1
CY62128V25LL-100ZRC ZR32
100 CY62128V25L-100SI S34 32-Lead 450-Mil SOIC Industrial
CY62128V25LL-100SI S34
CY62128V25L-100ZI Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZI Z32
CY62128V25L-100ZAI ZA32 32-Lead STSOP Type 1
CY62128V25LL-100ZAI ZA32
CY62128V25L-100ZRI ZR32 32-Lead Reverse TSOP 1
CY62128V25LL-100ZRI ZR32
200 CY62128V18L-200SC S34 32-Lead 450-Mil SOIC Commercial
CY62128V18LL-200SC S34
CY62128V18L-200ZC Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZC Z32
CY62128V18L-200ZAC ZA32 32-Lead STSOP Type 1
CY62128V18LL-200ZAC ZA32
CY62128V18L-200ZRC ZR32 32-Lead Reverse TSOP 1
CY62128V18LL-200ZRC ZR32
CY62128V Family
9
Document #: 38-00547-B
200 CY62128V18L-200SI S34 32-Lead 450-Mil SOIC Industrial
CY62128V18LL-200SI S34
CY62128V18L-200ZI Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZI Z32
CY62128V18L-200ZAI ZA32 32-Lead STSOP Type 1
CY62128V18LL-200ZAI ZA32
CY62128V18L-200ZRI ZR32 32-Lead Reverse TSOP 1
CY62128V18LL-200ZRI ZR32
Ordering Information
(continued)
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
CY62128V Family
10
Package Diagrams
(continued)
51-85056-C
32-Lead Thin Small Outline Package Z32
CY62128V Family
11
Package Diagrams
(continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-B
CY62128V Family
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
51-85089-B
32-Lead Reverse Thin Small Outline Package ZR32
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