MoBL® CY62128E
1-Mbit (128K x 8) Static RAM
Features
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A15A
16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A
10
A
11
CE
1
CE
2
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Voltage range: 4.5V to 5.5V
■ Pin compatible with CY62128B
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin TSOP I packages
, CE2, and OE features
1
Functional Description
The CY62128E
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE
eight input and output pins (IO
impedance state when the device is deselected (CE
CE
LOW), the outputs are disabled (OE HIGH), or a write
2
operation is in progress (CE
To write to the device, take Chip Enable (CE1 LOW and CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins (IO
on the address pins (A
0
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing Write Enable
) HIGH. Under these conditions, the contents of the memory
(WE
location specified by the address pins appear on the IO pins.
[1]
is a high performance CMOS static RAM
®
) in portable
HIGH or CE2 LOW). The
1
through IO7) are placed in a high
0
LOW and CE2 HIGH and WE LOW)
1
HIGH or
1
through IO7) is then written into the location specified
through A16).
0
LOW and CE
1
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05485 Rev. *F Revised August 4, 2008
[+] Feedback
MoBL® CY62128E
Pin Configuration
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top Vi ew
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
26
25
26
27
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC
Top View
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
CE
2
WE
OE
CE
1
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (t
AA
, t
ACE
) and 25 ns (t
DOE
) are guaranteed.
[2]
Product Portfolio
Speed
(ns)
[4]
f = 1MHz f = f
[3]
1.3 2 11 16 1 4
Product Range VCC Range (V)
Min Typ
[3]
Max Typ
CY62128ELL Ind’l/Auto-A 4.5 5.0 5.5 45
CY62128ELL Auto-E 4.5 5.0 5.5 55 1.3 4 11 35 1 30
Document #: 38-05485 Rev. *F Page 2 of 12
Power Dissipation
Operating ICC (mA)
Max Typ
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
[+] Feedback
MoBL® CY62128E
Maximum Ratings
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
8. Only chip enables (CE
1
and CE2) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground
Potential...............................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
[5, 6]
.............. –0.5V to 6.0V (V
[5, 6]
........... –0.5V to 6.0V (V
CC(max)
CC(max)
CC(max)
+ 0.5V)
+ 0.5V)
+ 0.5V)
Electrical Characteristics (Over the Operating Range)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Device Range
Ambient
Temperature
CY62128ELL Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
Auto-E –40°C to +125°C
[7]
V
CC
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[8]
Output HIGH
Vol tage
Output LOW
Vol tage
Input HIGH Voltage V
Input LOW voltage V
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power down
Current—CMOS
Inputs
Capacitance (For all Packages)
IOH = –1 mA 2.4 2.4 V
IOL = 2.1 mA 0.4 0.4 V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
CC
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –4 +4 μA
f = f
= 1/tRCVCC = V
max
f = 1 MHz 1.3 2 1.3 4
I
= 0 mA
OUT
CMOS levels
CE1 > VCC – 0.2V or CE2 < 0.2V,
> VCC – 0.2V or VIN < 0.2V,
V
IN
f = 0, V
[9]
CC
= V
CC(max)
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
CC(max)
V
= V
CC
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[3]
Max Min Typ
+ 0.5 2.2 V
CC
[3]
Max
+ 0.5 V
CC
–1 +1 –4 +4 μA
11 16 11 35 mA
14 130μA
10 pF
CC(typ)
Unit
Document #: 38-05485 Rev. *F Page 3 of 12
[+] Feedback
MoBL® CY62128E
Thermal Resistance
3.0V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC(min)
V
CC(min)
t
CDR
VDR> 2.0V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Notes
10. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
[9]
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveform
Parameters Val ue Unit
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
1.77 V
SOIC
Package
STSOP
Package
48.67 32.56 33.01 °C/W
25.86 3.59 3.42 °C/W
639 Ω
TSOP
Package
Unit
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Ty p
V
DR
I
CCDR
[9]
t
CDR
[10]
t
R
Data Retention Waveform
Document #: 38-05485 Rev. *F Page 4 of 12
VCC for Data Retention 2 V
[8]
Data Retention Current VCC= VDR, CE1 > VCC − 0.2V or CE2 < 0.2V,
> VCC - 0.2V or VIN < 0.2V
V
IN
Ind’l/Auto-A 4 μA
Auto-E 30 μA
Chip Deselect to Data
Retention Time
Operation Recovery
Time
[11]
[3]
Max Unit
0ns
t
RC
ns
[+] Feedback
MoBL® CY62128E
Switching Characteristics (Over the Operating Range)
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I
OL/IOH
as shown in the “” on page 4.
13. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
14. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[12]
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[15]
Read Cycle Time 45 55 ns
Address to Data Valid 45 55 ns
Data Hold from Address Change 10 10 ns
CE
LOW and CE2 HIGH to Data Valid 45
1
OE LOW to Data Valid 22
OE LOW to Low-Z
OE HIGH to High-Z
CE1 LOW and CE2 HIGH to Low-Z
CE1 HIGH or CE2 LOW to High-Z
CE1 LOW and CE2 HIGH to Power Up 0
CE1 HIGH or CE2 LOW to Power Down 45
Write Cycle Time 45 55 ns
CE1 LOW and CE2 HIGH to Write End 35
Address Setup to Write End 35 40 ns
Address Hold from Write End 0
Address Setup to Write Start 0 0 ns
WE Pulse Width 35
Data Setup to Write End 25 25 ns
Data Hold from Write End 0 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[13]
[13, 14]
[13, 14]
[13]
[13]
[13, 14]
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Max Min Max
55
25
5
18
10
18
5
20
10
20
0
55
40
0
40
10
18
10
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05485 Rev. *F Page 5 of 12
[+] Feedback
MoBL® CY62128E
Switching Waveforms
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
21
Notes:
16. The device is continuously selected. OE
, CE1 = VIL, CE2 = VIH.
17. WE
is HIGH for read cycle.
18. Address valid before or similar to CE
1
transition LOW and CE2 transition HIGH.
19. Data IO is high impedance if OE
= VIH.
20. If CE
1
goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state and input signals must not be applied.
Figure 1. Read Cycle 1 (Address Transition Controlled)
[16, 17]
Figure 2. Read Cycle No. 2 (OE Controlled)
Figure 3. Write Cycle No. 1 (WE Controlled)
[11, 17, 18
[11, 15, 19, 20]
]
Document #: 38-05485 Rev. *F Page 6 of 12
[+] Feedback
MoBL® CY62128E
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA IO
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA IO
NOTE
21
Figure 4. Write Cycle No. 2 (CE1
or CE2 Controlled)
[11, 15, 19, 20]
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)
Truth Table
CE
H X X X High-Z Deselect/Power down Standby (ISB)
X L X X High-Z Deselect/Power down Standby (I
L H H L Data Out Read Active (I
L H L X Data In Write Active (ICC)
L H H H High-Z Selected, Outputs Disabled Active (I
Document #: 38-05485 Rev. *F Page 7 of 12
1
CE
2
WE OE Inputs/Outputs Mode Power
[11, 20]
CC
CC
SB
)
)
)
[+] Feedback
MoBL® CY62128E
Ordering Information
Speed
(ns)
45 CY62128ELL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) Industrial
45 CY62128ELL-45SXA 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-A
55 CY62128ELL-55SXE 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code
CY62128ELL-45ZAXI 51-85094 32-pin STSOP (Pb-free)
CY62128ELL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-55ZAXE 51-85094 32-pin STSOP (Pb-free)
Package
Diagram
Package Type
Package Diagrams
Figure 6. 32-pin (450 Mil) Molded SOIC (51-85081)
Operating
Range
Document #: 38-05485 Rev. *F Page 8 of 12
[+] Feedback
MoBL® CY62128E
Figure 7. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm) (51-85094)
51-85094-*D
Document #: 38-05485 Rev. *F Page 9 of 12
[+] Feedback
MoBL® CY62128E
Figure 8. 32-pin Thin Small Outline Package Type I (8 x 20 mm) (51-85056)
Document #: 38-05485 Rev. *F Page 10 of 12
[+] Feedback
MoBL® CY62128E
Document History Page
Document Title: CY62128E MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 38-05485
Revision ECN
Submission
Date
** 203120 See ECN AJU New data sheet
*A 299472 See ECN SYT Converted from Advance Information to Preliminary
*B 461631 See ECN NXR Converted from Preliminary to Final
*C 464721 See ECN NXR Updated the Block Diagram on page # 1
*D 563144 See ECN AJU Added footnote 4 on page 2
*E 1024520 See ECN VKN Added Automotive-A information
*F 2548575 08/05/08 NXR Corrected typo error in Ordering Information table
Orig. of
Change
Description of Change
Changed t
Changed t
Changed t
speed bins, respectively
Changed t
bins, respectively
Changed t
bins, respectively
from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
OHA
from 15 ns to 18 ns for 35 ns speed bin
DOE
, t
HZOE
HZCE
from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed
SCE
from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
HZWE
from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of I
SB1
, I
SB2
and I
from 1.0 μA to 1.5 μA
CCDR
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed I
= f
max
Changed I
Removed I
Changed I
Changed I
Changed I
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the Ordering Information Table
CC (Typ)
CC (max)
SB2 (max)
SB2 (Typ)
CCDR (max)
LZOE
LZCE
HZCE
PWE
SD
LZWE
from 8 mA to 11 mA and I
from 1.5 mA to 2.0 mA for f = 1 MHz
DC Specs from Electrical characteristics table
SB1
from 1.5 μA to 4 μA
from 0.5 μA to 1 μA
from 1.5 μA to 4 μA
from 3 to 5 ns
from 6 to 10 ns
from 22 to 18 ns
from 30 to 35 ns
from 22 to 25 ns
from 6 to 10 ns
Converted Automotive-E specs to final
Added footnote #9 related to I
Updated Ordering Information table
SB2
and I
CCDR
CC (max)
from 12 mA to 16 mA for f
Document #: 38-05485 Rev. *F Page 11 of 12
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MoBL® CY62128E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05485 Rev. *F Revised August 4, 2008 Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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