Cypress Semiconductor CY24713 Specification Sheet

CY24713

Set-top Box Clock Generator with VCXO

Features

Logic Block Diagram

Note

1. Float X

OUT

if XIN is externally driven.

Benefits

■ Integrated phase-locked loop (PLL)

■ Low-jitter, high-accuracy outputs

■ VCXO with analog adjust

■ 3.3V Operation

■ 8-pin SOIC

■ High-performance PLL tailored for Set Top Box applications

■ Meets critical timing requirements in complex system designs

■ Large ±150-ppm range, better linearity

■ Meet industry standard voltage platforms

■ Industry standard packaging saves on board space

Part Number Outputs Input Frequency Range Output Frequencies

CY24713 3 27-MHz pullable crystal input

4.9152 MHz, 13.5 MHz, 27 MHz

per Cypress specification

Pin Configuration

Table 1. Pin Definition

Name Number Description

XIN 1 Reference Crystal Input
VDD 2 3.3V Voltage Supply
VCXO 3 Input Analog Control for VCXO
VSS 4 Ground
CLK_B 5 13.5-MHz Clock Output
CLK_A 6 4.9152-MHz Clock Output
CLK_C 7 27-MHz Clock Output

[1]

XOUT

8 Reference Crystal Output

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07396 Rev. *A Revised May 22, 2008

Figure 1. CY24713, 8-Pin SOIC

[+] Feedback

CY24713

Absolute Maximum Conditions

Note

2. Rated for 10 years

Parameter Description Min Max Unit

V

DD

T

S

T

J

Supply Voltage –0.5 7.0 V
Storage Temperature

[2]

–65 125 °C
Junction Temperature – 125 °C
Digital Inputs V
Digital Outputs referred to V

DD

– 0.3 VDD + 0.3 V

SS

VSS – 0.3 VDD + 0.3 V
Electrostatic Discharge – 2000 V
Analog Input –0.5 7.0 V

Pullable Crystal Specifications

Parameter Description Condition Min Typ. Max Unit

F

C
R
R

NOM

LNOM
1
3/R1

Nominal crystal frequency Parallel resonance, funda-

–27–MHz

mental mode, AT cut
Nominal load capacitance – 14 – pF
Equivalent series resistance (ESR) Fundamental mode – – 25 Ω
Ratio of third overtone mode ESR to fundamen-

tal mode ESR

Ratio used because typica l R1

values are much less than the

3––

maximum spec.

DL Crystal drive level No external series resistor as-

–0.52.0mW

sumed

F

3SEPHI

F

3SEPLO

C

0

C

0/C1

C

1

Third overtone separation from 3*F
Third overtone separation from 3*F

NOM
NOM

High side 300 – – ppm

Low side – – –150 ppm
Crystal shunt capacitance – – 7 pF
Ratio of shunt to motional capacitance 180 – 250
Crystal motional capacitance 14.4 18 21.6 pF

Recommended Operating Conditions

Parameter Description Min Typ. Max Unit

V
T

A

C
t

PU

DD

LOAD

Operating Voltage 3.135 3.3 3.465 V
Ambient Temperature 0 – 70 °C
Max. Load Capacitance – – 15 pF
Power up time for all VDDs to reach minimum specified voltage (power

ramps must be monotonic)

DC Electrical Characteristics

Parameter Description Conditions Min Typ. Max Unit

I

OH

I

OL

C

IN

I

IZ

f

ΔXO

V

VCXO

I

VDD

Document #: 38-07396 Rev. *A Page 2 of 5

Output High Current VOH = VDD – 0.5, V
Output Low Current VOL = 0.5, V
Input Capacitance – – 7 pF
Input Leakage Current – 5 – μA
VCXO pullability range ±150 – – ppm
VCXO input range 0 – V
Supply Current – 25 30 mA

0.05 – 500 ms

= 3.3V 12 24 – mA

DD

= 3.3V 12 24 – mA

DD

DD

V

[+] Feedback