Datasheet CY2309SC-1T, CY2309SC-1H, CY2309SC-1, CY2309ZI-1HT, CY2309ZI-1H Datasheet (Cypress Semiconductor)
...
CY2305
CY2309
Low-cost 3.3V Zero Delay Buffer
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low-skew outputs
—Output-output skew less than 250 ps
—Device-device skew less than 700 ps
—One input drives five outputs (CY2305)
—One input drives nine outputs, group ed as 4 + 4 + 1
(CY2309)
• Less than 200 ps cycle-cycle jitter, compatible with
Pentium
-based systems
• Te st Mode to bypass phase-locked loop (PLL) (CY2309
only [see “Select Input Decoding” on page 2])
• Available in sp ac e-sa vin g 16-pin 150 -mil SOIC or
4.4-mm TSSOP p ack age s (CY2 309 ), a nd 8-pin , 1 50-m il
SOIC package (CY2305)
• 3.3V operation
• Industrial temperature available
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is avail able in a 16-p in SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
PLL
REF
S2
Select Input
Decoding
S1
2309-1
MUX
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Sele ct inputs as shown in the “Select Input
Decoding” table on page 2. If all outp ut clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly app lied to the out puts for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising ed ges on the R EF input. In this state,
the outputs are three-s tated and the PLL is turned of f, resulting
in less than 12.0 µA of current draw for commercial temperature devices and 25.0 µA for indus trial temperature p arts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and di stribute it. In this case, the skew betwe en the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs ha ve less than 20 0 ps of cycl e-cycle jitter . The input
to output propagation delay on both devices is guaranteed to
be less than 350 ps, and the output to output skew is
guaranteed to be less than 250 ps.
The CY2305/CY2309 is avai lable in two/thre e diff erent conf igurations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-dri ve ve rsion of the - 1, and i ts rise a nd
fall times are much faster than the -1s.
Pin Configuration
SOIC/TSSOP
DD
S2
REF
CLK2
CLK1
GND
Top View
1
2
3
4
5
6
7
8
SOIC
Top View
1
2
3
4
16
15
14
13
12
11
10
9
8
7
6
5
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
CLKOUT
CLK4
V
DD
CLK3
2309-2
2309-3
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA1
CLKA2
V
GND
CLKB1
CLKB2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07140 Rev. *C Revised December 14, 2002
Pin Description for CY2309
Pin Signal Description
DD
[1]
Input reference frequency, 5V-tolerant inp ut
[2]
[2]
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
1REF
2 CLKA1
3 CLKA2
4V
5 GND Ground
6 CLKB1
7 CLKB2
8S2
9S1
10 CLKB3
1 1 CLKB4
[2]
[2]
[3]
[3]
[2]
[2]
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
12 GND Ground
13 V
14 CLKA3
15 CLKA4
DD
[2]
[2]
16 CLKOUT
[2]
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, interna l feed bac k on this pin
CY2305
CY2309
Pin Description for CY2305
Pin Signal Description
1REF
2CLK2
3CLK1
[1]
[2]
[2]
Input reference frequency, 5V-tolerant inp ut
Buffered clock output
Buffered clock output
4 GND Ground
DD
[2]
[2]
[2]
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
5CLK3
6V
7CLK4
8 CLKOUT
Select Input Decoding for CY2309
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT
0 0 Three-state Three-state Driven PLL N
0 1 Driven Three-state Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull -ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
[4]
Output Source PLL Shutdown
Document #: 38-07140 Rev. *C Page 2 of 13
CY2305
CY2309
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL , its relativ e loading can adj ust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load, equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustmen ts are required, use the above graph to
calculate lo ading differences between the CLKOUT pin and
other outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”
Document #: 38-07140 Rev. *C Page 3 of 13
Maximum Ratings
CY2305
CY2309
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF.........................................–0.5V to 7V
Storage Temperature .................................–65°C to +150°C
Junction Temperature................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................> 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter Description Min. Max. Unit
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage 3.0 3.6 V
Operating Temperature (Ambient Temperature) 0 70 °C
Load Capacitance, below 100 MHz 30 pF
Load Capacitance, from 100 MHz to 133 MHz 10 pF
Input Capacitance 7 pF
Power-up time for all VDD's to reach minimum specified voltage
t
PU
(power ramps must be monotonic) 0.05 50 ms
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter Description Test Conditions Min. Max. Unit
[6]
DD
[5]
[5]
= 0V 50.0 µA
IN
[6]
[6]
DD
IOL = 8 mA (–1)
I
12 mA (–1H)
OH =
IOH = –8 mA (–1)
I
= –12 mA (–1H)
OL
2.0 V
2.4 V
0.8 V
100.0 µA
0.4 V
32.0 mA
SEL inputs at V
10-pF load
1
Measured at 1.4V, F
DD
10
10
= 66.67 MHz 40.0 50.0 60.0 %
out
100
133.33
[7]
MHz
MHz
Measured between 0.8V and 2.0V 2.50 ns
Measured between 0.8V and 2.0V 2.50 ns
[6]
All outputs equally loaded 250 ps
Measured at VDD/2 0 ±350 ps
[6]
Measured at VDD/2. Measured in PLL
[6]
Bypass Mode, CY2309 device only.
[6]
Measured at VDD/2 on the CLKOUT pins
158.7ns
0700ps
of devices
Measured at 66 .67 MHz, load ed outp uts 200 ps
Stable power supply, valid clock
1.0 ms
presented on REF pin
/2.
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
(PD mode) Power Down Supply Current REF = 0 MHz 12.0 µA
I
DD
I
DD
Input LOW Voltage
Input HIGH Voltage
Input LOW Current V
Input HIGH Current VIN = V
Output LOW Voltage
Output HIGH Voltage
Supply Current Unloaded outputs at 66.67 MHz,
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices
Parameter Name Test Conditions Min. Typ. Max. Unit
t1 Output Frequency 30-pF load
[6]
Duty Cycle
t3 Rise Time
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Notes:
5. REF input has a threshold voltage of V
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
= t2 ÷ t
[6]
[6]
[6]
Document #: 38-07140 Rev. *C Page 4 of 13
CY2305
CY2309
Switching Characteristics for CY2305SC- 1H and CY2309SC-1H Commercial Temper ature Devices
Parameter Name Description Min. Typ. Max. Unit
t1 Output Frequency 30-pF load
10-pF load
[6]
Duty Cycle
Duty Cycle
t3 Rise Time
t
4
t
5
t
6A
t
6B
t
7
t
8
t
J
t
LOCK
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
PLL Lock Time
[6]
[6]
= t2 ÷ t
[6]
= t2 ÷ t
1
1
[6]
[6]
[6]
Measured at 1.4V, F
Measured at 1.4V, F
Measured between 0.8V and 2.0V 1.50 ns
Measured between 0.8V and 2.0V 1.50 ns
[6]
All outputs equally loaded 250 ps
Measured at VDD/2 0 ±350 ps
[6]
Measured at VDD/2. Measured in PLL
[6]
Bypass Mode, CY2309 device only.
[6]
Measured at VDD/2 on the CLKOUT pins
of devices
Measured between 0.8V an d 2.0V using
Test Circuit #2
Measured at 66 .67 MHz, load ed outp uts 200 ps
Stable power supply, valid clock
presented on REF pin
= 66.67 MHz 40.0 50.0 60.0 %
out
<50.0 MHz 45.0 50.0 55.0 %
out
10
10
100
133.33
MHz
MHz
158.7ns
0700ps
1V/ns
1.0 ms
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter Description Min. Max. Unit
V
DD
T
A
C
L
C
L
C
IN
Supply V ol t age 3.0 3.6 V
Operating Temperature (Ambient Temperature) –40 85 °C
Load Capacitance, below 100 MHz 30 pF
Load Capacitance, from 100 MHz to 133 MHz 10 pF
Input Capacitance 7 pF
[7]
Electrical Characteristics for CY230 5SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter Description Test Conditions Min. Max. Unit
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Input LOW Voltage
Input HIGH Vo lt a ge
Input LOW Current V
Input HIGH Current VIN = V
Output LOW Voltage
Output HIGH Voltage
IDD (PD mode) Power Down Supply Current REF = 0 MHz 25.0 µA
I
DD
Supply Current Unloaded outputs at 66.67 MHz , SEL inputs at
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices
Parameter Name Test Conditions Min. Typ. Max. Unit
t1 Output Frequency 30-pF load
[6]
[6]
[6]
= t2 ÷ t
Duty Cycle
t3 Rise Time
t
4
Fall Time
[5]
[5]
= 0V 50.0 µA
IN
[6]
[6]
DD
IOL = 8 mA (-1)
=12 mA (-1H)
I
OH
IOH = –8 mA (-1)
= –12 mA (-1H)
I
OL
2.0 V
2.4 V
0.8 V
100.0 µA
0.4 V
35.0 mA
V
DD
[7]
10
10-pF load
1
Measured at 1.4V, F
= 66.67 MHz 40.0 50.0 60.0 %
out
10
100
133.33
MHz
MHz
Measured between 0.8V and 2.0V 2.50 ns
Measured between 0.8V and 2.0V 2.50 ns
Document #: 38-07140 Rev. *C Page 5 of 13
CY2305
CY2309
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices
[7]
Parameter Name Test Conditions Min. Typ. Max. Unit
[6]
[6]
[6]
All outputs equally loaded 250 ps
Measured at VDD/2 0 ±350 ps
Measured at VDD/2. Measured in
1 5 8.7 ns
PLL Bypass Mode, CY2309 de vice
t
5
t
6A
t
6B
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
only.
[6]
[6]
Measured at VDD/2 on the CLKOUT
pins of devices
Measured at 66.67 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
0 700 ps
200 ps
1.0 ms
t
7
t
J
t
LOCK
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
[6]
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industri al Temperature Devices
Parameter Name Description Min. Typ. Max. Unit
t
1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
8
t
J
t
LOCK
Output Frequency 30-pF load
10-pF load
[6]
[6]
[6]
= t2 ÷ t
[6]
= t2 ÷ t
1
1
Measured at 1.4V , F
Measured at 1.4V, F
Measured between 0.8V and 2.0V 1.50 ns
Measured between 0.8V and 2.0V 1.50 ns
[6]
All outputs equally loa ded 250 ps
Measured at VDD/2 0 ±350 ps
[6]
Measured at VDD/2. Measured in
[6]
PLL Bypass Mode, CY2309 dev ice
Duty Cycle
Duty Cycle
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
only.
Device to Device Skew
[6]
Measured at VDD/2 on the CLKOUT
pins of devices
Output Slew Rate
[6]
Measured between 0.8V and 2.0V
using Test Circuit #2
Cycle to Cycle Jitter
[6]
Measured at 66.67 MHz, loaded
outputs
PLL Lock Time
[6]
Stable power supply, valid clock
presented on REF pin
10
10
= 66.67 MHz 40.0 50.0 60.0 %
out
< 50.0 MHz 45.0 50.0 55.0 %
out
100
133.33
1 5 8.7 ns
0 700 ps
1 V/ns
200 ps
1.0 ms
MHz
MHz
[7]
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V 1.4V 1.4V
Document #: 38-07140 Rev. *C Page 6 of 13
Switching Waveforms (continued)
All Outputs Rise/Fall Time
CY2305
CY2309
OUTPUT
2.0V 2.0V
0.8V
t
3
Output-Output Skew
OUTPUT
OUTPUT
1.4V
t
5
1.4V
Input-Output Propagation Delay
/2
V
INPUT
OUTPUT
DD
t
VDD/2
6
0.8V
3.3V
0V
t
4
Device-Device Skew
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t
7
V
/2
DD
Document #: 38-07140 Rev. *C Page 7 of 13
CY2305
Duty Cy cle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs Frequency
(for 30 pF L oads over Temperat u re - 3. 3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Nu mber of Load ed Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
CY2309
Typical Duty Cycle
[8]
and IDD Trends
[9]
for CY2305-1 and CY2309-1
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
58
56
54
52
50
48
Duty Cycle (% )
46
44
42
40
3 3.1 3.2 3.3 3.4 3.5 3.6
(for 15 pF L o ads over Temperatur e - 3.3V)
60
58
56
54
52
50
48
Duty Cycle (%)
46
44
42
40
20 40 60 80 100 120 140
Duty Cycle Vs VDD
33 MHz
66 MHz
100 MHz
133 MHz
VDD (V)
Duty Cycle Vs F r equency
-40C
0C
25C
70C
85C
Frequency (MHz)
Notes:
8. Duty Cycle is taken from typical chip measured at 1.4V.
9. I
data is calculated from I
DD
Voltage (V); f = frequency (Hz)).
Document #: 38-07140 Rev. *C Page 8 of 13
DD
= I
CORE
+ nCVf, where I
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
120
100
80
60
IDD (mA)
40
20
0
0123456789
# of Loade d Outpu ts
is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply
CORE
33 MHz
66 MHz
100 MHz
CY2305
Duty Cy cle Vs VD D
(for 30 pF Loads ove r Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
160
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
CY2309
Typical Duty Cycle
[8]
and IDD Trends
[9]
for CY2305-1H and CY2309-1H
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
58
56
54
52
50
48
Duty Cycle (%)
46
44
42
40
3 3.1 3.2 3.3 3.4 3.5 3.6
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
54
52
50
48
Duty Cycle (%)
46
44
42
40
20 40 60 80 100 120 140
Duty Cycle Vs VDD
33 M Hz
66 M Hz
100 MHz
133 MHz
VDD (V)
Duty Cycle Vs Frequency
-40C
0C
25C
70C
85C
Frequency (MHz)
Document #: 38-07140 Rev. *C Page 9 of 13
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
160
140
120
100
80
IDD (mA)
60
40
20
0
0123456789
# of Loaded Outputs
33 MHz
66 MHz
100 MHz
Test Circuits
CY2305
CY2309
Test Circuit # 2
V
DD
OUTPUTS
V
DD
GND
(output slew rate) on -1H devices
8
GND
1 kΩ
1 kΩ
0.1 µF
0.1 µF
Test Circuit # 1
V
DD
OUTPUTS
V
DD
GND
GND
CLK
out
C
0.1 µF
LOAD
0.1 µF
For parameter t
Ordering Information
Ordering Code Package Type Operating Range
CY2305SC-1 8-pin 150-mil SOIC Commercial
CY2305SC-1T 8-pin 150-mil SOIC–Tape and Reel Commercial
CY2305SI-1 8-pin 150-mil SOIC Industrial
CY2305SI-1T 8-pin 150-mil SOIC–Tape and Reel Industrial
CY2305SC-1H 8-pin 150-mil SOIC Commercial
CY2305SC-1HT 8-pin 150-mil SOIC–Tape and Reel Commercial
CY2305SI-1H 8-pin 150-mil SOIC Industrial
CY2305SI-1HT 8-pin 150-mil SOIC–Tape and Reel Industrial
CY2305ZC-1 8-pin 150-mil TSSOP Commercial
CY2305ZC-1T 8-pin 150-mil TSSOP–Tape and Reel Commercial
CY2309SC-1 16-pin 150-mil SOIC Commercial
CY2309SC-1T 16-pin 150-mil SOIC–Tape and Reel Commercial
CY2309SI-1 16-pin 150-mil SOIC Industrial
CY2309SI-1T 16-pi n 150-mil SOIC–Tape and Reel Industrial
CY2309SC-1H 16-pin 150-mil SOIC Commercial
CY2309SC-1HT 16-pin 150-mil SOIC–Tape and Reel Commercial
CY2309SI-1H 16-pin 150-mil SOIC Industrial
CY2309SI-1HT 16-pin 150-mil SOIC–Tape and Reel Industrial
CY2309ZC-1H 16-pin 4.4-mm TSSOP Commercial
CY2309ZC-1HT 16-pin 4.4-mm TSSOP–Tape and Reel Commercial
CY2309ZI-1H 16-pin 4.4-mm TSSO P Industrial
CY2309ZI-1HT 16-pin 4.4-mm TSSO P–Tape and Reel Industrial
10 pF
Document #: 38-07140 Rev. *C Page 10 of 13
Package Diagrams
CY2305
CY2309
8-lead (150-Mil) SOIC S8
16-lead (150-Mil) Molded SOIC S16
51-85066-A
51-85068-A
Document #: 38-07140 Rev. *C P age 11 of 13
Package Diagrams (continued)
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
CY2305
CY2309
51-85091-**
Pentium is a regi ste red trad em ark of Inte l C o rpora tion. All product an d c om p an y nam es m enti on ed in this document may b e th e
trademark s of their respective hol ders.
Document #: 38-07140 Rev. *C Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2305
CY2309
Document History Page
Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer
Document Number: 38-07140
REV. ECN NO. Issue Date
** 110249 10/19/01 SZV Change from Spec number: 38-00530 to 38-07140
*A 111117 03/01/02 CKN Added t6B row to the Switching Characteristics Table; also added the letter
*B 117625 10/21/02 HWT Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the
*C 121828 12/14/02 RBI Power up requirements added to Operating Conditions Information
Orig. of
Change Description of Change
“A” to the t6A row
Corrected the table title from CY2305SC-IH and CY2309SC-IH to
CY2305SI-IH and CY2309SI-IH
ordering information table.
Added the Tape and Reel option to all the existing packages:
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,
CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,
CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT
Document #: 38-07140 Rev. *C Page 13 of 13
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