Cypress Semiconductor CY2291 Specification Sheet

Download

CY2291

Three-PLL General Purpose EPROM

Programmable Clock Generator

Features

Logic Block Diagram

32XIN 32XOUT XTALIN

XTALOUT

S2/SUSPEND

SHUTDOWN

32K

CONFIG EPROM

OSC.

XBUF

CPLL

SPLL

UPLL

OSC.

CPUCLK

CLKA

CLKB

CLKC

CLKD

MUX

CLKF

/1,2,4

/1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104

/2,3,4

/1,2,4,8

(8 BIT)

(10 BIT)

Benefits

■ Three integrated phase-locked loops

■ EPROM programmability

■ Factory-programmable (CY2291) or field-programmable

(CY2291F) device options

■ Low-skew, low-jitter, high-accuracy outputs

■ Power-management options (Shutdown, OE, Suspend)

■ Frequency select option

■ Smooth slewing on CPUCLK

■ Configurable 3.3V or 5V operation

■ 20-pin SOIC Package

■ Generates up to three custom frequencies from external

sources

■ Easy customization and fast turnaround

■ Programming support available for all opportunities

■ Meets critical industry standard timing requirements

■ Supports low-power applications

■ Eight user-selectable frequencies on CPU PLL

■ Allows downstream PLLs to stay locked on CPUCLK output

■ Enables application compatibility

■ Industry-standard packaging saves on board space

Part Number Outputs Input Frequency Range Output Frequency Range Specifics

CY2291 8 10 MHz–25 MHz (external crystal)

1 MHz–30 MHz (reference clock)

CY2291I 8 10 MHz–25 MHz (external crystal)

1 MHz–30 MHz (reference clock)

CY2291F 8 10 MHz–25 MHz (external crystal)

1 MHz–30 MHz (reference clock)

CY2291FI 8 10 MHz–25 MHz (external crystal)

1 MHz–30 MHz (reference clock)

76.923 kHz–100 MHz (5V)

76.923 kHz–80 MHz (3.3V)

76.923 kHz–90 MHz (5V)

76.923 kHz–66.6 MHz (3.3V)

76.923 kHz–90 MHz (5V)

76.923 kHz–66.6 MHz (3.3V)

76.923 kHz–80 MHz (5V)

76.923 kHz–60.0 MHz (3.3V)

Factory Programmable Commercial Temperature

Factory Programmable Industrial Temperature

Field Programmable Commercial Temperature

Field Programmable Industrial Temperature

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07189 Rev. *C Revised September 16, 2008

[+] Feedback

CY2291

Pinouts

CLKB

1 2 3 4 5 6 7 8

9 10

32XOUT

32K

CLKC

GND

XTALIN

XTALOUT

XBUF

32XIN V

BATT

SHUTDOWN/OE

S2/SUSPEND V

S1 S0

CLKF

CLKD

CPUCLK

CLKA

Notes

1. For best accuracy, use a parallel-resonant crystal, C

LOAD

≈ 17 pF or 18 pF.

2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).

3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.

4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pi ns are pulled LOW.

Pin Definitions

Name Pin Number Description

32XOUT 1 32.768-kHz crystal feedback.

32K 2 32.768-kHz output (always active if VBATT is present).

CLKC 3 Configurable clock output C.

VDD 4, 16 Voltage supply. GND 5 Ground.

XTALIN

XTALOUT

S2/SUSPEND 17

SHUTDOWN/OE 18

[1]

[1, 2]

XBUF 8 Buffered reference clock output. CLKD 9 Configurable clock output D.

CPUCLK 10 CPU frequency clock output.

CLKB 11 Configurable clock output B. CLKA 12 Configurable clock output A.

CLKF 13 Configurable clock output F.

S0 14 CPU clock select input, bit 0. S1 15 CPU clock select input, bit 1.

VBATT 19 Battery supply for 32.768-kHz circuit.

32XIN 20 32.768-kHz crystal input.

Figure 1. CY2291- 20-pin SOIC

6 7

Reference crystal input or external reference clock input. Reference crystal feedback.

CPU clock select input, bit 2. Optionally enables suspend feature when LOW.

[4]

Places outputs in three-state places outputs in three-state

condition and shuts down chip when LOW. Optionally , only

[4]

condition and does not shut down chip when LOW.

[3]

Document #: 38-07189 Rev. *C Page 2 of 12

[+] Feedback

CY2291

Operation

The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to me et the diverse clock generation needs of modern motherboards and other synchronous systems.

All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable cloc k outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals.

The CY2291 can be configured for either 5V or 3.3V operatio n. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscillator must connect a 10-MW resistor in parallel with the 32-kHz crystal.

Output Configuration

The CY2291 has five independent frequency sources on-chip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources.

All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note “Understanding the CY2291, CY2292, and CY2295” for information on configuring the part.

Power Saving Features

The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the V (for Commercial Temp. or 100 μA for Industrial Temp.) plus 15 μA max. for the 32-kHz subsystem and is typically 10 μA. After leaving shutdown mode, the PLLs have to re-lock. All outputs except 32K have a weak pull down so that the outputs do not float when three-stated.

The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any

[4]

pins are less than 50 μA

combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.

The CPUCLK can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial T emp. and for field-programmed parts). This feature is extremely useful in “Green” PC and laptop applications, where reducing the frequency of operation can result in conside rable power savings. This feature meets all 486 and Pentium® processor slewing requirements.

[3]

CyClocks Software

CyClocks™ is an easy-to-use application that allows you to configure any one of the EPROM programmable clocks offered by Cypress. Y ou may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. CyClocks is a sub-application within the CyberClocks™ software. You can download a copy of CyberClocks for free on Cypr ess’s web site at www.cypress.com.

Cypress FTG Programmer

The Cypress Frequency Timing Generator (FTG) Programmers is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670.

Custom Configuration Request Procedure

The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested are matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is:

Use CyClocks™ software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress w eb site (http://www.cypress.com) or from your local sales representative.

Once the custom request has been processed you receive a part number with a 3-digit extension (for example, CY2292SC-128) specific to the frequencies and pinout of your device. This is the part number used for samples requests and production orders.

Document #: 38-07189 Rev. *C Page 3 of 12

[+] Feedback

CY2291

Maximum Ratings

Notes

5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.

6. External input reference clock must have a duty cycle between 40% and 60%, measured at V

/2.

7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.

8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up t o 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150Ω pull up resistor to V

be connected to the Xout pin.

9. Xtal inputs have CMOS thresholds.

10.Load = Max., V

= 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula

(multiply by 0.65 for 3V operation): I

=10+0.06•(F

CPLL+FUPLL

+2•F

SPLL

)+0.27•(F

CLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF

(Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested .)

Supply Voltage...............................................–0.5V to + 7.0V

DC Input Voltage..................................... ......–0.5V to + 7.0V

Storage Temperature ................................. –65°C to +150°C

Operating Conditions

[5]

Max. Soldering Temperature (10 sec) ......................... 260°C

Junction Temperature.................................................. 150°C

Package Power Dissipation......................................750 mW

Static Discharge Voltage.............................................

≥ 2000V

(per MIL-STD-883, Method 3015)

Parameter Description Part Numbers Min. Max. Unit

V V V T

DD DD BATT A

Supply Voltage, 5.0V operation All 4.5 5.5 V Supply Voltage, 3.3V operation All 3.0 3.6 V Battery Backup Voltage All 2.0 5.5 V Commercial Operating Temperature, Ambient CY2291/CY2291F 0 +70 °C

Industrial Operating Temperature, Ambient CY2291I/CY2291FI −40 +85 °C C C f

REF

LOAD LOAD

Max. Load Capacitance 5.0V Operation All 25 pF

Max. Load Capacitance 3.3V Operation All 15 pF

External Reference Crystal All 10.0 25.0 MHz

External Reference Clock

[6, 7, 8]

Power up time for all VDDs to reach minimum specified voltage (power

All 1 30 MHz

0.05 50 ms

ramps must be monotonic)

Electrical Characteristics, Commercial 5.0V

Parameter Description Conditions Min. Typ. Max. Unit

V V V

V V I

DDS

BATT

OH OL OH–32

OL–32

IH IL

HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V

LOW-Level Output Voltage IOL = 4.0 mA 0.4 V

32.768-kHz HIGH-Level

Output Voltage

32.768-kHz LOW-Level

IOH = 0.5 mA V

BATT

0.5

IOL = 0.5 mA 0.4 V

Output Voltage

[9]

HIGH-Level Input Voltage

LOW-Level Input Voltage

Input HIGH Current VIN = V

Except crystal pins 2.0 V

[9]

Except crystal pins 0.8 V

– 0.5V <1 10 μA

Input LOW Current VIN = +0.5V <1 10 μA

Output Leakage Current Three-state outputs 250 μA

VDD Supply Current

Commercial

VDD Power Supply Current

in Shutdown Mode

BATT

[10]

Power Supply Current V

VDD = VDD Max., 5V operation 75 100 mA

Shutdown active, excluding V

BATT

= 3.0V 5 15 μA

CY2291/CY2291F 10 50 μA

Document #: 38-07189 Rev. *C Page 4 of 12

[+] Feedback

CY2291

Electrical Characteristics, Commercial 3.3V

Parameter Description Conditions Min. Typ. Max. Unit

OH–32

OL–32

HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V

LOW-Level Output Voltage IOL = 4.0 mA 0.4 V

32.768-kHz HIGH-Level

Output Voltage

32.768-kHz LOW-Level

IOH = 0.5 mA V

BATT

0.5

IOL = 0.5 mA 0.4 V

Output Voltage

[9]

HIGH-Level Input Voltage

LOW-Level Input Voltage

Except crystal pins 2.0 V

[9]

Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V <1 10 μA Input LOW Current VIN = +0.5V <1 10 μA

Output Leakage Current Three-state outputs 250 μA VDD Supply Current

[10]

= VDD Max., 3.3V operation 50 65 mA

Commercial

DDS

BATT

VDD Power Supply Current in Shutdown Mode

Power Supply Current V

BATT

[10]

Shutdown active,

excluding V

BATT

= 3.0V 5 15 μA

CY2291/CY2291F 10 50 μA

Electrical Characteristics, Industrial 5.0V

Parameter Description Conditions Min. Typ. Max. Unit

OH–32

OL–32

DDS

BATT

HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V

32.768-kHz HIGH-Level Output Voltage

32.768-kHz LOW-Level

IOH = 0.5 mA V

BATT

0.5

IOL = 0.5 mA 0.4 V Output Voltage

[9]

HIGH-Level Input Voltage LOW-Level Input Voltage

Except crystal pins 2.0 V

[9]

Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V < 1 10 μA Input LOW Current VIN = +0.5V < 1 10 μA

Output Leakage Current Three-state outputs 250 μA VDD Supply Current

[10]

= VDD Max., 5V operation 75 110 mA

Industrial VDD Power Supply Current

in Shutdown Mode V

Power Supply Current V

BATT

[10]

Shutdown active,

excluding V

BATT

= 3.0V 5 15 μA

CY2291I/CY2291FI 10 100 μA

Electrical Characteristics, Industrial 3.3V

Parameter Description Conditions Min. Typ. Max. Unit

OH–32

OL–32

Document #: 38-07189 Rev. *C Page 5 of 12

HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V

32.768-kHz HIGH-Level Output Voltage

32.768-kHz LOW-Level Output Voltage

IOH = 0.5 mA V

BATT

0.5

IOL = 0.5 mA 0.4 V

[+] Feedback

CY2291

Electrical Characteristics, Industrial 3.3V (continued)

Notes

11.XBUF duty cycle depends on XTALIN duty cycle.

12.Measured at 1.4V.

13.Measured between 0.4V and 2.4V.

14.Jitter varies with configuration. All standard configurations sample test ed at the factor y conform to this l imit. For more informat ion on jitter , please refer to the a pplication note: “Jitter in PLL-Based Systems.”

15.CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.

Parameter Description Conditions Min. Typ. Max. Unit

[10]

[9]

Except crystal pins 2.0 V

[9]

Except crystal pins 0.8 V

= VDD max., 3.3V operation 50 70 mA

HIGH-Level Input Voltage LOW-Level Input Voltage

Input HIGH Current VIN = VDD–0.5V < 1 10 μA Input LOW Current VIN = +0.5V < 1 10 μA Output Leakage Current Three-state outputs 250 μA VDD Supply Current

Industrial

DDS

BATT

VDD Power Supply Current in Shutdown Mode

Power Supply Current V

BATT

[10]

Shutdown active, excluding V

BATT

= 3.0V 5 15 μA

CY2291I/CY2291FI 10 100 μA

Switching Characteristics, Commercial 5.0V

Parameter Name Description Min. Typ. Max. Unit

Output Period Clock output range, 5V

operation

Output Duty

[11]

Cycle

Duty cycle for outputs, defined as t2 ÷ t f

> 66 MHZ

OUT

Duty cycle for outputs, defined as t f

< 66 MHZ

OUT

Rise Time Fall Time Output Disable

Time Output Enable

Time Skew

Output clock rise time Output clock fall time

[13]

Time for output to enter three-state mode after SHUTDOWN

/OE goes LOW

Time for output to leave three-state mode after SHUTDOWN

Skew delay between any identical or related outputs

12, 15]

/OE goes HIGH

[13]

CY2291 10

(100 MHz)

CY2291F 11.1

(90 MHz)

÷ t

[12]

40% 50% 60%

45% 50% 55%

[3,

13000

(76.923 kHz)

13000

(76.923 kHz)

35ns

2.5 4 ns 10 15 ns

10 15 ns

< 0.25 0.5 ns

10A

Document #: 38-07189 Rev. *C Page 6 of 12

CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/m

Clock Jitter

[14]

Lock Time for

Peak-to-peak period jitter (t9A Max. – t9A min.),% of clock period (f

OUT

< 4 MHz)

Peak-to-peak period jitter (t9B Max. – t9B min.)

(4 MHz <

< 16 MHz)

OUT

Peak-to-peak period jitter (16 MHz < f

OUT <

50 MHz)

Peak-to-peak period jitter

> 50 MHz)

OUT

Lock Time from Power Up < 25 50 ms

< 0.5 1 %

< 0.7 1 ns

< 400 500 ps

< 250 350 ps

CPLL

[+] Feedback

CY2291

Switching Characteristics, Commercial 5.0V (continued)

Parameter Name Description Min. Typ. Max. Unit

10B

Lock Time for UPLL and SPLL

Lock Time from Power Up < 0.25 1 ms

Slew Limits CPU PLL Slew Limits CY2291 8 100 MHz

CY2291F 8 90 MHz

Switching Characteristics, Commercial 3.3V

Parameter Name Description Min. Typ. Max. Unit

Output Period Clock output range, 3.3V

operation

Output Duty

[11]

Cycle

Duty cycle for outputs, defined as t2 ÷ t f

> 66 MHZ

OUT

Duty cycle for outputs, defined as t f

< 66 MHZ

Rise Time Fall Time Output Disable

Time Output Enable

Time Skew

OUT

Output clock rise time Output clock fall time

Time for output to enter three-state mode after SHUTDOWN

/OE goes LOW

Time for output to leave three-state mode after SHUTDOWN

Skew delay between any identical or related outputs

12, 15]

/OE goes HIGH

[13]

CY2291 12.5

(80 MHz)

CY2291F 15

(66.6 MHz)

÷ t

[12]

40% 50% 60%

45% 50% 55%

[3,

13000

(76.923 kHz)

13000

(76.923 kHz)

35ns

2.5 4 ns 10 15 ns

10 15 ns

< 0.25 0.5 ns

10A

10B

CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/m

Clock Jitter

[14]

Lock Time for

Peak-to-peak period jitter (t9A Max. – t9A min.),% of clock period (f

OUT

< 4 MHz)

Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz

< 16 MHz)

OUT

Peak-to-peak period jitter (16 MHz < f

OUT <

50 MHz)

Peak-to-peak period jitter

> 50 MHz)

OUT

Lock Time from Power Up <25 50 ms

<0.5 1 %

<0.7 1 ns

<400 500 ps

<250 350 ps

CPLL Lock Time for

Lock Time from Power Up <0.25 1 ms

UPLL and SPLL Slew Limits CPU PLL Slew Limits CY22 91 8 80 MHz

CY2291F 8 66.6 MHz

Document #: 38-07189 Rev. *C Page 7 of 12

[+] Feedback

CY2291

Switching Characteristics, Industrial 5.0V

Parameter Name Description Min. Typ. Max. Unit

Output Period Clock output range,

5V operation

Output Duty

[11]

Cycle

Duty cycle for outputs, defined as t2 ÷ t f

> 66 MHZ

OUT

Duty cycle for outputs, defined as t f

< 66 MHZ

OUT

Rise Time Output clock rise time Fall Time Output clock fall time Output Disable

Time Output Enable

Time Skew

Time for output to enter three-state mode after SHUTDOWN

/OE goes LOW

Time for output to leave three-state mode after SHUTDOWN

Skew delay between any identical or related outputs

12, 15]

/OE goes HIGH

[13]

CY2291I 11.1

(90 MHz)

CY2291FI 12.5

(80 MHz)

÷ t

[12]

40% 50% 60%

45% 50% 55%

[3,

13000

(76.923 kHz)

13000

(76.923 kHz)

35ns

2.5 4 ns 10 15 ns

10 15 ns

< 0.25 0.5 ns

10A

10B

CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/m

Clock Jitter

Lock Time for

Peak-to-peak period jitter (t9A Max. – t9A min.),% of clock period (f

[14]

Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz <

< 16 MHz)

[14]

OUT

Peak-to-peak period jitter (16 MHz < f

[14]

Peak-to-peak period jitter (f

> 50 MHz)

OUT

OUT <

< 4 MHz)

50 MHz)

Lock Time from Power Up <25 50 ms

<0.5 1 %

<0.7 1 ns

<400 500 ps

<250 350 ps

[14]

CPLL Lock Time for

Lock Time from Power Up <0.25 1 ms

UPLL and SPLL Slew Limits CPU PLL Slew Limits CY22 91I 8 90 MHz

CY2291FI 8 80 MHz

Switching Characteristics, Industrial 3.3V

Parameter Name Description Min. Typ. Max. Unit

Output Period Clock output range, 3.3V

operation

Output Duty

[11]

Cycle

Duty cycle for outputs, defined as t2 ÷ t f

> 66 MHZ

OUT

Duty cycle for outputs, defined as t f

< 66 MHZ

Rise Time Fall Time Output Disable

Time

OUT

Output clock rise time Output clock fall time

Time for output to enter three-state mode after SHUTDOWN

/OE goes LOW

[13]

CY2291I 15

(66.6 MHz)

CY2291FI 16.66

(60 MHz)

÷ t

[12]

40% 50% 60%

45% 50% 55%

13000

(76.923 kHz)

13000

(76.923 kHz)

35ns

2.5 4 ns

10 15 ns

Document #: 38-07189 Rev. *C Page 8 of 12

[+] Feedback

CY2291

Switching Characteristics, Industrial 3.3V (continued)

OUTPUT

Figure 2. All Outputs, Duty Cycle and Rise/Fall Time

Figure 3. Output Three-State Timing

[4]

ALL

THREE-STATE

OUTPUTS

CLK

OUTPUT

CLK

Figure 4. CLK Outputs Jitter and Skew

Parameter Name Description Min. Typ. Max. Unit

Output Enable Time

Skew

Time for output to leave three-state mode after SHUTDOWN

Skew delay between any identical or related outputs

12, 15]

/OE goes HIGH

[3,

10 15 ns

< 0.25 0.5 ns

t t

8 9A

9D 10A

10B

CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/ms Clock Jitter

Clock Jitter

[14]

Lock Time for CPLL

Lock Time for UPLL and SPLL

Slew Limits CPU PLL Slew Limits CY2291I 8 66.6 MHz

Switching Waveforms

Peak-to-peak period jitter (t9A Max. – t9A min.),% of clock period (f

OUT

< 4 MHz)

Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz <

< 16 MHz)

OUT

Peak-to-peak period jitter (16 MHz < f

Peak-to-peak period jitter (f

OUT <

50 MHz)

> 50 MHz) < 250 350 ps

OUT

< 0.5 1 %

< 0.7 1 ns

< 400 500 ps

Lock Time from Power Up < 25 50 ms

Lock Time from Power Up < 0.25 1 ms

CY2291FI 8 60 MHz

Document #: 38-07189 Rev. *C Page 9 of 12

[+] Feedback

CY2291

Switching Waveforms

SELECT

CPU

OLD SELECT NEW SELECT STABLE

old

new

t8&t

Figure 5. CPU Frequency Change

0.1 μF

CLK out

LOAD

GND

OUTPUTS

Note

16.Not recommended for new designs.

Test Circuit

Ordering Information

Ordering Code Package Type Operating Range Operating Voltage

CY2291FI

[16]

Pb-Free

CY2291SXC–XXX 20-Pin SOIC Commercial 5.0V CY2291SXC–XXXT 20-Pin SOIC – Tape and Reel Commercial 5.0V CY2291SXL–XXX 20-Pin SOIC Commercial 3.3V CY2291SXL–XXXT 20-Pin SOIC – Tape and Reel Commercial 3.3V CY2291FX 20-Pin SOIC Commercial 3.3V or 5.0V CY2291FXT 20-Pin SOIC – Tape and Reel Commercial 3.3V or 5.0V

20-Pin SOIC Industrial 3 .3V or 5.0V

Package Characteristics

Package θJA (C/W) θJC (C/W) Transistor Count

20-pin SOIC 125 25 9271

Document #: 38-07189 Rev. *C Page 10 of 12

[+] Feedback

CY2291

Package Diagram

51-85024 *C

Figure 6. 20-Pin (300 MIL) SOIC Package Outline

Document #: 38-07189 Rev. *C Page 11 of 12

[+] Feedback

CY2291

Document History Page

Document Title: CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Document Number: 38-07189

REV. ECN

Orig. of

Change

Submission

Date

Description of Change

** 110321 SZV 10/28/01 Change from Spec number: 38-00410 to 38-07189 *A 121836 RBI 12/14/02 Power up requirements added to Operating Conditions Information *B 276756 RGL 10/18/04 Added Lead Free Devices *C 2565316 AESA/KVM 09/16/08 Updated template. Added Note “Not recommended for new designs.”

Removed part number CY2291F, CY2291FT, CY2291SC-XXX, CY2291SC-XXXT, CY2291SI-XXX, CY2291SI-XXXT, CY2291SL-XXX, CY2291SL-XXXT, CY2291FIT, CY2291SXI-XXX, CY2291SXI-XXXT, CY2291FXI and CY2291FXIT. Changed CyClocks reference to include CyberClocks. Changed Lead-Free to Pb-Free. Updated Package diagram 51-85024 *B to 51-85024 *C.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2001- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be us ed fo r medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an exp re ss wri tte n ag reement with Cypress. Furthermore, Cypress does not authori ze i t s pr o ducts for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunctio n with a Cypress integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does n ot assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-07189 Rev. *C Revised September 16, 2008 Page 12 of 12

Pentium is a registered trademark of Intel Corporation. CyClocks is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.

[+] Feedback

Cypress Semiconductor CY2291 Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual