Cypress Semiconductor CY14B102N, CY14E108N, CY14E108L User Manual

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ADVANCE

CY14E108L, CY14E108N

8 Mbit (1024K x 8/512K x 16) nvSRAM

Features

A0 - A

Address

CAP

DQ0 - DQ7

HSB

CY14E108L

BHE BLE

Logic Block Diagram

[1]

CY14E108N

Note

1. Address A

- A19 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A18 and Data DQ0 - DQ15 for x16 configuration.

Functional Description

■ 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 1024K x 8 (CY14E108L) or 512K x 16

(CY14E108N)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

software, device pin, or AutoStore

■ RECALL to SRAM initiated by software or power up

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 5V +10% operation

■ Commercial and industrial temperatures

■ 48-pin FBGA, 44 and 54-pin TSOP II packages

■ Pb-free and RoHS compliance

nonvolatile elements initiated by

on power down

The Cypress CY14E108L/CY14E108N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 1024K words of 8 bits each or 512K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-45524 Rev. *A Revised June 24, 2008

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CY14E108L, CY14E108N

Pinouts

CAP

DQ0

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

HSB

DQ1

48-FBGA

(not to scale)

Top View

(x8)

[2]

CAP

DQ10

DQ8

DQ9

DQ13

DQ12

DQ14

DQ15

DQ0

BHE

BLE

DQ2

DQ1

DQ3

DQ4

DQ5

DQ6

DQ7

HSB

DQ11

48-FBGA

(not to scale)

Top View

(x16)

[2]

Note

2. Address expansion for 16 Mbit. NC pin not connected to die.

NC NC

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

1 2

3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22

44 - TSOP II

Top View

(not to scale)

DQ7

HSB

CAP

(x8)

[2]

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

CAP

2 3

4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

23 24 25

26 27

54 - TSOP II

Top View

(

not to scale)

NC NC

54 53 52 51

HSB

BHE BLE

DQ15 DQ14 DQ13 DQ12

DQ11 DQ10 DQ9 DQ8

(x16)

[2]

Figure 1. Pin Diagram - 48 FBGA

Figure 2. Pin Diagram - 44/54 TSOP II

Document Number: 001-45524 Rev. *A Page 2 of 20

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CY14E108L, CY14E108N

Pin Definitions

Pin Name IO Type Description

– A

DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on

DQ0 – DQ15

WE Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address

BHE

BLE V

HSB

CAP

NC No Connect No Connect. Do not connect this pin to the die.

Input Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration.

Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration.

operation. Bidirectional Data IO Lines for x16 Configuratio n. Used as input or output lines depending on

operation.

location latched by the falling edge of CE

. Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. IO pins are tri-stated on deasserting OE

high. Input Byte High Enable, Active LOW. Controls DQ15 - DQ8. Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.

Ground Gr ound for the Device. Must be connected to the ground of the system.

Power Supply Power Supply Inputs to the Device.

Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM

to nonvolatile elements.

Document Number: 001-45524 Rev. *A Page 3 of 20

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CY14E108L, CY14E108N

Device Operation

0.1uF

Vcc

10kOhm

CAP

Vcc

CAP

The CY14E108L/CY14E108N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14E108L/CY14E108N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.

SRAM Read

The CY14E108L/CY14E108N performs a READ cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A 1,048,576 data bytes or 524,288 words of 16 bits each is

0-19

or A

determines which of the

0-18

accessed. When the read is initiated by an address transition, the outputs are valid after a delay of t CE

or OE, the outputs are valid at t

later. The data outputs repeatedly respond to address changes

. If the read is initiated by

or at t

ACE

DOE

within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed when CE and WE are LOW and

is HIGH. The address inputs must be stable before entering

HSB the WRITE cycle and must remain stable until either CE goes high at the end of the cycle. The data on the common IO pins DQ before the end of a WE controlled WRITE or before the end of a CE

controlled WRITE. It is recommended that OE be kept HIGH

are written into the memory if the data is valid t

0–15

during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns of f the output buffers t

after WE goes LOW.

HZWE

AutoStore Operation

The CY14B108L/CY14B108N stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108L/CY14B108N.

During a normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation. If the voltage on the V automatically disconnects the V operation is initiated with power provided by the V

Figure 3 shows th e proper connection of the storage capacitor

Electrical Characteristics on page 7 for the size of V

) for automatic store operation. Refer to the section DC

CAP

Software Store activated by an address

pin. This stored

CAP

pin drops below V

pin from VCC. A STORE

CAP

SWITCH

, whichever is

or WE

, the part

capacitor.

CAP

To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress.

Figure 3. AutoStore Mode

Hardware STORE Operation

The CY14B108L/CY14B108N provides the HSB pin to control and acknowledge the STORE operations. Use the HSB request a hardware STORE cycle. When the HSB

pin to

pin is driven LOW, the CY14B108L/CY14B108N conditionally initiates a STORE operation after t begins if a WRITE to the SRAM took place since the last STORE

. An actual STORE cycle only

DELAY

or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition w hile the STORE (initiated by any means) is in progress.

SRAM READ and WRITE operations that are in progress when HSB

is driven LOW by any means are given time to complete

before the STORE operation is initiated. After HSB

goes LOW, the CY14B108L/CY14B108N continues SRAM operations for t

. During t

DELAY

place. If a WRITE is in progress when HSB allowed a time, t cycles requested after HSB

, multiple SRAM READ operations may take

DELAY

to complete. However, any SRAM WRITE

DELAY

goes LOW is inhibited until HSB

is pulled low it is

returns HIGH. During any STORE operation, regardless of how it was initiated,

the CY14B108L/CY14B108N continues to drive the HSB

pin LOW, releasing it only when the STORE is complete.Upon completion of the STORE operation, the CY14B108L/CY14B108N remains disabled until the HSB returns HIGH. Leave the HSB

unconnected if it is not used.

Hardware RECALL (Power Up)

During power up or after any low power condition (V

CC<VSWITCH

again exceeds the sense voltage of V

cycle is automatically initiated and takes t

), an internal RECALL request is latched. When

, a RECALL

SWITCH

HRECALL

to complete.

Document Number: 001-45524 Rev. *A Page 4 of 20

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CY14E108L, CY14E108N

Software ST OR E

Notes

3. The six consecutive address locations must be in the order listed. WE

must be HIGH during all six cycles to enable a nonvolatile cycle.

4. While there are 20/19 address lines on the CY14B108L/CY14B108N, only the lower 16 lines are used to control software modes.

5. IO state depends on the state of OE

, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.

Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B108L/CY14B108N software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed .

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ sequence must be performed.

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x8FC0 Initiate STORE Cycle

The software sequence may be clocked with CE READs or OE

controlled READs. After the sixth address in the

sequence is entered, the STORE cycle commences and the chip

controlled

is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the t the SRAM is activated again for the READ and WRITE operation.

cycle time is fulfilled,

STORE

Software RECALL

Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE be performed.

1. Read Address 0x4E38 Valid READ

2. Read Address 0xB1C7 Valid READ

3. Read Address 0x83E0 Valid READ

4. Read Address 0x7C1F Valid READ

5. Read Address 0x703F Valid READ

6. Read Address 0x4C63 Initiate RECALL Cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells. After the t ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.

controlled READ operations must

cycle time, the SRAM is again

RECALL

Table 1. Mode Selection

CE WE OE

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38

L H L 0x4E38

A15 - A0 Mode IO Power

Active

[3,4,5]

0xB1C7

0x83E0

0x7C1F

0x703F 0x8B45

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

AutoStore

Output Data Output Data Output Data Output Data Output Data Output Data

Disable

[3,4,5]

Active

0xB1C7

0x83E0

0x7C1F

0x703F 0x4B46

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

AutoStore Enable

Output Data Output Data Output Data Output Data Output Data Output Data

Document Number: 001-45524 Rev. *A Page 5 of 20

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CY14E108L, CY14E108N

Table 1. Mode Selection (continued)

CE WE OE

L H L 0x4E38

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x8B45 AutoStore Disable

The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x4B46 AutoStore Enable

A15 - A0 Mode IO Power

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

If the AutoStore function is disabled or re-enabled a manual STORE operation (hardware or software) must be issued to save the AutoStore state thr ough subsequent power down cycles. The part comes from the factory with AutoStore enabled.

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile Store

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile

Recall

Output Data Output Data Output Data Output Data Output Data

Output High Z

Output Data Output Data Output Data Output Data Output Data

Output High Z

Active I

Active

CC2

[3,4,5]

Data Protection

The CY14E108L/CY14E108N protects data from corruption during low voltage conditions by inhibiting all externa lly initiated STORE and write operations. The low voltage condition is detected when V is in a write mode (both CE and WE LOW) at power up, after a RECALL or STORE, the write is inhibited until a negative transition on CE inadvertent writes during power up or brown out conditions.

< V

or WE is detected. This protects against

. If the CY14E108L/CY14E108N

SWITCH

Noise Considerations

Refer CY Application Note AN1064.

[3,4,5]

Document Number: 001-45524 Rev. *A Page 6 of 20

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CY14E108L, CY14E108N

Maximum Ratings

Notes

6. Outputs shorted for no more than one second. No more than one output shorted at a time.

7. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature) and V

= 5V. Not 100% tested.

8. The HSB

pin has I

OUT

=-10uA for VOH of 2.4V. This parameter is characterized but not tested.

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +150°C

Supply Voltage on V Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V

Input Voltage.............................................–0.5V to Vcc+0.5V

Transient Vo ltage (<20 ns) on

Any Pin to Ground Potential..................–2.0V to V

Relative to GND..........–0.5V to 7.0V

+ 0.5V

+ 2.0V

Package Power Dissipation Capability (T

= 25°C) ...................................................1.0W

Surface Mount Pb Soldering

Temperature (3 Seconds).......................................... +260°C

[6]

Output Short Circuit Current

....................................15 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch Up Current................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 4.5V to 5.5V Industrial –40°C to +85°C 4.5V to 5.5V

DC Electrical Characteristics

[8]

Over the Operating Range (VCC = 2.7V to 3.6V)

Parameter Description Test Conditions Min Max Unit

CC1

Average VCC Current tRC = 20 ns

= 25 ns

= 45 ns

Dependent on output loading and cycle rate.Values obtained without output loads. I

= 0 mA

OUT

CC2

CC3

CC4

[7]

Average VCC Current During STORE

Average VCC Current at

= 200 ns, 5V, 25°C

typical Average V

During AutoSt ore Cycle

CAP

Current

All Inputs Don’t Care, VCC = Max Average current for duration t

> (VCC – 0.2). All other I/P cycling. Dependent on output loading and cycle rate. Values obtained without output loads.

All Inputs Don’t Care, VCC = Max Average current for duration t

VCC Standby Current CE > (VCC – 0.2). All others V

Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz.

V V V V V

IH IL OH OL CAP

Input Leakage Current (except HSB

)

Input Leakage Current (For HSB

)

Off-State Output Leakage Current

Input HIGH Voltage 2.0 VCC + 0.5 V Input LOW Voltage Vss – 0.5 0.8 V Output HIGH Voltage I Output LOW Voltage I Storage Capacitor B etween V

= Max, VSS < V

VCC = Max, VSS < V

= –2 mA 2.4 V

OUT

= 4 mA 0.4 V

OUT

Commercial 70

70 55

Industrial 75

75 57

12 mA

STORE

38 mA

12 mA

STORE

< 0.2V or > (VCC – 0.2V).

< V

< VCC, CE or OE > V

pin and VSS, 5V Rated 122 164 μF

CAP

–2 +2 μA

–200 +2 μA

–2 +2 μA

6mA

mA mA mA

Document Number: 001-45524 Rev. *A Page 7 of 20

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CY14E108L, CY14E108N

Capacitance

5.0V

OUTPUT

5 pF

512Ω

5.0V

OUTPUT

30 pF

512Ω

for tri-state specs

963Ω

Note

9. These parameters are guaranteed but not tested.

In the following table, the capacitance parameters are listed

Parameter Description Test Conditions Max Unit

OUT

Input Capacitance TA = 25°C, f = 1 MHz, Output Capacitance 14 pF

[9]

= 0 to 3.0V

14 pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed

Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.

Figure 4. AC Test Loads

[9]

28.82 31.11 30.73 °C/W

7.84 5.56 6.08 °C/W

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <5 ns

Input and Output Timing Reference Levels....................1.5V

Document Number: 001-45524 Rev. *A Page 8 of 20

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AC Switching Characteristics

Notes

10.WE

must be HIGH during SRAM read cycles.

11.Device is continuously selected with CE

and OE both LOW.

12.Measured ±200 mV from steady state output voltage.

13.If WE

is LOW when CE goes LOW, the output goes into high impedance state.

In the following table, the AC switching characteristics are listed.

Parameters

Cypress

Parameters

SRAM Read Cycle

ACE

DOE

OHA

LZCE

HZCE

LZOE

HZOE

DBE

LZBE

HZBE

[10] [11]

[12]

[12] [10] [10]

t t t t t t t t t t t

- Byte Enable to Data Valid 10 12 20 ns

- Byte Enable to Output Active 0 0 0 ns

- Byte Disable to Output Inactive 8 10 15 ns

SRAM Write Cycle

PWE

SCE

HZWE

LZWE

[12,13]

[12]

t t t t t t t t t t

- Byte Enable to End of Write 15 20 30 ns

Alt

Parameters

ACS RC AA OE OH LZ HZ OLZ OHZ PA PS

WC WP CW DW DH AW AS WR WZ OW

Chip Enable Access Time 20 25 45 ns Read Cycle Time 20 25 45 ns Address Access Time 20 25 45 ns Output Enable to Data Valid 10 12 20 ns Output Hold After Address Change 3 3 3 ns Chip Enable to Output Active 3 3 3 ns Chip Disable to Output Inactive 8 10 15 ns Output Enable to Output Active 0 0 0 ns Output Disable to Output Inactive 8 10 15 ns Chip Enable to Power Active 0 0 0 ns Chip Disable to Power Standby 20 25 45 ns

Write Cycle Time 20 25 45 ns Write Pulse Width 15 20 30 ns Chip Enable To End of Write 15 20 30 ns Data Setup to End of Write 8 10 15 ns Data Hold After End of Write 0 0 0 ns Address Setup to End of Write 15 20 30 ns Address Setup to Start of Write 0 0 0 ns Address Hold After End of Write 0 0 0 ns Write Enable to Output Disable 8 10 15 ns Output Active after End of Write 3 3 3 ns

Description

20 ns 25 ns 45 ns

Min Max Min Max Min Max

Unit

Document Number: 001-45524 Rev. *A Page 9 of 20

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CY14E108L, CY14E108N

AutoStore and Power Up RECALL

OHA

ADDRESS

DQ (DATA OUT)

DATA VALID

Notes

14.t

HRECALL

starts from the time VCC rises above V

SWITCH.

15.If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.

16.The software sequence is clocked with CE

controlled or OE controlled reads.

17.The six consecutive addresses must be read in the order listed in the mode selection table. WE

must be HIGH during all six consecutive cycles.

18.This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.

19.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command

20.On a hardware STORE initiation, SRAM operation continues to be enabled for time t

DELAY

to allow read and write cycles to complete.

21.HSB

must remain HIGH during READ and WRITE cycles.

Parameters Description

[15]

[14]

Power Up RECALL Duration 20 ms STORE Cycle Duration 15 ms Low Voltage Trigger Level 4.4 V VCC Rise Time 150 μs

HRECALL

STORE

SWITCH

VCCRISE

CY14E108L/CY14E108N

Min Max

Software Controlled STORE and RECALL Cycle

In the following table, the software controlled STORE/RECALL cycle parameters are listed.

Parameters Description

GHAX

RECALL

[18, 19]

STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Clock Pulse Width 15 20 30 ns Address Hold Time 1 1 1 ns RECALL Duration 200 200 200 μs Soft Sequence Processing Time 70 70 70 μs

20ns 25ns 45ns

Min Max Min Max Min Max

Hardware STORE Cycle

Parameters Description

[20]

DELAY

HLHX

Time allowed to complete SRAM cycle 1 70 μs Hardware STORE pulse width 15 ns

[16, 17]

CY14E108L/CY14E108N

Min Max

Unit

Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled

Document Number: 001-45524 Rev. *A Page 10 of 20

[10, 11, 21]

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CY14E108L, CY14E108N

Switching Waveforms (continued)

ADDRESS

ACE

LZCE

HZCE

DOE

LZOE

DATA VALID

ACTIVE

STANDBY

DQ (DATA OUT)

ICC

LZBE

DBE

HZBE

HZOE

HZCE

BHE , BLE

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

BHE , BLE

Notes

22.CE

or WE must be >VIH during address transitions.

23.BHE

and BLE are applicable for x16 configuration only.

Figure 6. SRAM Read Cycle #2: CE

and OE Controlled

[10, 21, 23]

Figure 7. SRAM Write Cycle #1: WE Controlled

Document Number: 001-45524 Rev. *A Page 11 of 20

[13, 21, 22, 23]

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CY14E108L, CY14E108N

Switching Waveforms (continued)

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

BHE , BLE

SWITCH

STORE

HRECALL

AutoStore

POWER-UP RECALL

Read & Write Inhibited

STORE occurs only if a SRAM write has happened

No STORE occurs without atleast one SRAM write

VCCRISE

Figure 8. SRAM Write Cycle #2: CE

Controlled

[13, 21, 22, 23]

Figure 9. AutoStore or Power Up RECALL

[24]

Note

24.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V

Document Number: 001-45524 Rev. *A Page 12 of 20

SWITCH

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CY14E108L, CY14E108N

Switching Waveforms (continued)

ADDRESS # 1 ADDRESS # 6

ADDRESS

GHAX

STORE

/ t

RECALL

DATA VALID

HIGH IMPEDANCE

DQ (DATA)

Figure 10. CE

Controlled Software STORE/RECALL Cycle

[17]

Figure 11. OE Controlled Software ST OR E/RECALL Cycle

[17]

Document Number: 001-45524 Rev. *A Page 13 of 20

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Switching Waveforms (continued)

Figure 12. Hardware STORE Cycle

[20]

Figure 13. Soft Sequence Processing

[18, 19]

Document Number: 001-45524 Rev. *A Page 14 of 20

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Ordering Information

Speed

(ns)

20 CY14E108L-ZS20XCT 51-85087 44-pin TSOP II Commercial

CY14E108L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14E108L-ZS20XI 51-85087 44-pin TSOP II CY14E108L-BA20XCT 51-85128 48-ball FBGA Commercial CY14E108L-BA20XIT 51-85128 48-ball FBGA Industrial CY14E108L-BA20XI 51-85128 48-ball FBGA CY14E108L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14E108L-ZSP20XIT 51-85160 54-pin TSOP II Industrial CY14E108L-ZSP20XI 51-85160 54-pin TSOP II CY14E108N-BA20XCT 51-85128 48-ball FBGA Commercial CY14E108N-BA20XIT 51 - 85128 48-ball FBGA Industrial CY14E108N-BA20XI 51-85128 48-ball FBGA CY14E108N-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14E108N-ZSP20XIT 51-85160 54-pin TSOP II Industrial CY14E108N-ZSP20XI 51-85160 54-pin TSOP II

25 CY14E108L-ZS25XCT 51-85087 44-pin TSOP II Commercial

CY14E108L-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14E108L-ZS25XI 51-85087 44-pin TSOP II CY14E108L-BA25XIT 51-85128 48-ball FBGA Industrial CY14E108L-BA25XI 51-85128 48-ball FBGA CY14E108N-BA25XCT 51-85128 48-ball FBGA Commercial CY14E108L-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14E108L-ZSP25XIT 51-85160 54-pin TSOP II Industrial CY14E108L-ZSP25XI 51-85160 54-pin TSOP II CY14E108N-BA25XCT 51-85128 48-ball FBGA Commercial CY14E108N-BA25XIT 51 - 85128 48-ball FBGA Industrial CY14E108N-BA25XI 51-85128 48-ball FBGA CY14E108N-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14E108N-ZSP25XIT 51-85160 54-pin TSOP II Industrial CY14E108N-ZSP25XI 51-85160 54-pin TSOP II

Ordering Code

Package Diagram

Package Type

Operating

Range

Document Number: 001-45524 Rev. *A Page 15 of 20

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CY14E108L, CY14E108N

Ordering Information (continued)

Option: T - Tape & Reel Blank - Std.

Speed:

20 - 20ns

25 - 25 ns

Data Bus: L - x8 N - x16

Density:

108 - 8 Mb

Voltage: E - 5.0V

Cypress

CY 14 E 108 L - ZS P 20 X C T

NVSRAM

14 - Auto Store + Software Store + Hardware Store

Temperature: C - Commercial (0 to 70°C)

I - Industrial (–40 to 85°C)

Pb-Free

Package: BA - 48 FBGA ZS - TSOP II

P - 54 Pin Blank - 44 Pin

45 - 45 ns

Speed

(ns)

45 CY14E108L-ZS45XCT 51-85087 44-pin TSOP II Commercial

CY14E108L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14E108L-ZS45XI 51-85087 44-pin TSOP II CY14E108L-BA45XCT 51-85128 48-ball FBGA Commercial CY14E108L-BA45XIT 51-85128 48-ball FBGA Industrial CY14E108L-BA45XI 51-85128 48-ball FBGA CY14E108L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14E108L-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14E108L-ZSP45XI 51-85160 54-pin TSOP II CY14E108N-BA45XCT 51-85128 48-ball FBGA Commercial CY14E108N-BA45XIT 51 - 85128 48-ball FBGA Industrial CY14E108N-BA45XI 51-85128 48-ball FBGA CY14E108N-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14E108N-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14E108N-ZSP45XI 51-85160 54-pin TSOP II

All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.

Ordering Code

Package Diagram

Package Type

Operating

Range

Part Numbering Nomenclature

Document Number: 001-45524 Rev. *A Page 16 of 20

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CY14E108L, CY14E108N

Package Diagrams

MAX MIN.

DIMENSION IN MM (INCH)

11.938 (0.470)

PLANE

SEATING

PIN 1 I.D.

18.517 (0.729)

0.800 BSC

0°-5°

0.400(0.016)

0.300 (0.012)

EJECTOR PIN

OKE

11.735 (0.462)

10.058 (0.396)

10.262 (0.404)

1.194 (0.047)

0.991 (0.039)

0.150 (0.0059)

0.050 (0.0020)

(0.0315)

18.313 (0.721)

10.058 (0.396)

10.262 (0.404)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

BASE PLANE

0.10 (.004)

TOP VIEW BOTTOM VIEW

51-85087-*A

Figure 14. 44-Pin TSOP II (51-85087)

Document Number: 001-45524 Rev. *A Page 17 of 20

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CY14E108L, CY14E108N

Package Diagrams (continued)

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.20 MAX

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

A1 CORNER

TOP VIEW

BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

10.00±0.10

6.00±0.10

1.875

2.625

0.36

51-85128-*D

Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)

Document Number: 001-45524 Rev. *A Page 18 of 20

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CY14E108L, CY14E108N

Package Diagrams (continued)

51-85160-**

Figure 16. 54-Pin TSOP II (51-85160)

Document Number: 001-45524 Rev. *A Page 19 of 20

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ADVANCE

CY14E108L, CY14E108N

Document History Page

Document Title: CY14E108L/CY14E108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001- 45524

REV. ECN NO.

Submission

Date

Orig. of Change

Description of Change

** 2428826 See ECN GVCH New Data Sheet ** 2520023 06/23/08 GVCH/PYRS Updated I

industrial and Commecial temperature Grade

for tRC=20ns, 25ns and 45ns access speed for both

CC1

Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II packages Changed tCW value from 16ns to 15ns

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be use d for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not auth orize its produc ts for use as crit ical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a C ypress integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Code except as specifi ed above is prohib ited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the app licati on or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot auth orize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-45524 Rev. *A Revised June 24, 2008 Page 20 of 20

AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Semiconductor CY14B102N, CY14E108N, CY14E108L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual