PRELIMINARY
CYBLE-416045-02
EZ-BLE™ Creator™ Module
General Description
The Cypress CYBLE-416045-02 is a fully certified and qualified
module supporting Bluetooth
Low Energy (BLE) wireless
communication. The CYBLE-416045-02 is a turnkey solution
and includes onboard crystal oscillators, trace antenna, passive
components, and the Cypress PSoC® 63 BLE silicon device.
Refer to the PSoC® 63 BLE datasheet for additional details on
the capabilities of the PSoC 63 BLE device used on this module.
The EZ-BLE Creator module is a scalable and reconfigurable
platform architecture. It combines programmable and
reconfigurable analog and digital blocks with flexible automatic
routing. The CYBLE-416045-02 also includes digital
programmable logic, high-performance analog-to-digital
conversion (ADC), low-power comparators, and standard
communication and timing peripherals.
The CYBLE-416045-02 includes a royalty-free BLE stack
compatible with Bluetooth 5.0 and provides up to 36 GPIOs in a
14 × 18.5 × 2.00 mm package.
The CYBLE-416045-02 is a complete solution and an ideal fit for
applications seeking a high performance BLE wireless solution.
Module Description
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Module size: 14.0 mm × 18.5 mm × 2.00 mm (with shield)
1 MB Application Flash with 32-KB EEPROM area and 32-KB
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Secure Flash
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288-KB SRAM with Selectable Retention Granularity
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Up to 36 GPIOs with programmable drive modes, strengths,
and slew rates
Bluetooth 5.0 qualified single-mode module
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QDID: TBD
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Declaration ID:TBD
Certified to FCC, CE, MIC, and ISED regulations
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Industrial temperature range: –40 °C to +85 °C
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150-MHz Arm Cortex-M4F CPU with single-cycle multiply
(Floating Point and Memory Protection Unit)
100-MHz Cortex M0+ CPU with single-cycle multiply and MPU.
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One-Time-Programmable (OTP) E-Fuse memory for validation
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and security
Power Consumption
TX output power: –20 dbm to +4 dbm
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Received signal strength indicator (RSSI) with 4-dB resolution
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TX current consumption of 5.7 mA (radio only, 0 dbm)
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RX current consumption of 6.7 mA (radio only)
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Low power 1.7-V to 3.6-V Operation
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Active, Low-power Active, Sleep, Low-power Sleep, Deep
Sleep, and Hibernate modes for fine-grained power
management
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Deep Sleep mode current with 64K SRAM retention is 7 µA
with 3.3-V external supply and internal buck
On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter,
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<1 µA quiescent current
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Backup domain with 64 bytes of memory and Real-Time-ClockProgrammable Analog
Serial Communication
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Nine independent run-time reconfigurable serial communication blocks (SCBs), each is software configurable as I2C,
SPI, or UART
Timing and Pulse-Width Modulation
Thirty-two Timer/Counter Pulse-Width Modulator (TCPWM)
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blocks
Center-aligned, Edge, and Pseudo-random modes
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Comparator-based triggering of Kill signals
Capacitive Sensing
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Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
Cypress-supplied software component makes
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capacitive-sensing design easy
Automatic hardware-tuning algorithm (SmartSense™)
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Serial Communication
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Two independent runtime reconfigurable serial communication
blocks (SCBs) with I2C, SPI, or UART functionality
Timing and Pulse-Width Modulation
Four 16-bit timer, counter, pulse-width modulator (TCPWM)
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blocks
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Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
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other high-reliability digital logic applications
Up to 36 Programmable GPIOs
Any GPIO pin can be CapSense, analog, or digital
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Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-24085 Rev. ** Revised May 30, 2018
PRELIMINARY
CYBLE-416045-02
Audio Subsystem
I2S Interface; up to 192 kilosamples (ksps) Word Clock
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Two PDM channels for stereo digital microphones
Programmable Analog
12-bit 1 Msps SAR ADC with differential and single-ended
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modes and Sequencer with signal averaging
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One 12-bit voltage mode DAC with < 5 µs settling time
Two opamps with low-power operation modes
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Two low-power comparators that operate in Deep Sleep and
Hibernate modes.
Built-in temp sensor connected to ADC
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Programmable Digital
12 programmable logic blocks, each with 8 Macrocells and an
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8-bit data path (called universal digital blocks or UDBs)
Usable as drag-and-drop Boolean primitives (gates, registers),
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or as Verilog programmable blocks
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Cypress-provided peripheral component library using UDBs to
implement functions such as Communication peripherals (for
example, LIN, UART, SPI, I2C, S/PDIF and other protocols),
Waveform Generators, Pseudo-Random Sequence (PRS)
generation, and many other functions.
Smart I/O (Programmable I/O) blocks enable Boolean
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operations on signals coming from, and going to, GPIO pins
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Two ports with Smart_IO blocks, capability are provided; these
are available during Deep Sleep
Energy Profiler
Block that provides history of time spent in different power
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modes
Allows software energy profiling to observe and optimize
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energy consumption
Security Built into Platform Architecture
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Multi-faceted secure architecture based on ROM-based root of
trust
Secure Boot uninterruptible until system protection attributes
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are established
Authentication during boot using hardware hashing
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Step-wise authentication of execution images
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Secure execution of code in execute-only mode for protected
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routines
All Debug and Test ingress paths can be disabled
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Cryptography Accelerators
Hardware acceleration for Symmetric and Asymmetric
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cryptographic methods (AES, 3DES, RSA, and ECC) and Hash
functions (SHA-512, SHA-256)
True Random Number Generator (TRNG) function
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Capacitive Sensing
n Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR, liquid tolerance, and proximity sensing
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Mutual Capacitance sensing (Cypress CSX) with dynamic
usage of both Self and Mutual sensing
Wake on Touch with very low current
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Cypress-supplied software component makes capacitive
sensing design fast and easy
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Automatic hardware tuning (SmartSense)
Document Number: 002-24085 Rev. ** Page 2 of 60
PRELIMINARY
CYBLE-416045-02
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
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Overview: Module Roadmap
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PSoC 63 BLE Silicon Datasheet
Application Notes:
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AN96841 - Getting Started with EZ-BLE Module
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AN210781 - Getting Started with PSoC 6 MCU BLE
AN215656 - PSoC 6 MCU Dual-CPU System Design
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AN91162 - Creating a BLE Custom Profile
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AN217666 - PSoC 6 MCU Interrupts
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AN91445 - Antenna Design and RF Layout Guidelines
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AN213924 - PSoC 6 MCU Bootloader Guide
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AN219528 - PSoC 6 MCU Power Reduction Techniques
Technical Reference Manual (TRM):
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PSoC 63 with BLE Architecture Technical Reference Manual
PSoC 63 with BLE Registers Technical Reference Manual
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Knowledge Base Articles
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KBA97095 - EZ-BLE™ Module Placement
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KBA213976 - FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
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KBA210802 - Queries on BLE Qualification and Declaration
Processes
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Development Kits:
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CYBLE-416045-EVAL, CYBLE-416045-02 Evaluation Board
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CY8CKIT-062-BLE, PSoC 63 BLE Pioneer Kit
Test and Debug Tools:
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CYSmart, Bluetooth® LE Test and Debug Tool (Windows)
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CYSmart Mobile, Bluetooth® LE Test and Debug Tool
(Android/iOS Mobile App)
PSoC® Creator™ Integrated Design Environment (IDE)
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware
systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can:
1. Explore the library of 200+ Components in PSoC Creator
2. Drag and drop Component icons to complete your hardware
system design in the main design workspace
3. Configure Components using the Component Configuration
Tools and the Component datasheets
Figure 1. PSoC Creator Schematic Entry and Components
4. Co-design your application firmware and hardware in the
PSoC Creator IDE or build project for 3rd party IDE
5. Prototype your solution with the PSoC 6 Pioneer Kits.If a
design change is needed, PSoC Creator and Components
enable you to make changes on the fly without the need for
hardware revisions.
Document Number: 002-24085 Rev. ** Page 3 of 60
PRELIMINARY
CYBLE-416045-02
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem..................................... 5
System Resources ...................................................... 5
BLE Radio and Subsystem ......................................... 6
Analog Blocks.............................................................. 6
Programmable Digital.................................................. 7
Fixed-Function Digital.................................................. 7
GPIO ........................................................................... 8
Special-Function Peripherals ...................................... 8
Module Overview .............................................................. 9
Module Description...................................................... 9
Pad Connection Interface .............................................. 11
Recommended Host PCB Layout ................................. 12
Digital and Analog Capablities and Connections........ 14
Power............................................................................... 17
Critical Components List ........................................... 19
Antenna Design......................................................... 19
Electrical Specification .................................................. 20
Device-Level Specifications ...................................... 20
Analog Peripherals .................................................... 28
Digital Peripherals ..................................................... 36
Memory ..................................................................... 38
System Resources .................................................... 39
Environmental Specifications ....................................... 49
Environmental Compliance ....................................... 49
RF Certification.......................................................... 49
Environmental Conditions ......................................... 49
ESD and EMI Protection ........................................... 49
Regulatory Information.................................................. 50
FCC........................................................................... 50
ISED.......................................................................... 51
European Declaration of Conformity ......................... 52
MIC Japan................................................................. 52
Packaging........................................................................ 53
Ordering Information...................................................... 55
Part Numbering Convention...................................... 55
Acronyms........................................................................ 56
Document Conventions ................................................. 58
Units of Measure ....................................................... 58
Document History Page................................................. 59
Sales, Solutions, and Legal Information...................... 60
Worldwide Sales and Design Support....................... 60
Products .................................................................... 60
PSoC® Solutions ...................................................... 60
Cypress Developer Community................................. 60
Technical Support ..................................................... 60
Document Number: 002-24085 Rev. ** Page 4 of 60
PRELIMINARY
CYBLE-416045-02
Functional Definition
CPU and Memory Subsystem
CPU
The CPU subsystem in the More Part Numbers consists of two
Arm Cortex cores and their associated busses and memories:
M4 with Floating-point unit and Memory Protection Units (FPU
and MPU) and an M0+ with an MPU. The Cortex M4 and M0+
have 8-KB Instruction Caches (I-Cache) with 4-way set associativity. This subsystem also includes independent DMA
controllers with 32 channels each, a Cryptographic accelerator
block, 1 MB of on-chip Flash, 288 KB of SRAM, and 128 KB of
ROM.
The Cortex M0+ provides a secure, un-interruptible Boot
function. This guarantees that post-Boot, system integrity is
checked and privileges enforced. Shared resources can be
accessed through the normal Arm multi-layer bus arbitration and
exclusive accesses are supported by an Inter-Processor
Communication (IPC) scheme, which implements hardware
semaphores and protection. Active power consumption for the
Cortex M4 is 22 µA/MHz and 15 µA/MHz for the Cortex M0+,
both at 3.3 V chip supply voltage with the internal buck enabled
and at 0.9 V internal supply. Note that at Cortex M4 speeds
above 100 MHz, the M0+ and Peripheral subsystem are limited
to half the M4 speed. If the M4 is running at 150 Mhz, the M0+and
peripheral subsystem is limited to 75 MHz.
DMA Controllers
There are two DMA controllers with 16 channels each. They
support independent accesses to peripherals using the AHB
Multi-layer bus.
Flash
CYBLE-416045-02 has 1-MB of flash with additional 32K of
Flash that can be used for EEPROM emulation for longer
retention and a separate 32-KB block of Flash that can be
securely locked and is only accessible via a key lock that cannot
be changed (One Time Programmable).
SRAM with 32-KB Retention Granularity
There is 288 KB of SRAM memory, which can be fully retained
or retained in increments of user-designated 32-KB blocks.
SROM
There is a supervisory 128-KB ROM that contains boot and
configuration routines. This ROM will guarantee Secure Boot if
authentication of User Flash is required.
One-Time-Programmable (OTP) eFuse
The 1024-bit OTP memory can provide a unique and unalterable
Identifier on a per-chip basis. This unalterable key can be used
to access Secured Flash.
System Resources
Power System
The power system provides assurance that voltage levels are as
required for each respective mode and will either delay mode
entry (on power-on reset (POR), for example) until voltage levels
are as required for proper function or generate resets (Brown-Out
Detect (BOD)) when the power supply drops below specified
levels. The design will guaranteed safe chip operation between
power supply voltage dropping below specified levels (for
example, below 1.7 V) and the Reset occurring. There are no
voltage sequencing requirements. The VDD core logic supply
(1.7 to 3.6 V) will feed an on-chip buck, which will produce the
core logic supply of either 1.1 V or 0.9 V selectable. Depending
on the frequency of operation, the buck converter will have a
quiescent current of <1 µA. A separate power domain called
Backup is provided; note this is not a power mode. This domain
is powered from the VBACKUP domain and includes the 32-kHz
WCO, RTC, and backup registers. It is connected to VDD when
not used as a backup domain. Port 0 is powered from this supply.
Pin 5 of Port 0 (P0.5) can be assigned as a PMIC wakeup output
(timed by the RTC); P0.5 is driven to the resistive pull-up mode
by default.
Clock System
The Part Number clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no metastable conditions occur.
The clock system for the CYBLE-416045-02 consists of the
Internal Main Oscillator (IMO) and the Internal Low-speed Oscillator (ILO), crystal oscillators (ECO and WCO), PLL, FLL, and
provision for an external clock. An FLL will provide fast wake-up
at high clock speeds without waiting for a PLL lock event (which
can take up to 50 µs). Clocks may be buffered and brought out
to a pin on a Smart I/O port.
The 32-kHz oscillator is trimmable to within 2 ppm using a higher
accuracy clock. The ECO will deliver ±20-ppm accuracy and will
use an external crystal.
IMO Clock Source
The IMO is the primary source of internal clocking in More Part
Numbers. It is trimmed during testing to achieve the specified
accuracy. The IMO default frequency is 8 MHz. IMO tolerance is
±2% and its current consumption is less than 10 µA.
ILO Clock Source
The ILO is a very low power oscillator, nominally 32 kHz, which
may be used to generate clocks for peripheral operation in Deep
Sleep mode. ILO-driven counters can be calibrated to the IMO
to improve accuracy. Cypress provides a software component,
which does the calibration.
Document Number: 002-24085 Rev. ** Page 5 of 60
PRELIMINARY
CYBLE-416045-02
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO or from the WCO; this allows watchdog operation during
Deep Sleep and Hibernate modes, and generates a watchdog
reset if not serviced before the timeout occurs. The watchdog
reset is recorded in the Reset Cause register.
Clock Dividers
Integer and Fractional clock dividers are provided for peripheral
use and timing purposes. There are eight 8-bit integer and
sixteen 16-bit integer clock dividers. There is also one 24.5-bit
fractional and four 16.5-bit fractional clock dividers.
Reset
The More Part Numbers can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the Reset. An XRES pin is
reserved for external reset to avoid complications with
configuration and multiple pin functions during power-on or
reconfiguration.
BLE Radio and Subsystem
Part Number incorporates a Bluetooth Smart subsystem that
contains the Physical Layer (PHY) and Link Layer (LL) engines
with an embedded security engine. The physical layer consists
of the digital PHY and the RF transceiver that transmits and
receives GFSK packets at 2 Mbps over a 2.4-GHz ISM band,
which is compliant with Bluetooth Smart Bluetooth Specification
5.0. The baseband controller is a composite hardware and
firmware implementation that supports both master and slave
modes. Key protocol elements, such as HCI and link control, are
implemented in firmware. Time-critical functional blocks, such as
encryption, CRC, data whitening, and access code correlation,
are implemented in hardware (in the LL engine).
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-Ω antenna via a
matching/filtering network. In the receive direction, this block
converts the RF signal from the antenna to a digital bit stream
after performing GFSK demodulation. In the transmit direction,
this block performs GFSK modulation and then converts a digital
baseband signal to a radio frequency before transmitting it to air
through the antenna.
Key features of BLESS are as follows:
Master and slave single-mode protocol stack with logical link
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control and adaptation protocol (L2CAP), attribute (ATT), and
security manager (SM) protocols
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API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
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L2CAP connection-oriented channel (Bluetooth 4.1 feature)
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GAP features
Broadcaster, Observer, Peripheral, and Central roles
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Security mode 1: Level 1, 2, and 3
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p
User-defined advertising data
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Multiple bond support
GATT features
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GATT client and server
Supports GATT sub-procedures
p
p
32-bit universally unique identifier (UUID) (Bluetooth 4.1
feature)
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Security Manager (SM)
Pairing methods: Just works, Passkey Entry, and Out of Band
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LE Secure Connection Pairing model
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p
Authenticated man-in-the-middle (MITM) protection and data
signing
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Link Layer (LL)
Master and Slave roles
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128-bit AES engine
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Low-duty cycle advertising
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p
LE Ping
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Supports all SIG-adopted BLE profiles
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Power levels for Adv (1.28s, 31 bytes, 0 dBm) and Con
(300 ms, 0 byte, 0 dBm) are 42 µW and 70 µW respectively
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice of three internal voltage references, V
(nominally 1.024 V), as well as an external reference
V
REF
through a GPIO pin. The Sample-and-Hold (S/H) aperture is
programmable; it allows the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling
time, to be relaxed if required. System performance will be 65 dB
for true 12-bit precision provided appropriate references are
used and system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an external
bypass (through a fixed pin location) for the internal reference
amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through the selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, the aggregate sampling bandwidth is equal to
1 Msps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware-driven switching. A feature
provided by the sequencer is the buffering of each channel to
reduce CPU interrupt-service requirements. To accommodate
signals with varying source impedances and frequencies, it is
possible to have different sample times programmable for each
channel. Also, the signal range specification through a pair of
range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value
exceeds the programmed range; this allows fast detection of
out-of-range values without having to wait for a sequencer scan
to be completed and the CPU to read the values and check for
out-of-range values in software. There are 16 channels of which
any 13 can be sampled in a single scan.
, VDD/2, and
DD
Document Number: 002-24085 Rev. ** Page 6 of 60
PRELIMINARY
CYBLE-416045-02
The SAR is able to digitize the output of the on-chip temperature
sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 V to 3.6 V.
Temperature Sensor
Part Number has an on-chip temperature sensor. This consists
of a diode, which is biased by a current source that can be
disabled to save power. The temperature sensor is connected to
the ADC, which digitizes the reading and produces a temperature value by using a Cypress-supplied software that includes
calibration and linearization.
12-bit Digital-Analog Converter
There is a 12-bit voltage mode DAC on the chip, which can settle
in less than 5 µs. T he DAC may be dri ven by the DMA co ntrollers
to generate user-defined waveforms. The DAC output from the
chip can either be the resistive ladder output (highly linear near
ground) or a buffered output.
Continuous Time Block (CTBm) with Two Opamps
This block consists of two opamps, which have their inputs and
outputs connected to fixed pins and have three power modes
and a comparator mode. The outputs of these opamps can be
used as buffers for the SAR inputs. The non-inverting inputs of
these opamps can be connected to either of two pins, thus
allowing independent sensors to be used at different times. The
pin selection can be made via firmware. The opamps can be set
to one of the four power levels; the lowest level allowing
operation in Deep Sleep mode in order to preserve lower performance Continuous-Time functionality in Deep Sleep mode. The
DAC output can be buffered through an opamp.
Low-Power Comparators
CYBLE-416045-02 has a pair of low-power comparators, which
can also operate in Deep Sleep and Hibernate modes. This
allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during Deep Sleep
and Hibernate modes. The comparator outputs are normally
synchronized to avoid metastability unless operating in an
asynchronous power mode (Hibernate) where the system
wake-up circuit is activated by a comparator-switch event.
Programmable Digital
Smart I/O
There are two Smart I/O blocks, which allow Boolean operations
on signals going to the GPIO pins from the subsystems of the
chip or on signals coming into the chip. Operation can be
synchronous or asynchronous and the blocks operate in
low-power modes, such as Deep Sleep and Hibernate.This
allows, for example, detection of logic conditions that can
indicate that the CPU should wake up instead of waking up on
general I/O interrupts, which consume more power and can
generate spurious wake-ups.
Universal Digital Blocks (UDBs) and Port Interfaces
The CYBLE-416045-02 has 12 UDBs; the UDB array also
provides a switched Digital System Interconnect (DSI) fabric that
allows signals from peripherals and ports to be routed to and
through the UDBs for communication and control.
Fixed-Function Digital
Timer/Counter/PWM Block
The timer/counter/PWM block consists of 32 counters with
user-programmable period length. There is a Capture register to
record the count value at the time of an event (which may be an
I/O event), a period register which is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals which are used as PWM duty cycle outputs. The block
also provides true and complementary outputs with
programmable offset between them to allow the use as
deadband programmable complementary PWM outputs. It also
has a Kill input to force outputs to a predetermined state; for
example, this is used in motor-drive systems when an
overcurrent state is indicated and the PWMs driving the FETs
need to be shut off immediately with no time for software
intervention. There are eight 32-bit counters and 24 16-bit
counters.
Serial Communication Blocks (SCB)
Part Number has nine SCBs, which can each implement an I
UART, or SPI interface. One SCB will operate in Deep Sleep with
an external clock, this SCB will only operate in Slave mode
(requires external clock).
2
I
C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce the interrupt overhead and latency for the CPU. It also
supports EzI2C that creates a mailbox address range in the
memory of Part Number and effectively reduces the I2C communication to reading from and writing to an array in the memory. In
addition, the block supports a 256 byte-deep FIFO for receive
and transmit, which, by increasing the time given for the CPU to
read the data, greatly reduces the need for clock stretching
caused by the CPU not having read the data on time. The FIFO
mode is available in all channels and is very useful in the
absence of DMA.
2
The I
C peripheral is compatible with I2C Standard-mode,
Fast-mode, and Fast-Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
UART Mode: This is a full-feature UART operating at up to
8 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows the
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. A 256 byte-deep FIFO
allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used
to synchronize SPI Codecs), and National Microwire (half-duplex
form of SPI). The SPI block can use the FIFO and supports an
EzSPI mode in which the data interchange is reduced to reading
and writing an array in memory. The SPI interface will operate
with a 25-MHz SPI Clock.
2
C,
Document Number: 002-24085 Rev. ** Page 7 of 60
PRELIMINARY
CYBLE-416045-02
GPIO
CYBLE-416045-02 has up to 36 GPIOs. The GPIO block implements the following:
n
Eight drive strength modes:
p Analog input mode (input and output buffers disabled)
p
Input only
p
Weak pull-up with strong pull-down
p
Strong pull-up with weak pull-down
Open drain with strong pull-down
p
Open drain with strong pull-up
p
Strong pull-up with strong pull-down
p
Weak pull-up with weak pull-down
p
n
Input threshold select (CMOS or LVTTL)
n
Hold mode for latching previous state (used for retaining the
I/O state in Deep Sleep and Hibernate modes)
Selectable slew rates for dV/dt-related noise control to improve
n
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix (HSIOM) is used to multiplex between
various signals that may connect to an I/O pin. Data output and
pin state registers store, respectively, the values to be driven on
the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it. Six G PIO pins are capable
of overvoltage tolerant (OVT) operation where the input voltage
may be higher than VDD (these may be used for I2C functionality
to allow powering the chip off while maintaining physical
connection to an operating I
ality).
GPIO pins can be ganged to sink 16 mA or higher values of sink
current. GPIO pins, including OVT pins, may not be pulled up
higher than 3.6 V.
2
C bus without affecting its function-
analog multiplexed bus. Any GPIO pin can be connected to this
AMUX bus through an analog switch. CapSense function can
thus be provided on any pin or a group of pins in a system under
software control. Cypress provides a software component for the
CapSense block for ease-of-use.
Shield voltage can be driven on another mux bus to provide
water-tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Proximity sensing can also be implemented.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
The CapSense block has two 7-bit IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available). A (slow) 10-bit Slope ADC
may be realized by using one of the IDACs.
The block can implement Swipe, Tap, Wake-up on Touch
(< 3 µA at 1.8 V), mutual capacitance, and other types of sensing
functions.
Audio Subsystem
This subsystem consists of an I2S block and two PDM channels.
The PDM channels interface to a PDM microphone's bit-stream
output. The PDM processing channel provides droop correction
and can operate with clock speeds ranging from 384 kHz to
3.072 MHz and produce word lengths of 16 to 24 bits at audio
sample rates of up to 48 ksps.
The I2S interface supports both Master and Slave modes with
Word Clock rates of up to 192 ksps (8-bit to 32-bit words).
Special-Function Peripherals
CapSense
CapSense is supported on all pins in the Part Number through a
CapSense Sigma-Delta (CSD) block that can be connected to an
Document Number: 002-24085 Rev. ** Page 8 of 60
PRELIMINARY
CYBLE-416045-02
Module Overview
Module Description
The CYBLE-416045-02 module is a complete module designed to be soldered to the main host board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should
be completed with the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item Specification
Module dimensions
Antenna location dimensions
PCB thickness Height (H) 0.80 ± 0.10 mm
Shield height Height (H) 1.20 ± 0.10 mm
Maximum component height Height (H) 1.20 mm typical (shield)
Total module thickness (bottom of module to highest component) Height (H) 2.00 mm typical
See Figure 2 on page 10 for the mechanical reference drawing for CYBLE-416045-02.
Length (X) 14.00 ± 0.15 mm
Width (Y) 18.50 ± 0.15 mm
Length (X) 14.00 ± 0.15 mm
Width (Y) 4.62 ± 0.15 mm
Document Number: 002-24085 Rev. ** Page 9 of 60
PRELIMINARY
CYBLE-416045-02
Figure 2. Module Mechanical Drawing
Top View
Bottom View (Seen from Bottom)
Side View
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 4 on page 11, Figure 5 and Figure 6 on page 12, and Figure 7 and Ta bl e 3 on page 13.
Document Number: 002-24085 Rev. ** Page 10 of 60
PRELIMINARY
CYBLE-416045-02
Pad Connection Interface
Host PCB Keep-Out Area Around Trace Antenna
As shown in the bottom view of Figure 2 on page 10, the CYBLE-416045-02 connects to the host board via solder pads on the back
of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBLE-416045-02 module.
Table 2. Solder Pad Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 43 Solder Pads 1.02 mm 0.61 mm 0.90 mm
Figure 3. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host
board. This placement minimizes the additional recommended keep-out area stated in item 2. Please refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm).
Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-416045-02 Trace Antenna
Document Number: 002-24085 Rev. ** Page 11 of 60
PRELIMINARY
CYBLE-416045-02
Recommended Host PCB Layout
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Figure 5 through Figure 7 and Ta b le 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-416045-02. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad
on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 5. Host Layout Pattern for CYBLE-416045-02 Figure 6. Module Pad Location from Origin
Document Number: 002-24085 Rev. ** Page 12 of 60
PRELIMINARY
CYBLE-416045-02
Ta bl e 3 provides the center location for each solder pad on the CYBLE-416045-02. All dimensions reference the to the center of the
Top View (Seen on Host PCB)
solder pad. Refer to Figure 7 for the location of each module solder pad.
Table 3. Module Solder Pad Location
Solder Pad
(Center of Pad)
1 (0.38, 4.93) (14.96, 194.09)
2 (0.38, 5.83) (14.96, 229.53)
3 (0.38, 6.73) (14.96, 264.96)
4 (0.38, 7.63) (14.96, 300.39)
5 (0.38, 8.54) (14.96, 336.22)
6 (0.38, 9.44) (14.96, 371.65)
7 (0.38, 10.34) (14.96, 407.09)
8 (0.38, 11.24) (14.96, 442.52)
9 (0.38, 12.14) (14.96, 477.95)
10 (0.38, 13.04) (14.96, 513.38)
11 (0.38, 13.95) (14.96, 549.21)
12 (0.38, 14.85) (14.96, 584.64)
13 (0.38, 15.75) (14.96, 620.08)
14 (0.38, 16.65) (14.96, 655.51)
15 (0.69, 18.12) (27.17, 713.38)
16 (1.59, 18.12) (62.60, 713.38)
17 (2.49, 18.12) (98.03, 713.38)
18 (3.39, 18.12) (133.46, 713.38)
19 (4.29, 18.12) (168.90, 713.38)
20 (5.20, 18.12) (204.72, 713.38)
21 (6.10, 18.12) (240.16, 713.38)
22 (7.00, 18.12) (275.59, 713.38)
23 (7.90, 18.12) (311.02, 713.38)
24 (8.80, 18.12) (346.46, 713.38)
25 (9.70, 18.12) (381.89, 713.38)
26 (10.61, 18.12) (417.72, 713.38)
27 (11.51, 18.12) (453.15, 713.38)
28 (12.41, 18.12) (488.58, 713.38)
29 (13.31, 18.12) (524.01, 713.38)
30 (13.62, 16.65) (536.22, 655.51)
31 (13.62, 15.75) (536.22, 620.08)
32 (13.62, 14.85) (536.22, 584.64)
33 (13.62, 13.95) (536.22, 549.21)
34 (13.62, 13.04) (536.22, 513.38)
35 (13.62, 12.14) (536.22, 477.95)
36 (13.62, 11.24) (536.22, 442.52)
37 (13.62, 10.34) (536.22, 407.09)
38 (13.62, 9.44) (536.22, 371.65)
39 (13.62, 8.54) (536.22, 336.22)
40 (13.62, 7.63) (536.22, 300.39)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
Figure 7. Solder Pad Reference Location
41 (13.62, 6.73) (536.22, 264.96)
42 (13.62, 5.83) (536.22, 229.53)
43 (13.62, 4.93) (536.22, 194.09)
Document Number: 002-24085 Rev. ** Page 13 of 60
PRELIMINARY
CYBLE-416045-02
Digital and Analog Capablities and Connections
Ta bl e 4 and Ta bl e 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the
solder pads on CYBLE-416045-02, the BLE device port-pin, and denotes whether the digital function shown is available for each
solder pad. Tab le 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for
a single option shown with a
Table 4. Digital Peripheral Capabilities
Pad
Number
Device
Port Pin
1GND
2P0.53(scb0_CTS) 3(scb0_SS0) tcpwm[0].line_compl[2]
3 VBACKUP Battery Backup Domain Input Voltage (1.71 V to 3.6 V)
4 VDD Power Supply Input Voltage (1.71 V to 3.6 V)
5P0.0 3(scb0_SS1) tcpwm[0].line[0]
6P0.1 3(scb0_SS2) tcpwm[0].line_compl[0]
7 P10.3 3(scb1_CTS) 3(scb1_SS0) tcpwm[0].line_compl[7]
8 P10.4 3(scb1_SS1) tcpwm[0].line[0]
9P9.33(scb2_CTS) 3(scb2_SS0) tcpwm[0].line_compl[5]
10 P10.6 3(scb1_SS3) tcpwm[0].line[1]
11 P10.5 3(scb1_SS2) tcpwm[0].line_compl[0]
12 P10.1 3(scb1_TX) 3 (scb1_MISO) 3(scb1_SDA) tcpwm[0].line_compl[6]
13 P10.0 3(scb1_RX) 3(scb1_MOSI) 3(scb1_SCL) tcpwm[0].line[6]
14 P9.4 3(scb2_SS1) tcpwm[0].line[7]
15 GND Ground Connection
16 VREF Voltage Reference Input (Optional)
17 P9.0 3(scb2_RX) 3(scb2_MOSI) 3(scb2_SCL) tcpwm[0].line[4]
18 P9.1 3(scb2_TX) 3(scb2_MISO) 3(scb2_SDA) tcpwm[0].line_compl[4]
19 P9.5 3(scb2_SS2) tcpwm[0].line_compl[7]
20 P9.6 3(scb2_SS3) tcpwm[0].line[0]
21 P9.2 3(scb2_RTS) 3(scb2_SCLK) tcpwm[0].line[5]
22 P7.2 3(scb4_RTS) 3(scb4_SCLK) tcpwm[0].line[5]
23 P7.1 3(scb4_TX) 3(scb4_MISO) 3(scb4_SDA) tcpwm[0].line_compl[4]
24 P6.4 3(SCB6_RX) 3(scb6_MOSI)
25 P5.4 3(scb5_SS1) tcpwm[0].line[6]
26 P6.7 3(scb6_CTS) 3(scb6_SS0)
27 P6.6 3(scb6_RTS) 3(scb6_SCLK)
28 P6.2 3(scb3_RTS) 3(scb3_SCLK)
29 P6.5 3(scb6_TX) 3(scb6_MISO)
UART SPI I2C TCPWM
[4]
3.
(scb8_MOSI)
(scb8_SS0)
(scb8_SCLK)
(scb8_SCLK)
(scb8_MISO)
3(scb8_SCL)
(scb6_SCL)
3(scb8_SDA)
3(scb6_SDA)
[2,3]
Ground Connection
tcpwm[1].line_compl[2]
tcpwm[1].line[0]
tcpwm[1].line_compl[0]
tcpwm[1].line_compl[23]
tcpwm[1].line[0]
tcpwm[1].line_compl[21]
tcpwm[1].line[2]
tcpwm[1].line_compl[0]
tcpwm[1].line_compl[22]
tcpwm[1].line[22]
tcpwm[1].line[0]
tcpwm[1].line[20]
tcpwm[1].line_compl[20]
tcpwm[1].line_compl[0]
tcpwm[1].line[1]
tcpwm[1].line[21]
tcpwm[1].line[13]
tcpwm[1].line_compl[12]
tcpwm[0].line[2]
tcpwm[1].line[10]
tcpwm[1].line[6]
tcpwm[0].line_compl[3]
tcpwm[1].line_compl[11
tcpwm[0].line[3]
tcpwm[1].line[11]
tcpwm[0].line[1]
tcpwm[1].line[9]
tcpwm[0].line_compl[2]
tcpwm[1].line_compl[10]
Cap
EXT_CLK
Sense
_IN
33 3
33 3
33(JTAG RST) 3
33
33PDM_CLK 3
3 ctb_cmp1 3
33
33PDM_DATA 3
33
33
33
33
33
33
33
3 ctb_cmp0 3
33
33
33(JTAG TDO) 3
33I2S_SCK_RX 3
33(SWDCLK)
33(SWDIO)
33
33(JTAG TDI) 3
AUDIO
CMP Dig-
ital Out
SWD/JTAG GPIO
(JTAG TCLK)
(JTAG TMS)
3
3
Document Number: 002-24085 Rev. ** Page 14 of 60
PRELIMINARY
CYBLE-416045-02
Table 4. Digital Peripheral Capabilities
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive
or negative polarity.
4. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
30 P6.3 3(scb3_CTS) 3(scb3_SS0)
31 P7.7 3(scb3_SS1) tcpwm[0].line_compl[7]
32 P5.6 3(scb5_SS3) tcpwm[0].line[7]
33 P10.2 3(scb1_RTS) 3(scb1_SCLK) tcpwm[0].line[7]
34 P12.6 3(scb6_SS3) tcpwm[0].line[7]
35 P12.7 tcpwm[0].line_compl[7]
36 P5.5 3(scb5_SS2) tcpwm[0].line_compl[6]
37 P5.3 3(scb5_CTS) 3(scb5_SS0) cpwm[0].line_compl[5]
38 P5.2 3(scb5_RTS) 3(scb5_SCLK) tcpwm[0].line[5]
39 P5.0 3(scb5_RX) 3(scb5_MOSI) 3(scb5_SCL) tcpwm[0].line[4]
40 P5.1 3(scb5_TX) 3(scb5_MISO) 3(scb5_SDA) tcpwm[0].line_compl[4]
41 P0.4 3(scb0_RTS) 3(scb0_SCLK) tcpwm[0].line[2]
42 XRES External Reset (Active Low)
43 GND
[4]
(scb8_SS0)
tcpwm[0].line_compl[1]
tcpwm[1].line_compl[9]
tcpwm[1].line_compl[15]
tcpwm[1].line[7]
tcpwm[1].line[23]
tcpwm[1].line[7]
tcpwm[1].line_compl[7]
tcpwm[1].line_compl[6]
tcpwm[1].line_compl[5]
tcpwm[1].line[5]
tcpwm[1].line[4]
tcpwm[1].line_compl[4]
tcpwm[1].line[2]
Ground Connection
33
33
33I2S_SDI_RX 3
33
33
33
33I2S_WS_RX 3
33I2S_SDO_TX 3
33I2S_WS_TX 3
33I2S_EXT_CLK 3
33I2S_CLK_TX 3
33
Document Number: 002-24085 Rev. ** Page 15 of 60
PRELIMINARY
CYBLE-416045-02
Table 5. Additional Analog and Digital Functional Capabilities
Pad Number Device Port Pin Analog Functionality Digital HV
1 GND Ground Connection
2P0.5 3(pmic_wakeup_out) 3(UDB0[5])
3 VBACKUP Battery Backup Domain Input Voltage (1.71 V to 3.6 V)
4 VDD Power Supply Input Voltage (1.71 V to 3.6 V)
5P0.0wco_in 3(UDB0[0])
6 P0.1 wco_out 3(UDB0[1])
7 P10.3 sarmux[3] 3(UDB9[3])
8 P10.4 sarmux[4] 3(UDB9[4])
9 P9.3 ctb_oa1_out 3(UDB10[3]) SMARTIO10[3]
10 P10.6 sarmux[6] 3(UDB9[6])
11 P10.5 sarmux[5] 3(UDB9[5])
12 P10.1 sarmux[1] 3(UDB9[1])
13 P10.0 sarmux[0] 3(UDB9[0])
14 P9.4 ctb_oa1- 3(UDB10[4]) SMARTIO9[4]
15 GND Ground Connection
16 VREF Reference Voltage Input (Optional)
17 P9.0 ctb_oa0+ 3(UDB10[0]) SMARTIO9[0]
18 P9.1 ctb_oa0- 3(UDB10[1]) SMARTIO9[1]
19 P9.5 ctb_oa1+ 3(UDB10[5]) SMARTIO9[5]
20 P9.6 ctb_oa0+ 3(UDB10[6]) SMARTIO9[6]
21 P9.2 ctb_oa0_out 3(UDB10[2]) SMARTIO9[2]
22 P7.2 csd.csh_tankpadd
23 P7.1 csd.cmodpadd
24 P6.4 3(UDB4[4])
25 P5.4 3(UDB3[5])
26 P6.7 swd_clk 3(UDB4[7])
27 P6.6 swd_data 3(UDB4[6])
28 P6.2 lpcomp.inp_comp1 3(UDB4[2])
29 P6.5 3(UDB4[5])
30 P6.3 lpcomp.inn_comp1 3(UDB4[3])
31 P7.7 csd.cshieldpads 3(UDB5[7])
32 P5.6 lpcomp.inp_comp0 3(UDB3[6])
33 P10.2 sarmux[2] 3(UDB9[2])
34 P12.6 ECO_IN 3(UDB7[6])
35 P12.7 ECO_OUT 3(UDB7[7])
36 P5.5 3(UDB3[5])
37 P5.3 3
38 P5.2 3(UDB3[2])
39 P5.0 3(UDB3[0])
40 P5.1 3(UDB3[1])
41 P0.4 pmic_wakeup_in
42 XRES External Reset (Active Low)
43 GND Ground Connection
csd.csh_tankpads
csd.cmodpads
hibernate_wakeup[1]
Universal Digital
Block (UDB)
3(UDB5[2])
3(UDB5[1])
(UDB3[3])
3(UDB0[4])
SMARTIO
Document Number: 002-24085 Rev. ** Page 16 of 60
PRELIMINARY
CYBLE-416045-02
Power
The power connection diagram (see Figure 8) shows the general requirements for power pins on the CYBLE-416045-02. The
CYBLE-416045-02 contains a single power supply connection (VDD) and a backup voltage input (VBACKUP).
Description of the power pins is as follows:
1. VBACKUP is the supply to the backup domain. The backup domain includes the 32 kHz WCO, RTC, and backup registers. It
can generate a wake-up interrupt to the chip via the RTC timers or an external input. It can also generate an output to wakeup
external circuitry. It is connected to VDD when not used as a separate battery backup domain. VBACKUP provides the supply
for Port 0.
2. VDD is the main power supply input (1.7 to 3.6V). It provides the power input to the digital, analog and radio domains. Isolation
required for these domains is integrated on-module, therefore no additional isloation is required for the CYBLE-416045-02.
The supply voltage range is 1.71 to 3.6 V with all functions and circuits operating over that range. All ground connections specified
must be connected to system ground.
VDD and VBACKUP may be shorted together externally. They are not required to be seperate inputs voltages.
Figure 8. CYBLE-416045-02 Power Connections
Document Number: 002-24085 Rev. ** Page 17 of 60
PRELIMINARY
CYBLE-416045-02
The CYBLE-416045-02 schematic is shown in Figure 9.
Figure 9. CYBLE-416045-02 Schematic Diagram
Document Number: 002-24085 Rev. ** Page 18 of 60
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