Cypress Semiconductor 4008 User Manual

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PRELIMINARY

CYBLE-214009-00

EZ-BLE

PSoC® Module

General Description

The Cypress CYBLE-214009-00 is a fully certified and qualified module supporting Bluetooth



Low Energy (BLE) wireless communication. The CYBLE-214009-00 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC

PSoC

4 BLE datasheet for additional details on the capabilities

of the PSoC

4 BLE device used on this module.

4 BLE. Refer to the

The EZ-BLETM PSoC® module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-214009-00 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals.

The CYBLE-214009-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a small 11 × 11 × 1.80 mm package.

The CYBLE-214009-00 is a complete solution and an ideal fit for applications seeking a highly integrated BLE wireless solution.

CYBLE-214009-00 is drop-in compatible CYBLE-014008-00.

Module Description

n Module size: 11.0 mm × 11.0 mm × 1.80 mm (with shield)

n Bluetooth 4.1 single-mode module

n Industrial temperature range: –40 °C to +85 °C

n 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit

multiply, operating at up to 48 MHz

n 256-KB flash memory, 32-KB SRAM memory

n Watchdog timer with dedicated internal low-speed oscillator

(ILO)

n Two-pin SWD for programming

n Up to 25 GPIOs configurable as open drain high/low,

pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output

n Certified to FCC, CE, MIC, KC, and IC regulations

n Bluetooth SIG 4.1 qualified

Power Consumption

n TX output power: –18 dbm to +3 dbm

n Received signal strength indicator (RSSI) with 1-dB resolution

n TX current consumption of 15.6 mA (radio only, 0 dbm)

n RX current consumption of 16.4 mA (radio only)

n Low power mode support

p Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on p Hibernate: 150 nA with SRAM retention p Stop: 60 nA with XRES wakeup

Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-09714 Rev. **

Revised October 29, 2015

Programmable Analog

n Four opamps with reconfigurable high-drive external and

high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode.

n 12-bit, 1-Msps SAR ADC with differential and single-ended

modes; channel sequencer with signal averaging

n Two current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

n One low-power comparator that operate in Deep-Sleep mode

Programmable Digital

n Four programmable logic blocks called universal digital blocks,

(UDBs), each with eight macrocells and datapath

n Cypress-provided peripheral Component library, user-defined

state machines, and Verilog input

Capacitive Sensing

n Cypress CapSense Sigma-Delta (CSD) provides best-in-class

SNR (> 5:1) and liquid tolerance

n Cypress-supplied software component makes

capacitive-sensing design easy

n Automatic hardware-tuning algorithm (SmartSense™)

Segment LCD Drive

n LCD drive supported on all GPIOs (common or segment) n Operates in Deep-Sleep mode with four bits per pin memory

Serial Communication

n Two independent runtime reconfigurable serial communication

blocks (SCBs) with I

C, SPI, or UART functionality

Timing and Pulse-Width Modulation

n Four 16-bit timer, counter, pulse-width modulator (TCPWM)

blocks

n Center-aligned, Edge, and Pseudo-random modes n Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

Up to 25 Programmable GPIOs

n Any GPIO pin can be CapSense, LCD, analog, or digital n Two overvoltage-tolerant (OVT) pins; drive modes, strengths,

and slew rates are programmable

PRELIMINARY

CYBLE-214009-00

Overview............................................................................ 3

Module Description...................................................... 3

Pad Connection Interface ................................................ 5

Recommended Host PCB Layout ................................... 6

Power Supply Connections and Recommended External

Components.................................................................... 10

Connection Options................................................... 10

External Component Recommendation .................... 10

Critical Components List ........................................... 13

Antenna Design......................................................... 13

Electrical Specification .................................................. 14

GPIO ......................................................................... 16

XRES......................................................................... 17

Analog Peripherals .................................................... 17

Digital Peripherals ..................................................... 21

Serial Communication ............................................... 23

Memory ..................................................................... 24

System Resources .................................................... 24

Environmental Specifications ....................................... 30

Environmental Compliance ....................................... 30

RF Certification.......................................................... 30

Environmental Conditions ......................................... 30

ESD and EMI Protection ........................................... 30

Regulatory Information.................................................. 31

FCC........................................................................... 31

Industry Canada (IC) Certification............................. 32

European R&TTE Declaration of Conformity ............ 32

MIC Japan................................................................. 33

KC Korea................................................................... 33

Ordering Information...................................................... 34

Part Numbering Convention...................................... 34

Acronyms........................................................................ 35

Document Conventions ................................................. 37

Units of Measure ....................................................... 37

Errata ............................................................................... 38

Document History Page................................................. 39

Sales, Solutions, and Legal Information...................... 40

Worldwide Sales and Design Support....................... 40

Products .................................................................... 40

PSoC® Solutions ...................................................... 40

Cypress Developer Community................................. 40

Technical Support ..................................................... 40

Document Number: 002-09714 Rev. ** Page 2 of 40

PRELIMINARY

CYBLE-214009-00

Overview

Module Description

The CYBLE-214009-00 module is a complete module designed to be soldered to the main host board.

Module Dimensions and Drawing

Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions

PCB thickness Height (H) 0.80 ± 0.10 mm Shield height Height (H) 1.00 ± 0.10 mm Maximum component height Height (H) 1.00 mm typical (shield) Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical

See Figure 1 on page 4 for the mechanical reference drawing for CYBLE-214009-00.

Length (X) 11.00 ± 0.15 mm

Width (Y) 11.00 ± 0.15 mm

Length (X) 11.00 ± 0.15 mm

Width (Y) 4.62 ± 0.15 mm

Document Number: 002-09714 Rev. ** Page 3 of 40

PRELIMINARY

CYBLE-214009-00

Figure 1. Module Mechanical Drawing

Top View

Side View

Bottom View

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 and Figure 4 on page 6.

Document Number: 002-09714 Rev. ** Page 4 of 40

PRELIMINARY

CYBLE-214009-00

Pad Connection Interface

As shown in the bottom view of Figure 1 on page 4, the CYBLE-214009-00 connects to the host board via solder pads on the back of the module. Tab l e 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-214009-00 module.

Table 2. Solder Pad Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 32 Solder Pads

Pad9/Pad24: 0.74 mm

All Others: 0.79 mm

Figure 2. Solder Pad Dimensions

0.41 mm 0.66 mm

Document Number: 002-09714 Rev. ** Page 5 of 40

PRELIMINARY

CYBLE-214009-00

Recommended Host PCB Layout

Top View (On Host PCB)

Host PCB Keep-Out Area Around Trace Antenna

Figure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm.

Figure 3. Recommended PCB Layout Pattern for CYBLE-214009-00

To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2.

2. It is recommended that the area around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm).

Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-214009-00 Trace Antenna

Document Number: 002-09714 Rev. ** Page 6 of 40

PRELIMINARY

CYBLE-214009-00

Ta bl e 3 details the solder pad pitch (center-to-center) for each of the neighboring connections.

Table 3. Module Solder Pad Connection Dimensions

Pad X Pad Y Pad Pitch (Pad X - Pad Y) Comments

Bottom Right Corner 1 4.83 mm Distance from bottom right corner to Pad 1 center

1 2 0.66 mm Distance from Pad 1 center to Pad 2 center 2 3 0.66 mm Distance from Pad 2 center to Pad 3 center 3 4 0.66 mm Distance from Pad 3 center to Pad 4 center 4 5 0.66 mm Distance from Pad 4 center to Pad 5 center 5 6 0.66 mm Distance from Pad 5 center to Pad 6 center 6 7 0.66 mm Distance from Pad 6 center to Pad 7 center 7 8 0.66 mm Distance from Pad 7 center to Pad 8 center 8 9 0.66 mm Distance from Pad 8 center to Pad 9 center

Top Right Corner 10 1.21 mm Distance from Pad 9 center to Pad 10 center

10 11 0.66 mm Distance from Pad 10 center to Pad 11 center 11 12 0.66 mm Distance from Pad 11 center to Pad 12 center 12 13 0.66 mm Distance from Pad 12 center to Pad 13 center 13 14 0.66 mm Distance from Pad 13 center to Pad 14 center 14 15 0.66 mm Distance from Pad 14 center to Pad 15 center 15 16 0.66 mm Distance from Pad 15 center to Pad 16 center 16 17 0.66 mm Distance from Pad 16 center to Pad 17 center 17 18 0.66 mm Distance from Pad 17 center to Pad 18 center 18 19 0.66 mm Distance from Pad 18 center to Pad 19 center 19 20 0.66 mm Distance from Pad 19 center to Pad 20 center 20 21 0.66 mm Distance from Pad 20 center to Pad 21 center 21 22 0.66 mm Distance from Pad 21 center to Pad 22 center 22 23 0.66 mm Distance from Pad 22 center to Pad 23 center

Top Left Corner 24 0.89 mm Distance from Top Left Corner to Pad 24 center

24 25 0.66 mm Distance from Pad 24 center to Pad 25 center 25 26 0.66 mm Distance from Pad 25 center to Pad 26 center 26 27 0.66 mm Distance from Pad 26 center to Pad 27 center 27 28 0.66 mm Distance from Pad 27 center to Pad 28 center 28 29 0.66 mm Distance from Pad 28 center to Pad 29 center 29 30 0.66 mm Distance from Pad 29 center to Pad 30 center 30 31 0.66 mm Distance from Pad 30 center to Pad 31 center 31 32 0.66 mm Distance from Pad 31 center to Pad 32 center 32 Bottom Left Corner 4.83 mm Distance from Pad 32 center to Bottom Left Corner

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PRELIMINARY

CYBLE-214009-00

Ta bl e 4 and Ta bl e 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the

Notes

2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.

3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.

solder pads on CYBLE-214009-00, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Tab le 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a

Table 4. Digital Peripheral Capabilities

Pad

Number

Device

Port Pin

1GND 2P1.1 3P1.0 3(TCPWM0) 333 4P1.53(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2) 333 5P0.13(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0) 333 6P0.73(SCB0_CTS) 3(SCB0_SCLK) 3(TCPWM2) 33

7 VDD Digital Power Supply Input (1.71 to 5.5V) 8P1.4

9P0.43(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1) 333 3 10 P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1) 333 11 P0 .6 3(SCB0_RTS) 3(SCB0_SS0)

12 P1.2 3(SCB1_SS2) 3(TCPWM1) 333 13 V 14 P2.6 15 P1.3 3(SCB1_SS3) 3(TCPWM1) 333 16 P3.0 3(SCB0_RX) 3(SCB0_SDA) 3(TCPWM0) 333 17 P2.1 3(SCB0_SS2) 333 18 P2.2 3(SCB0_SS3) 333 19 P2.3 33 3 3 20 VDDA Analog Power Supply Input (1.71 to 5.5V) 21 P3.4 22 P3.1 3(SCB0_TX) 3(SCB0_SCL) 3(TCPWM0) 333 23 P3.7 3(SCB1_CTS) 3(TCPWM3) 33 3 3 24 P3.5 3(SCB1_TX) 3(SCB1_SCL) 3(TCPWM2) 333 25 P3.3 3(SCB0_CTS) 3(TCPWM1) 333 26 VREF Reference Voltage Input 27 P3.2 28 P3.6 3(SCB1_RTS) 3(TCPWM3) 333 29 XRES External Reset Hardware Connection Input 30 P2.4 31 P2.5 333 32 GND Ground Connection

[3]

DDR

UART SPI I2C TCPWM

Ground Connection

3(SCB1_SS1) 3(TCPWM0) 333

3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2) 333

3(TCPWM2) 333

Radio Power Supply (1.9V to 5.5V)

3(SCB1_RX) 3(SCB1_SDA) 3(TCPWM2) 333

3(SCB0_RTS) 3(TCPWM1) 333

Cap-

[2]

Sense

WCO

Out

ECO

LCD SWD GPIO

OUT

(SWDCLK)

(SWDIO)

333

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PRELIMINARY

CYBLE-214009-00

Table 5. Analog Peripheral Capabilities

Pad Number Device Port Pin SARMUX OPAMP LPCOMP

1GND 2P1.1 3P1.0 4P1.5 5P0.1 6P0.7 7 VDD Digital Power Supply Input (1.71 to 5.5V) 8P1.4

9P0.4 10 P0.5 11 P0 .6 12 P1.2 13 V 14 P2.6 15 P1.3 16 P3.0 17 P2.1 3(CTBm1_OA0_INN) 18 P2.2 19 P2.3 20 VDDA Analog Power Supply Input (1.71 to 5.5V) 21 P3.4 22 P3.1 3 23 P3.7 3 24 P3.5 3 25 P3.3 3 26 VREF Reference Voltage Input (Optional) 27 P3.2 28 P3.6 3 29 XRES External Reset Hardware Connection Input 30 P2.4 31 P2.5 32 GND Ground Connection

DDR

[3]

Ground Connection

3(CTBm1_OA0_INN) 3(CTBm1_OA0_INP) 3(CTBm1_OA1_INP)

3(COMP0_INN)

3(CTBm1_OA1_INN)

3(COMP1_INP) 3(COMP1_INN)

3(CTBm1_OA0_OUT)

Radio Power Supply (1.9V to 5.5V)

3(CTBm1_OA0_INP)

3(CTBm1_OA1_OUT)

3(CTBm1_OA0_OUT) 3(CTBm1_OA1_OUT)

3(CTBm1_OA1_INN) 3(CTBm1_OA1_INP)

Document Number: 002-09714 Rev. ** Page 9 of 40

PRELIMINARY

CYBLE-214009-00

Power Supply Connections and Recommended External Components

Three Ferrite Bead Option

Single Ferrite Bead Option

Power Connections

The CYBLE-214009-00 contains three power supply connections, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respectively. VDDR supplies power for the device radio.

VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Ta b l e 1 0 . The maximum power supply ripple for both power connections on the module is 100 mV, as shown in

Ta bl e 8.

The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used.

Connection Options

Two connection options are available for any application:

1. Single supply: Connect VDD, VDDA, and VDDR to the same supply.

2. Independent supply: Power VDD, VDDA, and VDDR separately.

Figure 5. Recommended Host Schematic Options for a Single Supply Option

External Component Recommendation

In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection.

Figure 5 details the recommended host schematic options for a

single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-214009-00.

Figure 6 details the recommended host schematic for an

independent supply scenario.

The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).

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PRELIMINARY

CYBLE-214009-00

Figure 6. Recommended Host Schematic for an Independent Supply Option

Document Number: 002-09714 Rev. ** Page 11 of 40

PRELIMINARY

CYBLE-214009-00

The CYBLE-214009-00 schematic is shown in Figure 7.

Figure 7. CYBLE-214009-00 Schematic Diagram

Document Number: 002-09714 Rev. ** Page 12 of 40

PRELIMINARY

CYBLE-214009-00

Critical Components List

Ta bl e 6 details the critical components used in the CYBLE-214009-00 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE Crystal Y1 24.000 MHz, 10PF Crystal Y2 32.768 kHz, 12.5PF

Antenna Design

Ta bl e 7 details antenna used on the CYBLE-214009-00 module. The Cypress module performance improves many of these charac-

teristics. For more information, see Table 9.

Table 7. Trace Antenna Specifications

Item Description

Frequency Range 2400 – 2500 MHz Peak Gain 0.5 dBi typical Average Gain -0.5 dBi typical Return Loss 10 dB minimum

Document Number: 002-09714 Rev. ** Page 13 of 40

PRELIMINARY

CYBLE-214009-00

Electrical Specification

Ta bl e 8 details the absolute maximum electrical characteristics for the Cypress BLE module.

Table 8. CYBLE-214009-00 Absolute Maximum Ratings

Parameter Description Min Ty p Max Units Details/Conditions

DDD_ABS

CCD_ABS

DDD_RIPPLE

GPIO_ABS

GPIO_injection

VDD, V = V

SSA

Direct digital core voltage input relative to V

Maximum power supply ripple for VDD, V V

DDR

GPIO voltage –0.5 – VDD +0.5 V Absolute maximum Maximum current per GPIO –25 – 25 mA Absolute maximum GPIO injection current: Maximum for VIH > VDD

and minimum for V

LU Pin current for latch up –200 200 mA –

Ta bl e 9 details the RF characteristics for the Cypress BLE module.

Table 9. CYBLE-214009-00 RF Performance Characteristics

Parameter Description Min Ty p Max Units Details/Conditions

RFO RF output power on ANT –18 0 3 dBm

F G G

Avg

RF receive sensitivity on ANT – –91 – dBm

Module frequency range 2400 – 2480 MHz – Peak gain – 0.5 – dBi – Average gain – –0.5 – dBi –

RL Return loss – –10 – dB –

or V

DDA

)

DDR

input voltage

supply relative to VSS (V

DDA

< V

SSD

and

–0.5 – 6 V Absolute maximum

–0.5 – 1.95 V Absolute maximum

3.0V supply

– – 100 mV

Ripple frequency of 100 kHz to 750 kHz

–0.5 – 0.5 mA

Absolute maximum current injected per pin

Configurable via register settings

Guaranteed by design simulation; High Gain Mode

Ta bl e 10 through Table 50 list the module level electrical characteristics for the CYBLE-214009-00. All specifications are valid for –40

°C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

Table 10. CYBLE-214009-00 DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

DD1

DD2

DDR1

DDR2

Active Mode, V

DD3

DD4

DD5

DD6

DD7

Power supply input voltage (V

DD = VDDA = VDDR

Power supply input voltage unregulated (V V

DDA = VDDR

)

) 1.71 – 5.5 V With regulator enabled

DD =

1.71 1.8 1.89 V

Internally unregulated

supply Radio supply voltage (radio on) 1.9 – 5.5 V – Radio supply voltage (radio off) 1.71 – 5.5 V –

= 1.71 V to 5.5 V

Execute from flash; CPU at 3 MHz – 1.7 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 6 MHz – 2.5 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 12 MHz – 4 – mA

T = 25 °C,

= 3.3 V

Document Number: 002-09714 Rev. ** Page 14 of 40

PRELIMINARY

CYBLE-214009-00

Table 10. CYBLE-214009-00 DC Specifications (continued)

Parameter Description Min Typ Max Units Details/Conditions

DD8

DD9

DD10

DD11

DD12

Sleep Mode, V

DD13

Sleep Mode, V

DD14

Deep-Sleep Mode, V

DD15

DD16

DD17

DD18

Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 24 MHz – 7.1 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 48 MHz – 13.4 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °C

= 1.71 to 5.5 V

IMO on – – – mA

and V

= 1.9 to 5.5 V

DDR

ECO on – – – mA

= 1.71 to 3.6 V

WDT with WCO on – 1.3 – µA

T = 25 °C, VDD = 3.3 V,

SYSCLK = 3 MHz

T = 25 °C, V

SYSCLK = 3 MHz

= 3.3 V,

T = 25 °C,

VDD = 3.3 V WDT with WCO on – – – µA T = –40 °C to 85 °C

WDT with WCO on – – – µA

T = 25 °C,

= 5 V

WDT with WCO on – – – µA T = –40 °C to 85 °C

Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)

DD19

DD20

WDT with WCO on – – – µA T = 25 °C WDT with WCO on – – – µA T = –40 °C to 85 °C

Hibernate Mode, VDD = 1.71 to 3.6 V

DD27

DD28

GPIO and reset active – 150 – nA

GPIO and reset active – – – nA T = –40 °C to 85 °C

Hibernate Mode, V

DD29

DD30

Stop Mode, V

DD33

DD34

DD35

DD36

Stop Mode, V

DD37

DD38

DD39

DD40

GPIO and reset active – – – nA

GPIO and reset active – – – nA T = –40 °C to 85 °C

= 1.71 to 3.6 V

Stop-mode current (VDD)–20–nA

Stop-mode current (V

Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C

Stop-mode current (V

= 3.6 to 5.5 V

Stop-mode current (VDD)–––nA

Stop-mode current (V

Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C Stop-mode current (V

= 3.6 to 5.5 V

)–40–- nA

DDR

)–––nA

DDR

)–––nA

DDR

) – – – nA T = –40 °C to 85 °C

DDR

T = 25 °C,

VDD = 3.3 V

T = 25 °C,

= 5 V

T = 25 °C,

= 3.3 V

T = 25 °C,

= 3.3 V

DDR

T = –40 °C to 85 °C,

= 1.9 V to 3.6 V

DDR

T = 25 °C,

= 5 V

T = 25 °C,

= 5 V

DDR

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CYBLE-214009-00

Table 11. AC Specifications

Note

4. V

must not exceed VDD + 0.2 V.

Parameter Description Min Typ Max Units Details/Conditions

CPU

SLEEP

DEEPSLEEP

HIBERNATE

STOP

CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 V Wakeup from Sleep mode – 0 – µs Guaranteed by characterization

Wakeup from Deep-Sleep mode – – 25 µs

24-MHz IMO. Guaranteed by

characterization Wakeup from Hibernate mode – – 800 µs Guaranteed by characterization Wakeup from Stop mode – – 2 ms XRES wakeup

GPIO

Table 12. GPIO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

[4]

PULLUP

PULLDOWN

IL_CTBM

HYSTTL

HYSCMOS

DIODE

TOT_GPIO

Input voltage HIGH threshold 0.7 × V LVTTL input, V LVTTL input, V

< 2.7 V 0.7 × V

≥ 2.7 V 2.0 – – V –

Input voltage LOW threshold – – 0.3 × V LVTTL input, V LVTTL input, V Output voltage HIGH level V Output voltage HIGH level V

< 2.7 V – – 0.3× V

≥ 2.7 V – – 0.8 V –

–0.6 – – V IOH = 4 mA at 3.3-V VDD

–0.5 – – V IOH = 1 mA at 1.8-V V

Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V V Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V V Output voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V V Pull-up resistor 3.5 5.6 8.5 kΩ – Pull-down resistor 3.5 5.6 8.5 kΩ – Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V Input leakage on CTBm input pins – – 4 nA – Input capacitance – – 7 pF – Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V Input hysteresis CMOS 0.05 × V Current through protection diode to

DD/VSS

Maximum total source or sink chip current

– – 100 µA –

– – 200 mA –

– – V CMOS input

– – V –

VCMOS input

V–

– – 1 –

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CYBLE-214009-00

Table 13. GPIO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

RISEF

FALLF

RISES

FALLS

GPIOUT1

GPIOUT2

GPIOUT3

GPIOUT4

GPIOIN

Rise time in Fast-Strong mode 2 – 12 ns 3.3-V V Fall time in Fast-Strong mode 2 – 12 ns 3.3-V V Rise time in Slow-Strong mode 10 – 60 ns 3.3-V V Fall time in Slow-Strong mode 10 – 60 ns 3.3-V V GPIO Fout; 3.3 V ≤ V

Fast-Strong mode GPIO Fout; 1.7 V≤ V

Fast-Strong mode GPIO Fout; 3.3 V ≤ V

Slow-Strong mode GPIO Fout; 1.7 V ≤ V

Slow-Strong mode GPIO input operating frequency

1.71 V ≤ V

≤ 5.5 V

≤ 3.3 V

≤ 5.5 V

≤ 3.3 V

––33MHz

– – 16.7 MHz

–– 7MHz

––3.5MHz

90/10%, 25 pF load, 60/40 duty cycle

– – 48 MHz 90/10% V

DDD

, C , C , C , C

LOAD

= 25 pF = 25 pF = 25 pF = 25 pF

XRES

Table 14. XRES DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

PULLUP

HYSXRES

DIODE

Input voltage HIGH threshold 0.7 × V Input voltage LOW threshold – – 0.3 × V

– – V CMOS input

DDD

V CMOS input

DDD

Pull-up resistor 3.5 5.6 8.5 kΩ – Input capacitance – 3 – pF – Input voltage hysteresis – 100 – mV – Current through protection diode to

DD/VSS

– – 100 µA –

Table 15. XRES AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

RESETWIDTH

Reset pulse width 1 – – µs –

Analog Peripherals

Opamp

Table 16. Opamp Specifications

Parameter Description Min Typ Max Units

(Opamp Block Current. VDD = 1.8 V. No Load)

DD_HI

DD_MED

DD_LOW

GBW (Load = 20 pF, 0.1 mA. V

Power = high – 1000 1300 µA Power = medium – 500 – µA Power = low – 250 350 µA

= 2.7 V)

DDA

GBW_HI Power = high 6 – – MHz GBW_MED Power = medium 4 – – MHz GBW_LO Power = low – 1 – MHz

OUT_MAX (VDDA ≥

2.7 V, 500 mV from Rail)

Document Number: 002-09714 Rev. ** Page 17 of 40

Details/

Conditions

PRELIMINARY

CYBLE-214009-00

Table 16. Opamp Specifications (continued)

Parameter Description Min Typ Max Units

OUT_MAX_HI

OUT_MAX_MID

OUT_MAX_LO

OUT (VDDA

OUT_MAX_HI

OUT_MAX_MID

OUT_MAX_LO

OUT (VDDA

OUT_1

OUT_2

OUT_3

OUT_4

OS_TR

OS_DR_TR

= 1.71 V, 500 mV from Rail)

Power = high 10 – – mA Power = medium 10 – – mA Power = low – 5 – mA

Power = high 4 – – mA Power = medium 4 – – mA Power = low – 2 – mA Charge pump on, V Charge pump on, V

≥ 2.7 V –0.05 – V

DDA

≥ 2.7 V –0.05 – V

DDA

– 0.2 V

DDA

– 0.2 V

DDA

≥ 2.7 V)

Power = high, I Power = high, I Power = medium, I Power = low, I

=10 mA 0.5 – V

LOAD

=1 mA 0.2 – V

LOAD

=1 mA 0.2 – V

LOAD

=0.1 mA 0.2 – V

LOAD

– 0.5 V

DDA

– 0.2 V

DDA

– 0.2 V

DDA

– 0.2 V

DDA

Offset voltage, trimmed 1 ±0.5 1 mV High mode Offset voltage, trimmed – ±1 – mV Medium mode Offset voltage, trimmed – ±2 – mV Low mode Offset voltage drift, trimmed –10 ±3 10 µV/C High mode Offset voltage drift, trimmed – ±10 – µV/C Medium mode Offset voltage drift, trimmed – ±10 – µV/C Low mode

CMRR DC 65 70 – dB V

High-power mode

PSRR At 1 kHz, 100-mV ripple 70 85 – dB V

Noise

LOAD

Slew_rate Cload = 50 pF, Power = High,

T_op_wake From disable to enable, no external RC

Input referred, 1 Hz–1 GHz, power = high – 94 – µVrms Input referred, 1 kHz, power = high – 72 – nV/rtHz Input referred, 10 kHz, power = high – 28 – nV/rtHz Input referred, 100 kHz, power = high – 15 – nV/rtHz Stable up to maximum load. Performance

––125 pF

specs at 50 pF

6 – – V/µsec

≥ 2.7 V

DDA

– 300 – µsec

dominating

Comp_mode (Comparator Mode; 50-mV Drive, T

T T T

PD1

PD2

PD3

Response time; power = high – 150 – nsec Response time; power = medium – 400 – nsec Response time; power = low – 2000 – nsec

RISE

= T

FAL L

(Approx.)

Vhyst_op Hysteresis – 10 – mV

Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for V

DDA

> 2.5 V)

GBW_DS Gain bandwidth product – 50 – kHz IDD_DS Current – 15 – µA Vos_DS Offset voltage – 5 – mV

Details/

Conditions

= 3.6 V,

DDD

= 3.6 V

DDD

Document Number: 002-09714 Rev. ** Page 18 of 40

PRELIMINARY

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Table 16. Opamp Specifications (continued)

Parameter Description Min Typ Max Units

Vos_dr_DS Offset voltage drift – 20 – µV/°C Vout_DS Output voltage 0.2 – V

–0.2 V

Vcm_DS Common mode voltage 0.2 – VDD–1.8 V

Table 17. Comparator DC Specifications

Parameter Description Min Ty p Max Units

OFFSET1

OFFSET2

OFFSET3

HYST

ICM1

ICM2

ICM3

Input offset voltage, Factory trim – – ±10 mV Input offset voltage, Custom trim – – ±6 mV Input offset voltage, ultra-low-power mode – ±12 – mV Hysteresis when enabled – 10 35 mV Input common mode voltage in normal mode 0 – V Input common mode voltage in low-power

0– V

mode Input common mode voltage in ultra

0–V

low-power mode

–0.1 V Modes 1 and 2

DDD

–1.15

CMRR Common mode rejection ratio 50 – – dB V CMRR Common mode rejection ratio 42 – – dB V I

CMP1

CMP2

CMP3

CMP

Block current, normal mode – – 400 µA Block current, low-power mode – – 100 µA Block current in ultra-low-power mode – 6 – µA DC input impedance of comparator 35 – – MΩ

Details/

Conditions

Details/

Conditions

≥ 2.7 V

DDD

≤ 2.7 V

DDD

Table 18. Comparator AC Specifications

Parameter Description Min Ty p Max Units

RESP1

RESP2

RESP3

Response time, normal mode, 50-mV overdrive

Response time, low-power mode, 50-mV overdrive

Response time, ultra-low-power mode, 50-mV overdrive

–38– ns50-mV overdrive

–70– ns50-mV overdrive

– 2.3 – µs 200-mV overdrive

Details/

Conditions

Temperature Sensor

Table 19. Temperature Sensor Specifications

Parameter Description Min Typ Max Units Details/Conditions

SENSACC

Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °C

SAR ADC

Table 20. SAR ADC DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

A_RES Resolution – – 12 bits

Document Number: 002-09714 Rev. ** Page 19 of 40

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Table 20. SAR ADC DC Specifications

A_CHNIS_S Number of channels - single-ended – – 8 8 full-speed A-CHNKS_D Number of channels - differential – – 4 Diff inputs use

neighboring I/O A-MONO Monotonicity – – – Yes A_GAINERR Gain error – – ±0.1 % With external

reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V

REF

A_ISAR Current consumption – – 1 mA A_VINS Input voltage range - single-ended V A_VIND Input voltage range - differential V

–V – V

DDA

V A_INRES Input resistance – – 2.2 kΩ A_INCAP Input capacitance – – 10 pF VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg

(1.024 V)

Table 21. SAR ADC AC Specifications

Parameter Description Min Typ Max Units

Details/

Conditions

A_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V

reference A_CMRR Common-mode rejection ratio 66 – – dB A_SAMP Sample rate – – 1 Msps 806 Ksps for More Part

Numbers devices Fsarintref SAR operating speed without external ref.

– – 100 Ksps 12-bit resolution

bypass

A_SNR Signal-to-noise ratio (SNR) 65 – – dB F

= 10 kHz

A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz A_INL Integral nonlinearity. V

1 Msps

A_INL Integral nonlinearity. V

1 Msps

A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,

500 Ksps

A_dnl Differential nonlinearity. VDD = 1.71 V to

5.5 V, 1 Msps

A_DNL Differential nonlinearity. VDD = 1.71 V to

3.6 V, 1 Msps

A_DNL Differential nonlinearity. VDD = 1.71 V to

5.5 V, 500 Ksps

= 1.71 V to 5.5 V,

= 1 .71 V to 3.6 V,

DDD

–1.7 – 2 LSB V

–1.5 – 1.7 LSB V

–1 – 2.2 LSB V

–1 – 2 LSB V

–1 – 2.2 LSB V

= 1 V to V

REF

= 1.71 V to V

REF

= 1 V to V

REF

= 1 V to V

REF

= 1.71 V to V

REF

= 1 V to V

REF

A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz

CSD

CSD Block Specifications

Parameter Description Min Ty p Max Units

CSD

Voltage range of operation 1.71 – 5.5 V

Details/

Conditions

Document Number: 002-09714 Rev. ** Page 20 of 40

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CSD Block Specifications (continued)

Parameter Description Min Ty p Max Units

Details/

Conditions

IDAC1 DNL for 8-bit resolution –1 – 1 LSB IDAC1 INL for 8-bit resolution –3 – 3 LSB IDAC2 DNL for 7-bit resolution –1 – 1 LSB IDAC2 INL for 7-bit resolution –3 – 3 LSB SNR Ratio of counts of finger to noise 5 – – Ratio

Capacitance range of

9 pF to 35 pF, 0.1-pF

sensitivity. Radio is not

operating during the

scan

DAC1_CRT1

Output current of IDAC1 (8 bits) in High

–612 – µA

range

DAC1_CRT2

Output current of IDAC1 (8 bits) in Low

–306 – µA

range

DAC2_CRT1

Output current of IDAC2 (7 bits) in High

–305 – µA

range

DAC2_CRT2

Output current of IDAC2 (7 bits) in Low

–153 – µA

range

Digital Peripherals

Timer

Table 22. Timer DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

TIM1

TIM2

TIM3

Block current consumption at 3 MHz – – 42 µA 16-bit timer Block current consumption at 12 MHz – – 130 µA 16-bit timer Block current consumption at 48 MHz – – 535 µA 16-bit timer

Table 23. Timer AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

TIMFREQ

CAPWINT

CAPWEXT

TIMRES

TENWIDINT

TENWIDEXT

TIMRESWINT

TIMRESEXT

Operating frequency F

CLK

Capture pulse width (internal) 2 × T Capture pulse width (external) 2 × T Timer resolution T

CLK

Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns ––ns

Counter

Table 24. Counter DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

CTR1

CTR2

CTR3

Block current consumption at 3 MHz – – 42

µA

16-bit counter Block current consumption at 12 MHz – – 130 µA 16-bit counter Block current consumption at 48 MHz – – 535 µA 16-bit counter

Document Number: 002-09714 Rev. ** Page 21 of 40

PRELIMINARY

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Table 25. Counter AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

CTRFREQ

CTRPWINT

CTRPWEXT

CTRES

CENWIDINT

CENWIDEXT

CTRRESWINT

CTRRESWEXT

Operating frequency F

CLK

Capture pulse width (internal) 2 × T Capture pulse width (external) 2 × T Counter Resolution T

CLK

Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns –– ns

Pulse Width Modulation (PWM)

Table 26. PWM DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

PWM1

PWM2

PWM3

Block current consumption at 3 MHz – – 42 µA 16-bit PWM Block current consumption at 12 MHz – – 130 µA 16-bit PWM Block current consumption at 48 MHz – – 535 µA 16-bit PWM

Table 27. PWM AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

PWMFREQ

PWMPWINT

PWMEXT

PWMKILLINT

PWMKILLEXT

PWMEINT

PWMENEXT

PWMRESWINT

PWMRESWEXT

Operating frequency F

CLK

Pulse width (internal) 2 × T Pulse width (external) 2 × T Kill pulse width (internal) 2 × T Kill pulse width (external) 2 × T Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns ––ns ––ns

LCD Direct Drive

Table 28. LCD Direct Drive DC Specifications

Spec ID Parameter Description Min Ty p Max Units Details/Conditions

SID228 I

LCDLOW

SID229 C

SID230 LCD SID231 I

SID232 I

LCDOP1

LCDOP2

LCDCAP

OFFSET

Operating current in low-power mode – 17.5 – µA 16 × 4 small segment

display at 50 Hz

LCD capacitance per segment/common

– 500 5000 pF

driver Long-term segment offset – 20 – mV

LCD system operating current V

= 5 V

BIAS

LCD system operating current V

= 3.3 V

BIAS

– 2 – mA 32 × 4 segments.

50 Hz at 25 °C

– 2 – mA 32 × 4 segments

50 Hz at 25 °C

Table 29. LCD Direct Drive AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID233 F

LCD

LCD frame rate 10 50 150 Hz

Document Number: 002-09714 Rev. ** Page 22 of 40

PRELIMINARY

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Serial Communication

Table 30. Fixed I2C DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

I2C1

I2C2

I2C3

I2C4

Table 31. Fixed I

Block current consumption at 100 kHz – – Block current consumption at 400 kHz – – Block current consumption at 1 Mbps – – I2C enabled in Deep-Sleep mode – –

C AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

I2C1

Bit rate – – 400 kHz

Table 32. Fixed UART DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

UART1

UART2

Block current consumption at 100 kbps – – 55 µA – Block current consumption at 1000 kbps – – 312 µA –

Table 33. Fixed UART AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

UART

Bit rate – – 1 Mbps –

50 155 390

1.4

µA – µA – µA – µA –

Table 34. Fixed SPI DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

SPI1

SPI2

SPI3

Block current consumption at 1 Mbps – – 360 µA – Block current consumption at 4 Mbps – – 560 µA – Block current consumption at 8 Mbps – – 600 µA –

Table 35. Fixed SPI AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

SPI

SPI operating frequency (master; 6x over sampling) – – 8 MHz –

Table 36. Fixed SPI Master Mode AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

DMO

DSI

HMO

MOSI valid after SCLK driving edge – – 18 ns – MISO valid before SCLK capturing edge

Full clock, late MISO sampling used

20 – – ns Full clock, late MISO sampling

Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge

Table 37. Fixed SPI Slave Mode AC Specifications

Parameter Description Min Ty p Max Units

DMI

DSO

DSO_ext

HSO

SSELSCK

MOSI valid before SCLK capturing edge 40 – – ns MISO valid after SCLK driving edge – – 42 + 3 × T MISO Valid after SCLK driving edge in

external clock mode. V

< 3.0 V

– – 50 ns

CPU

Previous MISO data hold time 0 – – ns SSEL valid to first SCK valid edge 100 – – ns

Document Number: 002-09714 Rev. ** Page 23 of 40

PRELIMINARY

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Memory

Note

5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

Table 38. Flash DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

WS48

WS32

WS16

Erase and program voltage 1.71 – 5.5 V – Number of Wait states at 32–48 MHz 2 – – CPU execution from flash Number of Wait states at 16–32 MHz 1 – – CPU execution from flash Number of Wait states for 0–16 MHz 0 – – CPU execution from flash

Table 39. Flash AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ROWWRITE

ROWERASE

ROWPROGRAM

BULKERASE

DEVPROG

END

RET

RET2

[5]

Row (block) write time (erase and program) – – 20 ms Row (block) = 256 bytes

[5]

Row erase time – – 13 ms –

[5]

Row program time after erase – – 7 ms –

[5]

Bulk erase time (256 KB) – – 35 ms –

[5]

Total device program time – – 25 seconds – Flash endurance 100 K – – cycles – Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years – Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years –

System Resources

Power-on-Reset (POR)

Table 40. POR DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

RISEIPOR

FALLIPOR

IPORHYST

Rising trip voltage 0.80 – 1.45 V – Falling trip voltage 0.75 – 1.40 V – Hysteresis 15 – 200 mV –

Table 41. POR AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

PPOR_TR

Precision power-on reset (PPOR) response time in Active and Sleep modes

––1µs –

Table 42. Brown-Out Detect

Parameter Description Min Ty p Max Units Details/Conditions

FALLPPOR

FALLDPSLP

BOD trip voltage in Active and Sleep modes 1.64 – – V – BOD trip voltage in Deep Sleep 1.4 – – V –

Table 43. Hibernate Reset

Parameter Description Min Typ Max Units Details/Conditions

HBRTRIP

Document Number: 002-09714 Rev. ** Page 24 of 40

BOD trip voltage in Hibernate 1.1 – – V –

PRELIMINARY

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Voltage Monitors (LVD)

Table 44. Voltage Monitor DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

V V V V V V V V V V V V V V V V

LVI 1

LVI 2

LVI 3

LVI 4

LVI 5

LVI 6

LVI 7

LVI 8

LVI 9

LVI 10

LVI 11

LVI 12

LVI 13

LVI 14

LVI 15

LVI 16

LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V – LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V – LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V – LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V – LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V – LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V – LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V – LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V – LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V – LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V – LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V – LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V – LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V – LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V – LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V – LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –

LVI_IDD Block current – – 100 µA –

Table 45. Voltage Monitor AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

MONTRIP

Voltage monitor trip time – – 1 µs –

SWD Interface

Table 46. SWD Interface Specifications

Parameter Description Min Typ Max Units Details/Conditions

F_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency F_SWDCLK2 1.71 V ≤ V

≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency

T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns – T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns – T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns – T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –

Document Number: 002-09714 Rev. ** Page 25 of 40

PRELIMINARY

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Internal Main Oscillator

Table 47. IMO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IMO1

IMO2

IMO3

IMO4

IMO5

IMO operating current at 48 MHz – – 1000 µA – IMO operating current at 24 MHz – – 325 µA – IMO operating current at 12 MHz – – 225 µA – IMO operating current at 6 MHz – – 180 µA – IMO operating current at 3 MHz – – 150 µA –

Table 48. IMO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IMOTOL3

Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration IMO startup time – 12 – µs –

Internal Low-Speed Oscillator

Table 49. ILO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ILO2

ILO operating current at 32 kHz – 0.3 1.05 µA –

Table 50. ILO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

STARTILO1

ILOTRIM1

ILO startup time – – 2 ms – 32-kHz trimmed frequency 15 32 50 kHz –

Table 51. ECO Trim Value Specification

Parameter Description Value Details/Conditions

ECO

TRIM

24-MHz trim value (firmware configuration)

0x00003FFA

Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG

Table 52. UDB AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

Data Path performance

MAX-TIMER

MAX-ADDER

MAX_CRC

Max frequency of 16-bit timer in a UDB pair

Max frequency of 16-bit adder in a UDB pair

Max frequency of 16-bit CRC/PRS in a UDB pair

––48MHz

PLD Performance in UDB

MAX_PLD

Max frequency of 2-pass PLD function in a UDB pair

––48MHz

Clock to Output Performance

CLK_OUT_UDB1

CLK_OUT_UDB2

Prop. delay for clock in to data out at 25 °C, Typical

Prop. delay for clock in to data out, Worst case

–15 – ns

–25 – ns

Document Number: 002-09714 Rev. ** Page 26 of 40

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Table 53. BLE Subsystem

Parameter Description Min Typ Max Units

RF Receiver Specification

RXS, IDLE RX sensitivity with idle transmitter – –89 – dBm

RX sensitivity with idle transmitter excluding Balun loss

RXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 dBm RF-PHY Specification

RXS, HIGHGAIN RX sensitivity in high-gain mode with idle

PRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification

CI1 Cochannel interference,

CI2 Adjacent channel interference

CI3 Adjacent channel interference

CI4 Adjacent channel interference

CI5 Adjacent channel interference

CI3 Adjacent channel interference

OBB1 Out-of-band blocking,

OBB2 Out-of-band blocking,

OBB3 Out-of-band blocking,

OBB4 Out-of-band blocking,

IMD Intermodulation performance

RXSE1 Receiver spurious emission

transmitter

Wanted signal at –67 dBm and Interferer at FRX

Wanted signal at –67 dBm and Interferer at FRX ±1 MHz

Wanted signal at –67 dBm and Interferer at FRX ±2 MHz

Wanted signal at –67 dBm and Interferer at ≥FRX ±3 MHz

Wanted Signal at –67 dBm and Interferer at Image frequency (F

Wanted signal at –67 dBm and Interferer at Image frequency (F

Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz

Wanted signal at –67 dBm and Interferer at F = 2003–2399 MHz

Wanted signal at –67 dBm and Interferer at F = 2484–2997 MHz

Wanted signal a –67 dBm and Interferer at F = 3000–12750 MHz

Wanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel

30 MHz to 1.0 GHz

IMAGE

)

± 1 MHz)

– –91 – dBm Guaranteed by design

simulation

(RCV-LE/CA/01/C)

– –91 – dBm

(RCV-LE/CA/06/C)

– 9 21 dB RF-PHY Specification

(RCV-LE/CA/03/C)

– 3 15 dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –29 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –39 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –20 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –30 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

–30 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–35 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–35 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–30 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–50 – – dBm RF-PHY Specification

(RCV-LE/CA/05/C)

– – –57 dBm 100-kHz measurement

bandwidth ETSI EN300 328 V1.8.1

Details/

Conditions

Document Number: 002-09714 Rev. ** Page 27 of 40

PRELIMINARY

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Table 53. BLE Subsystem (continued)

Parameter Description Min Typ Max Units

RXSE2 Receiver spurious emission

1.0 GHz to 12.75 GHz

RF Transmitter Specifications

TXP, ACC RF power accuracy – ±1 – dB

TXP, RANGE RF power control range – 20 – dB

TXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 – dBm

TXP, MAX Output power, maximum power setting

(PA10)

TXP, MIN Output power, minimum power setting

(PA1)

F2AVG Average frequency deviation for

10101010 pattern

F1AVG Average frequency deviation for

11110 000 pa ttern

EO Eye opening = ΔF2AVG/ΔF1AVG 0.8 – – RF-PHY Specification

FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification

FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification

FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification

FTX, DR Maximum drift rate –20 – 20 kHz/

IBSE1 In-band spurious emission at 2-MHz

offset

IBSE2 In-band spurious emission at ≥3-MHz

offset

TXSE1 Transmitter spurious emissions

(average), <1.0 GHz

TXSE2 Transmitter spurious emissions

(average), >1.0 GHz

RF Current Specifications

– – –47 dBm 1-MHz measurement

–3 – dBm

– –18 – dBm

185 – – kHz RF-PHY Specification

225 250 275 kHz RF-PHY Specification

50 µs

– – –20 dBm RF-PHY Specification

– – -30 dBm RF-PHY Specification

– – -55.5 dBm FCC-15.247

– – -41.5 dBm FCC-15.247

bandwidth ETSI EN300 328 V1.8.1

(TRM-LE/CA/05/C)

(TRM-LE/CA/06/C)

(TRM-LE/CA/06/C) RF-PHY Specification

(TRM-LE/CA/06/C)

(TRM-LE/CA/03/C)

Details/

Conditions

IRX Receive current in normal mode – 18.7 – mA

IRX_RF Radio receive current in normal mode – 16.4 – mA Measured at V

IRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mA

ITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – mA

ITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – mA

ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – mA Measured at V

ITX_RF, 0dBm Radio TX current at 0 dBm excluding

Balun loss

ITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – mA

ITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – mA

Document Number: 002-09714 Rev. ** Page 28 of 40

– 14.2 – mA Guaranteed by design

simulation

DDR

PRELIMINARY

CYBLE-214009-00

Table 53. BLE Subsystem (continued)

Parameter Description Min Typ Max Units

ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – mA

ITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – mA

Iavg_1sec, 0dBm Average current at 1-second BLE

connection interval

Iavg_4sec, 0dBm Average current at 4-second BLE

connection interval

General RF Specifications

FREQ RF operating frequency 2400 – 2482 MHz

CHBW Channel spacing – 2 – MHz

DR On-air data rate – 1000 – kbps

IDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 µs

IDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 µs

RSSI Specifications

RSSI, ACC RSSI accuracy – ±5 – dB

RSSI, RES RSSI resolution – 1 – dB

– 17.1 – µA TXP: 0 dBm; ±20-ppm

– 6.1 – µA TXP: 0 dBm; ±20-ppm

Details/

Conditions

master and slave clock accuracy. For empty PDU exchange

RSSI, PER RSSI sample period – 6 – µs

Document Number: 002-09714 Rev. ** Page 29 of 40

PRELIMINARY

CYBLE-214009-00

Environmental Specifications

Note

6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.

Environmental Compliance

This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBLE-214009-00 module is certified under the following RF certification standards:

n FCC ID: WAP4008

n CE

n IC: 7922A-4008

n MIC (Japan)

n KC: MSIP-CRM-Cyp-4008

Environmental Conditions

Ta bl e 54 describes the operating and storage conditions for the Cypress BLE module.

Table 54. Environmental Conditions for CYBLE-214009-00

Description Minimum Specification Maximum Specification

Operating temperature -40 °C 85 °C Operating humidity (relative, non-condensation) 5% 85% Thermal ramp rate Storage temperature –40 °C 85 °C Storage temperature and humidity ESD: Module integrated into system

Components

[6]

– 3 °C/minute

– 85 ° C at 85%

–

15 kV Air

2.2 kV Contact

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Document Number: 002-09714 Rev. ** Page 30 of 40

PRELIMINARY

CYBLE-214009-00

Regulatory Information

FCC

FCC NOTICE: The device CYBLE-214009-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter

approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

n Reorient or relocate the receiving antenna.

n Increase the separation between the equipment and receiver.

n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

n Consult the dealer or an experienced radio/TV technician for help

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008.

In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"

ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 13. When integrated in the OEMs

product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas

in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.

The radiated output power of CYBLE-214009-00 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-214009-00 in such a manner that minimizes the potential for human contact during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-09714 Rev. ** Page 31 of 40

PRELIMINARY

CYBLE-214009-00

Industry Canada (IC) Certification

CYBLE-214009-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-4008 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antennas listed in Table 7 on page 13, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

IC NOTICE: The device CYBLE-214009-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter

approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

IC RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)

this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label

on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-4008".

European R&TTE Declaration of Conformity

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-214009-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows:

All versions of the CYBLE-214009-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: 002-09714 Rev. ** Page 32 of 40

PRELIMINARY

CYBLE-214009-00

MIC Japan

CYBLE-214009-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-214009-00 do not need additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

KC Korea

CYBLE-214009-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008

Document Number: 002-09714 Rev. ** Page 33 of 40

PRELIMINARY

CYBLE-214009-00

Ordering Information

The CYBLE-214009-00 part number and features are listed in the following table.

Features

MPN

UDB

Opamp (CTBm)

CapSense

SCB Blocks

Direct LCD Drive

12-bit SAR ADC

LP Comparators

TCPWM Blocks

PWMs (using UDBs)

Max CPU Speed (MHz)

Flash (KB)

SRAM (KB)

CYBLE-214009-00 48 256 32 4 4 3 3 1 Msps 1 4 2 4 3 25 32-SMT

Part Numbering Convention

The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.

GPIO

I2S (using UDB)

Package

For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134 U.S. Cypress Headquarter Contact Info (408) 943-2600 Cypress website address http://www.cypress.com

Document Number: 002-09714 Rev. ** Page 34 of 40

PRELIMINARY

CYBLE-214009-00

Acronyms

Table 55. Acronyms Used in this Document

Acronym Description

ABUS analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi-

ALU arithmetic logic unit AMUXBUS analog multiplexer bus API application programming interface APSR application program status register

ARM ATM automatic thump mode BLE Bluetooth Low Energy Bluetooth

SIG BW bandwidth CAN Controller Area Network, a communications

CE European Conformity CSA Canadian Standards Association CMRR common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking

DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital

DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only

EMI electromagnetic interference

tecture) high-performance bus, an ARM data transfer bus

advanced RISC machine, a CPU architecture

Bluetooth Special Interest Group

protocol

capabilities, no analog. See GPIO.

memory

Table 55. Acronyms Used in this Document (continued)

Acronym Description

EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell FCC Federal Communications Commission FET field-effect transistor FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC

pin HCI host controller interface HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment

C, or IIC Inter-Integrated Circuit, a communications

protocol IC Industry Canada IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell KC Korea Certification LCD liquid crystal display LIN Local Interconnect Network, a communications

LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic

protocol.

Document Number: 002-09714 Rev. ** Page 35 of 40

PRELIMINARY

CYBLE-214009-00

Table 55. Acronyms Used in this Document (continued)

Acronym Description

MAC multiply-accumulate MCU microcontroller unit MIC Ministry of Internal Affairs and Communications

(Japan) MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL Opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register

PSoC PSRR power supply rejection ratio PWM pulse-width modulator QDID qualification design ID RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I

Programmable System-on-Chip™

C serial clock

Table 55. Acronyms Used in this Document (continued)

Acronym Description

SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced

features. See GPIO.

SMT surface-mount technology; a method for

producing electronic circuitry in which the components are placed directly onto the surface of

PCBs SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications

protocol SR slew rate SRAM static random access memory SRES software reset STN super twisted nematic SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion TIA transimpedance amplifier TN twisted nematic TRM technical reference manual TTL transistor-transistor logic TUV Germany: Technischer Überwachungs-Verein

(Technical Inspection Association) TX transmit UART Universal Asynchronous Transmitter Receiver, a

communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to

a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal

Document Number: 002-09714 Rev. ** Page 36 of 40

PRELIMINARY

CYBLE-214009-00

Document Conventions

Units of Measure

Table 56. Units of Measure

Symbol Unit of Measure

°C degrees Celsius dB decibel dBm decibel-milliwatts fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kΩ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MΩ mega-ohm Msps megasamples per second µA microampere µF microfarad µH microhenry µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Ω ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz Vvolt

Document Number: 002-09714 Rev. ** Page 37 of 40

PRELIMINARY

CYBLE-214009-00

Errata

This section describes the errata for the CYBLE-214009-00 module. Details include errata trigger conditions, scope of impact, and available workarounds. Contact your local Cypress Sales Representative if you have questions.

Errata Summary

1. CapSense is not enabled in PSoC Creator.

n PROBLEM DEFINITION

CapSense Support for CYBLE-214009-00 is not enabled in PSoC Creator 3.3.

n PARAMETERS AFFECTED

None

n TRIGGER CONDITIONS

Applicatoins that need CapSense functionality will not be able to enable it with PSoC Creator 3.3.

n SCOPE OF IMPACT

None

n WORKAROUND

No work aruond with PSoC Creator 3.3.

n FIX STATUS

This issue will be fixed in November, 2015 on a future PSoC Creator release.

n CHANGES

None

Document Number: 002-09714 Rev. ** Page 38 of 40

PRELIMINARY

CYBLE-214009-00

Document History Page

Document Title: CYBLE-214009-00 EZ-BLETM PSoC® Module Document Number: 002-09714

Revision ECN

** DSO 10/29/2015 Preliminary datasheet for CYBLE-214009-00 module.

Orig. of

Change

Submission

Date

Description of Change

Document Number: 002-09714 Rev. ** Page 39 of 40

PRELIMINARY

CYBLE-214009-00

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

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PSoC® Solutions

psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Technical Support

cypress.com/go/support

© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-09714 Rev. ** Revised October 29, 2015 Page 40 of 40

All products and company names mentioned in this document may be the trademarks of their respective holders.

Cypress Semiconductor 4008 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Module Description

Power Consumption

Programmable Analog

Programmable Digital

Capacitive Sensing

Segment LCD Drive

Serial Communication

Timing and Pulse-Width Modulation

Up to 25 Programmable GPIOs

Contents

Overview

Module Description

Pad Connection Interface

Recommended Host PCB Layout

Power Supply Connections and Recommended External Components

Connection Options

External Component Recommendation

Critical Components List

Antenna Design

Electrical Specification

GPIO

XRES

Analog Peripherals

Digital Peripherals

Serial Communication

Memory

System Resources

Environmental Specifications

Environmental Compliance

RF Certification

Environmental Conditions

ESD and EMI Protection

Regulatory Information

Industry Canada (IC) Certification

European R&TTE Declaration of Conformity

MIC Japan

KC Korea

Ordering Information

Part Numbering Convention

Acronyms

Document Conventions

Units of Measure

Errata

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Products

PSoC® Solutions

Cypress Developer Community

Technical Support