1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interferance sources with output power of +8.0 dBm.
2. Specified as module-to-module range. Mobile phone connection range will decrease based on the PA/LNA performance of the mobile phone used.
3. The CYBLE-473142-01 is capable of higher output power than specified, but is intentionally limited to +8.0dBm due to regulatory requirements for European Standards.
The CYBLE-473142-01 is a Bluetooth Low Energy (BLE)
wireless module solution with integrated Apple HomeKit support,
including the authentication co-processor. The
CYBLE-473142-01 includes onboard crystal oscillators, passive
components, and the Cypress CYW20719 B1 silicon device.
The CYBLE-473142-01 supports a number of peripheral
functions (ADC and PWM), as well as UART serial
communication protocol. The CYBLE-473142-01 includes a
royalty-free BLE stack compatible with Bluetooth 4.2 in a 14.7 ×
20.0 × 1.40mm package.
The CYBLE-473142-01 includes an integrated PCB trace
antenna. The CYBLE-473142-01 is qulaified by Bluetooth SIG,
and includes regulatory certification approval for FCC, ISED, and
CE.
Module Description
n Module size: 14.70 mm × 20.00 mm × 2.60 mm
n Extended Range:
p Up to 400 meters bi-directional communication
p Up to 450 meters in beacon only mode
n Bluetooth LE Mesh Qualified design
n Bluetooth LE 4.2 single-mode module
p QDID: TBD
p Declaration ID: TBD
n Certified to FCC, ISED, and CE standards
n Castelated solder pad connections for ease-of-use
n 1024-KB flash memory, 512-KB SRAM memory
n Extended Industrial temperature range: –30 °C to +105 °C
n Cortex-M4F 32-bit processor operating up to 96MHz
n Watchdog timer with dedicated internal low-speed oscillator
[1]
[1,2]
n RX current consumption
p BLE silicon: 5.8 mA (MCU + radio only)
p RFX2401C: 7.5 mA (PA/LNA only)
n Cypress CYW20719 silicon low power mode support
p PDS: 70 μA with 512 KB SRAM retention
p Deep Sleep: 1 μA with 16 KB SRAM retention
p HIDOFF: 350 nA with XRES wakeup
Functional Capabilities
n Apple HomeKit compliant with on-board authentication
co-processor
n Switched-cap Sigma-Delta ADC with internal reference
n UART serial communication block (PUART)
n Up to five PWMs supported
n BLE protocol stack supporting generic access profile (GAP)
Central, Peripheral, Observer, or Broadcaster roles
Benefits
CYBLE-473142-01 is fully integrated and certified solution that
provides all necessary components required to operate BLE
communication standards.
n Proven hardware design ready to use
n Large non-volatile memory for complex application devel-
opment
n Over-the-air update capable for development or field updates
n Bluetooth SIG qualified with QDID and Declaration ID
n WICED™ Studio provides an easy-to-use integrated design
environment (IDE) to configure, develop, program, and test a
BLE application
Power Consumption
n Maximum TX output power: +8.0 dbm
n RX Receive Sensitivity: –93 dbm
n Received signal strength indicator (RSSI) with 1-dB resolution
n TX current consumption
p BLE silicon: 5.7 mA (MCU + radio only, 0 dbm)
p RFX2401C: 27 mA (PA/LNA only, module +8 dBm)
[3]
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document Number: CYBLE-473142-01 Preliminary Revised December 26, 2017
Technical Support ..................................................... 34
...... 22
Document Number: CYBLE-473142-01 Preliminary Page 2 of 34
CYBLE-473142-01
Overview
Functional Block Diagram
Figure 1 illustrates the CYBLE-473142-01 functional block diagram.
Figure 1. Functional Block Diagram
Module Description
The CYBLE-473142-01 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for
the CYBLE-473142-01 will not be made until approval is provided by the end customer for this product. The CYBLE-473142-01 will
be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension ItemSpecification
Module dimensions
Antenna location dimensions
PCB thicknessHeight (H)0.80 ± 0.10 mm
Shield heightHeight (H)1.80 mm
Maximum component heightHeight (H)0.60 mm typical
Total module thickness (bottom of module to highest component)Height (H)2.60 mm typical
See Figure 2 for the mechanical reference drawing for CYBLE-473142-01.
Length (X)14.70 ± 0.15 mm
Width (Y)20.00 ± 0.15 mm
Length (X)14.70 mm
Width (Y)4.80 mm
Document Number: CYBLE-473142-01 Preliminary Page 3 of 34
CYBLE-473142-01
Figure 2. Module Mechanical Drawing
Bottom View (Seen from Bottom)
Side View
Top View (See from Top)
Notes
4. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 6.
5. The CYBLE-473142-01 includes castellated pad connections, denoted as the circular openings at the pad location above.
Document Number: CYBLE-473142-01 Preliminary Page 4 of 34
CYBLE-473142-01
Pad Connection Interface
Castellated Solder Pad (CSP) and Solder Pad (SP) Connection (Seen from Bottom)
Optional Host PCB Keep Out Area Around Chip Antenna
As shown in the bottom view of Figure 2 on page 4, the CYBLE-473142-01 has seven main connections that are connected to the
host board via castellated solder pads (“CSP”). The CYBLE-473142-01 also includes additional solder pad connections (“SP”) used
for debug or testing on the bottom side of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions
of the CYBLE-473142-01 module.
Figure 3. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 4) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.
2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace
antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please
refer to AN96841 for module placement best practices.
3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB trace antenna
may contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layers
of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).
Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBLE-473142-01 PCB Trace Antenna
Document Number: CYBLE-473142-01 Preliminary Page 5 of 34
CYBLE-473142-01
Recommended Host PCB Layout
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Figure 5 (Dimensioned) and Figure 6 (Relative to Origin) provide the recommended host PCB layout pattern for the
CYBLE-473142-01. Pad length of 1.27 mm (0.655 mm from center of the pad on either side) shown in Figure 6 is the minimum
recommended host pad length. All dimensions are in millimeters.
Document Number: CYBLE-473142-01 Preliminary Page 6 of 34
CYBLE-473142-01
Module Connections
Ta bl e 3 details the solder pad connection definitions and available functions for each connection pad. Tab le 3 lists the solder pads on
the CYBLE-473142-01, the silicon device pin, and denotes what functions are available for each solder pad. Table 3 also lists the
primary/intended function for each solder pad for the application this module was specifically designed for.
Table 3. Solder Pad Connection Definitions
Pad Num-
ber
1VDDPower Supply Input (3.30 V)Power Supply Input
2GNDGround ConnectionGround Connection
3PWM133PWM R, G, B, or W Function
4PWM233PWM R, G, B, or W Function
5PWM333PWM R, G, B, or W Function
6PWM433PWM R, G, B, or W Function
7ADCADC Input
8PUART_TX 3(PUART_TXD)Peripheral UART TXD
The CYBLE-473142-01 contains one power supply connection, VDD.
VDD accepts a supply input of 3.30 V. Ta bl e 9 provides this specification. The maximum power supply ripple for this power connection
is 300 mV, as shown in Tab le 9 .
Considerations and Optional Components for Brown Out (BO)Conditions
Power supply design must be completed to ensure that the CYBLE-473142-01 module does not encounter a Brown Out condition,
which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to the
module during power up or reset is in the range shown below:
V
≤ VDD ≤ V
IL
Refer to Table 13 for the VIL and V
specifications.
IH
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that
this cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that an
external voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please refer
to Figure 7 for the recommended circuit design when using an external voltage detection IC.
IH
Document Number: CYBLE-473142-01 Preliminary Page 7 of 34
CYBLE-473142-01
Figure 7. Reference Circuit Block Diagram for External Voltage Detection IC
In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the
module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potential cause issues
that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition.
External Reset (XRES)
The CYBLE-473142-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This
action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,
which is an input to the CYBLE-473142-01 module (solder pad 3). The CYBLE-473142-01 module
resistor on the XRES input
During power on operation, the XRES connection to the CYBLE-473142-01 is required to be held low 50 ms after the VDD power
supply input to the module is stable. This can be accomplished in the following ways:
n The host device should connect a GPIO to the XRES of Cypress CYBLE-473142-01 module and pull XRES low until VDD is stable.
XRES is recommended to be released 50 ms after VDD is stable.
n If the XRES connection of the CYBLE-473142-01 module is not used in the application, a 0.33 uF capacitor may be connected to
the XRES solder pad of the CYBLE-473142-01 in order to delay the XRES release. The capacitor value for this recommended
implementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The
capacitor value should result in an XRES release timing of 50 ms after VDD stability.
n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.
Refer to Figure 10 on page 14 for XRES operating and timing requirements during power on events.
does not require an external pull-up
UART Connections
For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and
only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and
CTS:
n UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.
n UART CTS: Must by pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the
module.
External Component Recommendation
Power Supply Circuitry
It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned
as close as possible to the module pin connection.
If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).
Apple MFi Authentication Coprocessor Interface
The CYBLE-473142-01 comes with an integrated MFi authentication co-processor. No additoinal connections are required to be made
to the module to enable Apple HomeKit functionality. All connections required are internally routed on the module PCB.
Document Number: CYBLE-473142-01 Preliminary Page 8 of 34
CYBLE-473142-01
Figure 8 illustrates the CYBLE-473142-01 schematic.
Figure 8. CYBLE-473142-01 Schematic Diagram
Document Number: CYBLE-473142-01 Preliminary Page 9 of 34
CYBLE-473142-01
Critical Components List
Ta bl e 4 details the critical components used in the CYBLE-473142-01 module.
Ta bl e 5 details the PCB trace antenna used in the CYBLE-473142-01 module.
Table 5. Trace Antenna Specifications
ItemDescription
Frequency Range2402 – 2480 MHz
Peak Gain–0.5 dBi maximum
Document Number: CYBLE-473142-01 Preliminary Page 10 of 34
CYBLE-473142-01
Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into
baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it
independently handles host controller interface (HCI) event types, and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the
TX/RX data before sending over the air:
n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
Bluetooth Low Energy
The CYBLE-473142-01 supports single-mode Bluetooth LE operation. The CYBLE-473142-01 supports all Bluetooth 4.2 and legacy
LE features, with the following benefits:
n LE data packet length extension
n LE secure connections
n Link layer privacy
n Enables Bluetooth Smart sensors to access the Internet directly via IPv6/6LoWPAN
Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth® Link
Controller.
n Major states:
p Standby
p Connection
Document Number: CYBLE-473142-01 Preliminary Page 11 of 34
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