Cypress Semiconductor 3063 User Manual

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

EZ-BT™ Module

CYBT-273063-02, CYBT-263064-02, CYBT-263065-02, EZ-BT™ Module

General Description

The CYBT-2X30XX-02 is a dual-mode Bluetooth BR/EDR and Low Energy (BLE) wireless module solution. The CYBT-2X30XX-02 includes an onboard crystal oscillator, passive components, PA/LNA, and the Cypress CYW20819 silicon device.

The CYBT-2X30XX-02 supports a number of peripheral functions (ADC, PWM), as well as multiple serial communication protocols (UART, SPI, I includes a royalty-free stack compatible with Bluetooth 5.0 in a

12.0 × 16.61 × 1.70 mm module form-factor. The CYBT-2X30XX-02 is offered in three certified versions

CYBT-273063-02, CYBT-263064-02, and CYBT-263065-02. The CYBT-273063-02 includes an integrated trace antenna. The CYBT-263064-02 supports an external antenna via a u-FL connector. The CYBT-263065-02 supports an external antenna through a RF solder pad output. CYBT-2X30XX-02 includes onboard external power/low noise amplifier, qualified by Bluetooth SIG, and includes regulatory certification approval for FCC, ISED, MIC, and CE.

Module Description

■ Module size: 12.5 mm × 19 mm × 1.95 mm

■ Complies with Bluetooth Core Specification version 5.0 and

includes support for BR, EDR 2/3 Mbps, eSCO, BLE, LE 2 Mbps, as well as Bluetooth Mesh.

❐ QDID: TBD ❐ Declaration ID: TBD

■ Certified to FCC, ISED, MIC, and CE standards

■ 256-KB on-chip Flash, 176-KB on-chip RAM

■ Industrial temperature range: –30 °C to +85 °C

■ Integrated Arm

floating point unit (FPU)

RF Characteristics

■ Maximum TX output power: +17.0 dBm

■ BLE RX Receive Sensitivity: –95.0 dBm

C, I2S/PCM). The CYBT-2X30XX-02

Cortex®-M4 microprocessor core with

■ Cypress CYW20819 silicon low power mode support

❐ PDS: 16.5 μA with 176 KB RAM retention ❐ ePDS: 8.7 μA ❐ HIDOFF (wake on external or timed interrupt): 1.75 μA

Functional Capabilities

■ Up to 20 GPIOs

■ I

C, I2S, UART, and PCM interfaces

■ Two Quad-SPI interfaces

■ Auxiliary ADC with up to 15 analog channels

■ Programmable key scan 20 × 8 matrix

■ General-purpose timers and six PWMs

■ Real-time clock (RTC) and watchdog timers (WDT)

■ Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR)

Support

■ BLE protocol stack supporting generic access profile (GAP)

Central, Peripheral, Observer, or Broadcaster roles

Benefits

CYBT-2X30XX-02 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth communication standards.

■ Proven hardware design ready to use

■ Ultra-flexible supermux I/O design allows maximum flexibility

for GPIO function assignment

■ Over-the-air update capable for development or field updates

■ Bluetooth SIG qualified.

■ ModusToolbox™ provides an easy-to-use integrated design

environment (IDE) to configure, develop, program, and test your Bluetooth application

Power Consumption

■ TX current consumption ❐ BLE silicon: 5.8 mA (radio only, 4 dBm)

❐ 8TR8201: 8 mA Typ (PA/LNA only)

■ RX current consumption ❐ Bluetooth silicon: 5.9 mA (radio only)

❐ 8TR8201: 75 mA Typ (PA/LNA only, +20 dBm Pout) ❐ 8TR8201: ?? mA Typ (PA/LNA only, +7.5 dBm Pout)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-29354 Rev. ** Revised December 26, 2019

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.

References

■ Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap

■ Development Kits: ❐ CYBT-273063-EVAL, CYBT-273063-02 Evaluation Board ❐ CYBT-263064-EVAL, CYBT-263064-02 Evaluation Board

❐ CYBT-213043-MESH, Mesh Evaluation Kit ❐ CYW920819Q40EVB-01, Evaluation Kit for CYW20819

silicon device

■ Test and Debug Tools: ❐ CYSmart, Bluetooth ❐ CYSmart Mobile, Bluetooth

LE Test and Debug Tool (Windows)

LE Test and Debug Tool

(Android/iOS Mobile App)

■ Knowledge Base Article ❐ KBA97095 - EZ-BLE™ Module Placement

❐ RF Regulatory Certifications for CYBT-2X30XX-02 EZ-BT

WICED Modules (TBD)

❐ KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐ KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules ❐ KBA223428 - Programming an EZ-BT WICED Module ❐ KBA225450 - Putting 2073x, 2070x, and 20719 Based De-

vices or Modules in HCI Mode

Development Environments

ModusToolbox Integrated Development Environment (IDE)

ModusToolbox simplifies development for IoT designers. It delivers easy-to-use tools and a familiar microcontroller (MCU) integrated

development environment (IDE) for Windows wireless connectivity libraries, power analysis, application-specific configurators for Bluetooth well as other peripherals.

In addition, code examples, documentation, technical support and community forums are available to help your IoT development process along. These tools and features enable an IoT designer to develop innovative IoT applications efficiently and with ease.

, macOS®, and Linux®. It provides a sophisticated environment for system setup,

Low Energy (BLE), CapSense®, as

Technical Support

■ Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share, and engage with both Cypress experts and other embedded engineers around the world.

■ Frequently Asked Questions (FAQs): Learn more about our Bluetooth ecosystem.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-29354 Rev. ** Page 2 of 45

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Overview ............................................................................4

Functional Block Diagram ...........................................4

Module Description ......................................................4

Pad Connection Interface ................................................6

Recommended Host PCB Layout ...................................7

Module Connections ........................................................9

Connections and Optional External Components ....... 11

Power Connections (VDD) ........................................11

External Reset (XRES) ..............................................11

HCI UART Connections ............................................11

External Component Recommendation .................... 11

Antenna Matching Network Requirements ................ 11

Critical Components List ............................................... 13

Antenna Design ..............................................................13

Qualified Antenna for CYBT-263064-02 and

CYBT-263065-02 ............................................................. 13

Bluetooth Baseband Core ............................................. 14

Power Management Unit ................................................15

Integrated Radio Transceiver ........................................16

Transmitter Path ........................................................16

Receiver Path ............................................................16

Local Oscillator ..........................................................16

Microcontroller Unit .......................................................17

External Reset ...........................................................17

32-kHz Crystal Oscillator ...........................................17

Power Modes ............................................................18

Firmware ...................................................................18

Watchdog ..................................................................18

Lockout Functionality .................................................18

True Random Number Generator .............................18

Peripherals and Communication Interfaces ................ 19

I2C .............................................................................19

HCI UART Interface ..................................................19

Peripheral UART Interface ........................................19

Serial Peripheral Interface .........................................19

ADC Port ................................................................... 20

GPIO Port ..................................................................20

PWM .......................................................................... 21

PDM Microphone .......................................................21

I2S Interface ..............................................................22

PCM Interface ...........................................................22

Electrical Characteristics ...............................................23

Current Consumption ................................................24

Silicon Core Buck Regulator ...................................

Digital LDO ................................................................25

RF LDO .....................................................................25

Digital I/O Characteristics ..........................................26

ADC Characteristics .................................................. 26

Chipset RF Specifications .............................................28

Timing and AC Characteristics ..................................... 30

UART Timing ............................................................. 30

SPI Timing ................................................................. 31

I2C Compatible Interface Timing ...............................33

I2S Interface Timing ..................................................34

Environmental Specifications .......................................36

Environmental Compliance .......................................36

RF Certification ..........................................................36

Safety Certification ....................................................36

Environmental Conditions .........................................36

ESD and EMI Protection ........................................... 36

Regulatory Information .................................................. 37

FCC ...........................................................................37

ISED ..........................................................................38

European Declaration of Conformity ......................... 39

MIC Japan .................................................................39

Packaging ........................................................................ 40

Ordering Information ......................................................42

Acronyms ........................................................................43

Document Conventions .................................................43

Units of Measure ....................................................... 43

Document History Page ................................................. 44

Sales, Solutions, and Legal Information ...................... 45

Worldwide Sales and Design Support ....................... 45

Products .................................................................... 45

PSoC® Solutions ......................................................45

Cypress Developer Community .................................45

Technical Support ..................................................... 45

.. 24

Document Number: 002-29354 Rev. ** Page 3 of 45

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Overview

CYW2019

Sili con Device

Passive Components

(RES, CAP, IND)

24 MHz XTAL

8TR8201

PA/LNA

XRES

32KHZ

XTAL I/O

HCI UART

PUART

SPI

I2C

ADC

(14 Channel)

GPI O x20

I2S/PCM

Functional Block Diagram

Figure 1 illustrates the CYBT-2X30XX-02 functional block diagram.

Figure 1. Functional Block Diagram

Note: General Purpose Input/Output pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Table 5 in the Module

Connections section.

Note: The total number of GPIOs available on the CYBT-2X30XX-02 is 20. Peripheral and/or Serial communication functions are implemented using these 20 GPIOs.

Module Description

The CYBT-2X30XX-02 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. The CYBT-2X30XX-02 will be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions

PCB thickness Height (H) 0.50 ± 0.10 mm Shield height Height (H) 1.20 mm typical Maximum component height Height (H) 0.80 mm typical Total module thickness (bottom of module to top of shield) Height (H) 1.70 mm typical

See Figure 2 for the mechanical reference drawing for CYBT-2X30XX-02.

Document Number: 002-29354 Rev. ** Page 4 of 45

Length (X) 12.5 ± 0.15 mm

Width (Y) 19 ± 0.15 mm

Length (X) 12.5 mm

Width (Y) 4.5 mm

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (Seen from Top)

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on the recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

Document Number: 002-29354 Rev. ** Page 5 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Pad Connection Interface

Solder Pad Connections

(Seen from Bottom)

Optional Host PCB Keep Out Area

Around PCB Antenna

(Seen from Bottom)

As shown in the bottom view of Figure 2 on page 5, the CYBT-2X30XX-02 has 35 connections to a host board via solder pads (SP).

Ta bl e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-2X30XX-02 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 35 Solder Pad 1.11 mm 0.61 mm 0.97 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to

AN96841 for module placement best practices.

3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).

Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-2X30XX-02 PCB Antenna

Document Number: 002-29354 Rev. ** Page 6 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure 7, and Ta b le 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBT-2X30XX-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.633 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-2X30XX-02 Host Layout (Dimensioned) Figure 6. CYBT-2X30XX-02 Host Layout (Relative to Origin)

Document Number: 002-29354 Rev. ** Page 7 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Ta bl e 3 provides the center location for each solder pad on the CYBT-2X30XX-02. All dimensions are referenced to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure 7 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location

Solder Pad

(Center of Pad)

1 (0.33, 6.83) (12.99, 268.90) 2 (0.33, 7.80) (12.99, 307.09) 3 (0.33, 8.76) (12.99, 344.88) 4 (0.33, 9.73) (12.99, 383.07) 5 (0.33, 10.69) (12.99, 420.87) 6 (0.33, 11.66) (12.99, 459.05) 7 (0.33, 12.62) (12.99, 496.85) 8 (0.33, 13.59) (12.99, 535.04)

9 (0.33, 14.55) (12.99, 572.83) 10 (0.33, 15.52) (12.99, 611.02) 11 (0.33, 16.48) (12.99, 648.82) 12 (0.33, 17.45) (12.99, 687.01) 13 (1.42, 18.67) (55.91, 735.04) 14 (2.39, 18.67) (94.09, 735.04) 15 (3.35, 18.67) (131.89, 735.04) 16 17 (5.28, 18.67) (207.87, 735.04) 18 (6.25, 18.67) (246.06, 735.04) 19 (7.22, 18.67) (284.25, 735.04) 20 (8.18, 18.67) (322.05, 735.04) 21 (9.15, 18.67) (360.24, 735.04) 22 (10.11, 18.67) (398.03, 735.04) 23 (11.08, 18.67) (436.22, 735.04) 24 (12.17, 17.45) (479.13, 687.01) 25 (12.17, 16.48) (479.13, 648.82) 26 (12.17, 15.52) (479.13, 611.02) 27 (12.17, 14.55) (479.13, 572.83) 28 (12.17, 13.59) (479.13, 535.04) 29 (12.17, 12.62) (479.13, 496.85) 30 (12.17, 11.66) (479.13, 459.05) 31 (12.17, 10.69) (479.13, 420.87) 32 (12.17, 9.73) (479.13, 383.07) 33 (12.17, 8.76) (479.13, 344.88) 34 (12.17, 7.80) (479.13, 307.09) 35 (12.17, 6.83) (479.13, 268.90)

Location (X,Y) from

Orign (mm)

(4.32, 18.67) (170.08, 735.04)

Dimension from

Orign (mils)

Document Number: 002-29354 Rev. ** Page 8 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Module Connections

Note

2. The CYBT-2X30XX-02 can configure GPIO connections to any Input/Output function described in Table 5 using the ModusToolbox Device Configurator.

Ta bl e 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available

on the CYBT-2X30XX-02 can be configured to any of the input or output functions listed in Tab le 5 . Ta bl e 4 specifies any function that is required to be used on a specific solder pad, and also identifies SuperMux capable GPIOs that can be configured using the ModusToolbox device configurator.

Table 4. CYBT-2X30XX-02 Solder Pad Connection Definitions

Pad Pad Name Silicon Pin Name XTALI/O ADC GPIO SuperMux Capable

1 GND GND Ground 2 XRES RST_N External Reset (Active Low) 3 P29 P29 - IN10 ✓✓ see Table 5 4P26 P26 - - ✓✓ see Table 5 5P37 P37 - IN2 ✓✓ see Table 5 6P1 P1 - IN28 ✓✓ see Table 5 7P0 P0 - IN29 ✓✓ see Table 5 8 P10 P10 - IN25 ✓✓ see Table 5

9P11 P11 - IN24 ✓✓ see Table 5 10 P13 P13 - IN22 ✓✓ see Table 5 11 P 14 P1 4 - I N21 ✓✓ see Table 5 12 P12 P12 - IN23 ✓✓ see Table 5 13 GND GND Ground 14 P9 P9 - IN26 ✓✓ see Table 5 15 P17 P17 - IN18 ✓✓ see Table 5 16 P5 P5 - - ✓✓ see Table 5 17 P6 P6 - - ✓✓ see Table 5 18 P2 P2 - - ✓✓, see Ta bl e 5 19 GND GND Ground

20 XTALI_32K XTALI_32K

21 XTALO_32K XTALO_32K

22 GND GND Ground 23 P3 P3 - - ✓✓ see Table 5 24 P8 P8 - IN27 ✓✓ see Table 5 25 P15 P15 - IN20 ✓✓ see Table 5 26 P4 P4 - - ✓✓ see Table 5 27 P28 P28 - IN11 ✓✓ see Table 5 28 UART_CTS_N UART_CTS_N UART (HCI UART) Clear To Send Input Only

29 HOST_WAKE HOST_WAKE

30 UART_RXD UART_RXD UART (HCI UART) Receive Data Only 31 UART_TXD UART_TXD UART (HCI UART) Transmit Data Only 32 DEV_WAKE DEV_WAKE

33 UART_RTS_N UART_RTS_N 34 VDD VDDIO Power Supply Input (2.5V ~ 3.6V) 35 GND GND Ground

External Oscillator Input

(32KHz)

External Oscillator

Output (32KHz)

A signal from the CYBT-2X30XX-02 module to the host indicating that the Bluetooth device requires

A signal from the host to the CYBT-2X30XX-02 module indicating that the host requires attention.

UART (HCI UART) Request To Send Output Only

-- -

attention

[2]

Document Number: 002-29354 Rev. ** Page 9 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Ta bl e 5 details the available Input and Output functions that are configurable to any solder pad in Table 4 that are marked as SuperMux

capable.

Table 5. GPIO SuperMux Input and Output Functions

Function Input or Output Function Type GPIOs Required Function Connection Description

SPI 1 Clock

SPI 1 Chip Select

SPI 1 Input/Output

SPI 2 Input/Output

Input Serial Communication Input

PUART

Output Serial Communication Output

C Input/Output

PCM In Input Audio Input Communication 3

PCM Out Output Audio Output Communication 3

S In Input Audio Input Communication 3

S Out Output Audio Output Communication 3

PDM Input Microphone 1 ~ 2

PWM Output Pulse Width Modulator 1 ~ 6

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

4 ~ 7

SPI 1 MOSI

SPI 1 MISO SPI 1 I/O 2 (Quad SPI) SPI 1 I/O 3 (Quad SPI)

SPI 1 Interrupt

SPI 2 Clock

SPI 2 Chip Select

SPI 2 MOSI

SPI 2 MISO SPI 2 I/O 2 (Quad SPI) SPI 2 I/O 3 (Quad SPI)

SPI 2 Interrupt

Peripheral UART RX

Peripheral UART CTS

Peripheral UART TX

Peripheral UART RTS

I2C Clock

I2C Data

PCM Input

PCM Clock

PCM Sync

PCM Output

PCM Clock

PCM Sync

I2S DI, Data Input

I2S WS, Word Select

I2S Clock I2S DO, Data Output I2S WS, Word Select

I2S Clock

PDM Input Channel 1 PDM Input Channel 2

PWM Channel 0 PWM Channel 1 PWM Channel 2 PWM Channel 3 PWM Channel 4 PWM Channel 5

Document Number: 002-29354 Rev. ** Page 10 of 45

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Connections and Optional External Components

UART_TXD

UART_RTS_N

HOST_WAKE

UART_RXD

GND

VDD

1323

XRES

GND

UART_CTS_N

GND

DEV_WAKE

P29

GND

P10

P13

P12

P11

P14

P17

P26

P15

XTALO_32K

XTALI_32K

P37

P28

Antenna Matching

37 External Antenna Pad

36 GND

LC1

TBD

LC2

TBD

LC3

TBD

Power Connections (VDD)

The CYBT-2X30XX-02 contains one power supply connection, VDD. VDD accepts a supply input of 2.5 V to 3.6 V. Ta b le 1 3 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Tab le 1 3.

External Reset (XRES)

The CYBT-2X30XX-02 has an integrated power-on reset circuit which completely resets all circuits to a known power-on state. This action can also be invoked by an external reset signal, forcing it into a power-on reset state. XRES is an active-low input signal on the CYBT-2X30XX-02 module (solder pad 2). The CYBT-2X30XX-02 does not require external pull-up resistors on the XRES input. Refer to Figure 11 on page 17 for Power On and XRES operation and timing requirements during power on events.

HCI UART Connections

The recommendations in this section apply to the HCI UART (Solder Pads 28, 30, 31, and 33). For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:

■ UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.

■ UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the

module.

External Component Recommendation

Power Supply Circuitry

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to the module pad connection.

If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).

Antenna Matching Network Requirements

The CYBT-263064-02 module requires ANT and GND connections to an external antenna via the RF pad connections on the module (Pads 36 and 37). In order to optimize RF performance, an Antenna Matching Network (AMN) is required to be placed between the ANT connection (Pad 37) and the antenna used in the final design. Figure 8 details the recommended Pi topology circuit footprint to use for the Antenna Matching Network.

Figure 8. Recommended Antenna Matching Network for CYBT-263064-02 Module

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CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

The design guidelines that should be followed when completing the Antenna Matching Network are as follows:

5 4 3 2 1

Cypress Semiconductor Corp.

UART_TXD

UART_RTS_N

HOST_WAKE

UART_RXD

MODULE PAD ASSIGNMENT

GND

VDD

Castellated solder pad

1323

XRES

GND

UART_CTS_N

GND

(BOTTOM VIEW)

DEV_WAKE

P29

GND

P10

P13

P12

P11

P14

P17

P26

P15

XTALO_32K

XTALI_32K

P37

P28

Filter

Antenna Matching

P32

P27

TP37

ANT

37 External Antenna Pad

36 GND

TP36

CYBT-273063-02 PCB ANT

CYBT-263064-02

CYBT-263065-02

UFL CONN

EXTERNAL ANT PAD

BT_RF

P0 P1 P2 P3

P5 P6

P10

P12 P13

P15 P17

RXEN

XTALI_32K

UART_CTS_N UART_RTS_N UART_RXD UART_TXD

HOST_WAKE

DEV_WAKE

XTALO_32K

XRES

P29

XRES

P26

P28

TXEN

P11

P14

P29

P37

P17

XTALO_32K

XTALI_32K

P13

P10

P12

P26

DEV_WAKE

HOST_WAKE

P15

UART_RXD

UART_RTS_N

UART_CTS_N

UART_TXD

P37

P28

P11

P14

BT_RF

RXEN TXEN

DIGLDO_OUTVDD

RFLDO_OUT

DIGLDO_OUT

VDD

RFLDO_OUTCBUCK_OUT

RFLDO_OUT

VDD

Title

Size

Document Number Re v

Date: Sheet

630-20133-01

1.0

CYBT-273063_263064_263065-02

11Tuesday, August 20, 2019

Title

Size

Document Number Re v

Date: Sheet

630-20133-01

1.0

CYBT-273063_263064_263065-02

11Tuesday, August 20, 2019

Title

Size

Document Number Re v

Date: Sheet

630-20133-01

1.0

CYBT-273063_263064_263065-02

11Tuesday, August 20, 2019

LC8

0Ohm,0201

R1 10K,0201

C1512pF,0201

C10

2.2uF,0201

LC5 10pF,0201

LC1

TBD,0201

TP27

TP6

LC10

1.8pF,0201

C12

0.1uF,0201

LC2

0.9pF_TBD,0201

TP9

CYW20819_B62

U1B

PMU_LDO_ONLY_STRAP

RFLDO_DIGLDO_VDDIN

XTALO

XTALI

NC_0 (PALDO_VDDIN)

IFVDD

PMU_AVDD

DIGLDO_VDDOUT

NC_1 (PALDO_VDDOUT)

PLLVDD

SR_VLX

SR_PVDD

RFLDO_VDDOUT

PAVDD

VCOVDD

XTALO_32K

XTALI_32K

PMU_AVSSF4PLLVSSF7PAVSSG6VCOVSSG7SR_PVSSH1IFVSS

C14 10pF,0201

TP20

TP22

24MHz

LC4 10pF,0201

TP8

TP21

TP4

TP13

FB1 600@100M

TP30

TP2

0.1uF,0201

TP1

TP11

R2 10K,0201

0.1uF,0201

TP16

TP17

2.2uH,0603

LC9

1.8pF,0201

TP25

TP3

LC11

2.7nH,0201

TP24

LC6 10pF,0201

2.2uF,0201

TP26

TP15

TP29

TP35

C19

100pF,0201

TP19

C13

0.1uF,0201

LC3

5.6nH_TBD,0201

CYW20819_B62

U1A

ADC_AVSS

UART_CTS_N

UART_TXD

UART_RXD

HOST_WAKE

UART_RTS_N

DEV_WAKE

RST_N

JTAG_SEL

P12

P17

P13

P11

P14

P15

P10

P28

P29

P26

P37

P27

P32

VDDO1

VDDC1

VDDO2

VDDC2

VSSC1C3VSSC2C6VSSC3

C17

1.0uF,0201

TP7

C1612pF,0201

10uF,0402

FB2 600@100M

UFL Connector_TE_1909763-1

1 2

TP31

8TR8201

NC_1

GND_1

GND_2

TXRX

TXEN

RXEN

NC_2

GND_3

GND_4

ANT

GND_5

NC_3

DNC13VDD_114NC_415VDD_216GND_6

TP18

C11

0.1uF,0201

TP5 TP28

TP12

TP33

TP32

TP23

TP34

0.1uF,0201

TP14

LC7

DNI,0201

0.1uF,0201

TP10

4.7uF,0402

■ The AMN should be placed close to the antenna on the main board.

■ Routing to the AMN from the ANT pad on the module must be controlled to an impedance of 50 W.

The final AMN circuit may contain only a single component, or all three components shown above. The final number and type of components will be determined based on the actual design of the system, and the final values for each component can be determined through tuning the AMN. For details on how to properly tune an AMN, please refer to Application Note AN91445.

Figure 9 illustrates the CYBT-2X30XX-02 schematic.

Figure 9. CYBT-2X30XX-02 Schematic Diagram

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Critical Components List

Ta bl e 6 details the critical components used in the CYBT-2X30XX-02 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 62-pin QFN Bluetooth Silicon Device - CYW20819 Crystal Y1 24.000 MHz, 12PF PA/LNA U2 PA/LNA, +23 dBm maximum boost

Antenna Design

Ta bl e 7 details the PCB trace antenna used in the CYBT-2X30XX-02 module.

Table 7. PCB Antenna Specifications

Item Description

Frequency Range 2400–2500 MHz Peak Gain –0.7 dBi typical Return Loss 10 dB minimum

Qualified Antenna for CYBT-263064-02 and CYBT-263065-02

The CYBT-263064-02 and CYBT-263065-02 module has been designed to work with a standard 2.2 dBi dipole antenna. Any antenna of equivalent or less gain can be used without additional application and testing for FCC regulations. Ta bl e 8 details the approved antennas for the CYBT-263064-02 and CYBT-263065-02 module for Bluetooth operation.

Table 8. Qualified Antennas

Manufacturer Part Number Gain

Pulse W1010 2.0 dBi

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Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening.

Table 9. Bluetooth Features

Bluetooth 1.0 Bluetooth 1.2 Bluetooth 2.0

Basic Rate Interlaced Scans EDR 2 Mbps and 3 Mbps SCO Adaptive Frequency Hopping – Paging and Inquiry eSCO – Page and Inquiry Scan – – Sniff – –

Bluetooth 2.1 Bluetooth 3.0 Bluetooth 4.0

Secure Simple Pairing Unicast Connectionless Data Bluetooth Low Energy Enhanced Inquiry Response Enhanced Power Control – Sniff Subrating eSCO –

Bluetooth 4.1 Bluetooth 4.2 Bluetooth 5.0

Low Duty Cycle Advertising Data Packet Length Extension LE 2 Mbps Dual Mode LE Secure Connection Slot Availability Mask LE Link Layer Topology Link Layer Privacy High Duty Cycle Advertising

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Power Management Unit

Figure 10 shows the CYW20819 power management unit (PMU) block diagram. The CYW20819 includes an integrated buck

regulator, a digital LDO for the digital core, and an RF LDO for the Radio. The PMU also includes a brownout detector which places the part in shutdown when input voltage is below a certain threshold.

Figure 10. Default Usage Mode

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Integrated Radio Transceiver

The CYBT-2X30XX-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band.

Transmitter Path

CYBT-2X30XX-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYBT-2X30XX-02 has an integrated power amplifier (PA) that can transmit up to +20 dBm for class 1 operation.

Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-2X30XX-02 to be used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYBT-2X30XX-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.

Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the band. The CYBT-2X30XX-02 uses an internal loop filter.

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Microcontroller Unit

The CYBT-2X30XX-02 includes a Cortex-M4 processor with 1 MB of program ROM, 176 KB of RAM, and 256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code execution from flash at near maximum speed and low power consumption.

The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.

External Reset

Figure 11 shows power on and reset timing of the CYBT-2X30XX-02. After VBAT is applied and reset is inactive, the internal buck

turns on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows the digital core to come out of reset. As shown in the figure, external reset can be applied at any time subsequent to power up.

Figure 11. Reset Timing

32-kHz Crystal Oscillator

The CYBT-2X30XX-02 includes connections for an external 32-kHz oscillator to provide accurate timing during low power operations.

Figure 12 shows the 32-kHz XTAL oscillator with external components and Tab le 1 0 lists the oscillator characteristics. This oscillator

can be operated with a 32 kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must have an accuracy of ±250 ppm or better per the BT spec over temperature and including aging. The external component values should be: R1 = 10 MΩ and C1 = C2 = 6 pF. The values of C1 and C2 are used to fine-tune the oscillator. A XTAL meeting the C1 and C2 values should be used.

Figure 12. 32 kHz Oscillator Block Diagram

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Table 10. XTAL Oscillator Characteristics

Parameter Symbol Conditions Minimum Ty p ical Maximum Unit

Output frequency F Frequency tolerance – Over temperature and aging – – 250 ppm XTAL drive level P XTAL series resistance R XTAL shunt capacitance C Load capacitance C

oscout

drv

series

shunt

For crystal selection – – 0.5 μW For crystal selection – – 70 kΩ For crystal selection – – 2.2 pF For crystal selection – 6 – pF

– – 32.768 – kHz

Power Modes

The CYBT-2X30XX-02 support the following HW power modes are supported:

■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.

■ Idle mode - CPU is paused.

■ Sleep mode - All system clocks are idle except for the LPO. The device can wake up either after a programmed period of time has

expired or if an external event is received via one of the GPIOs. In Sleep mode, the CPU is in WFI (wait for interrupt) and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. The state of the device is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.

■ Power Down Sleep (PDS) mode - Radio powered down and digital core mostly powered down except for RAM, registers, and

some core logic. CYBT-2X30XX-02 can wake up either after a programmed period of time has expired or if an external event is received via one of the GPIO.

■ Extended PDS (ePDS) - This is an extension of PDS Mode. In this mode, only the main RAM and ePDS control circuitry retains

power. As in other modes, the CYBT-2X30XX-02 can wake up either after a programmed period or upon receiving an external event.

■ HID-OFF (Deep Sleep) mode - Core, radio, and regulators powered down. Only the GPIO domain is powered. In this mode, the

CYBT-2X30XX-02 can be woken up either by an external event on one of the GPIOs or after a programmed period of time has expired. The lowest power option for HID-Off mode is to wake by external event, allowing all clocking sources to remain off. If a timed wake HID-Off state is desired, this is accomplished by powering the external or internal LPO. Current consumption will increase slightly in timed wake HID-Off mode to account for the LPO power. After wakeup, the part will go through full FW initialization although it will retain enough information to determine that it came out of HID-Off and the event that caused the wake up.

Transition between power modes is handled by the on-chip firmware with host/application involvement. In general, ePDS is the most power-efficient mode for active use cases. HID-Off is preferable for non-connectable beacon use cases (long advertisement intervals).

Firmware

The CYBT-2X30XX-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes. The ROM also supports OTA firmware update.

The CYBT-2X30XX-02 is fully supported by the Cypress ModusToolbox IDE. ModusToolbox releases provide latest ROM patches, drivers, and sample applications allowing customized applications using the CYBT-2X30XX-02 to be built quickly and efficiently.

Watchdog

CYBT-2X30XX-02 includes an onboard watchdog with a period of approximately 4 seconds. The watchdog generates an interrupt to the Firmware after 2 seconds of inactivity and resets the device after 4 seconds.

Lockout Functionality

The CYBT-2X30XX-02 powers up with SWD access to flash and RAM is disabled. After reset, FW checks OCF for the presence of a security lockout field. If present, FW leaves SWD Flash and RAM access disabled and also blocks any HCI commands from reading the raw contents of the RAM or Flash. This provides an effective way of protection against tampering, dumping, probing, or reverse engineering of the user application stored in the on-chip flash. The only firmware upgrade path in this scenario is secure over-the-air (OTA) update. The security field can be programmed in the factory after all programming and testing has been done.

True Random Number Generator

The CYBT-2X30XX-02 includes a hardware TRNG (True Random Number Generator). Applications can access the random number generator via firmware APIs.

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Peripherals and Communication Interfaces

I2C

The CYBT-2X30XX-02 provides a 2-pin I2C master/slave interface to communicate with I2C compatible peripherals. The following transfer clock rates are supported:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I

■ 1 MHz (Compatibility with high-speed I

The I2C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where read/write can be up to 64 bytes.

SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 4), allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I multimaster capability or flexible wait-state insertion by either master or slave devices.

HCI UART Interface

CYBT-2X30XX-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYBT-2X30XX-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface CYBT-2X30XX-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-2X30XX-02 or allow the CYBT-2X30XX-02 to sleep when radio activities permit. The CYBT-2X30XX-02 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. Combined, the two signals allow the host and the CYBT-2X30XX-02 to optimize system power consumption by allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific command.

The FW UART driver allows applications to select different baud rates.

C-compatible speed)

C-compatible devices is not guaranteed)

C does not support

Peripheral UART Interface

The CYBT-2X30XX-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the same as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be configured individually and separately for each functional pin. The CYBT-2X30XX-02 can map the peripheral UART to any GPIO.

Serial Peripheral Interface

The CYBT-2X30XX-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI operations. Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-2X30XX-02 has optional I/O ports that can be configured individually and separately for each functional pin.

SPI IO voltage depends on VDDO.

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ADC Port

The CYBT-2X30XX-02 includes a Σ-Δ ADC designed for audio and DC measurements. The ADC can measure the voltage on 15 GPIOs (P0, P1, P8-P15, P17, P28, P29, and P37). When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in Direct Current (DC) Mode.

The application can access the ADC through the ADC driver included in the firmware. The following CYBT-2X30XX-02 module solder pads can be used as ADC inputs:

■ Pad 3: P29, ADC Input Channel 10

■ Pad 5: P37, ADC Input Channel 2

■ Pad 6: P1, ADC Input Channel 28

■ Pad 7: P0, ADC Input Channel 29

■ Pad 8: P10, ADC Input Channel 25

■ Pad 9: P11, ADC Input Channels 24

■ Pad 10: P13, ADC Input Channel 22

■ Pad 11: P14, ADC Input Channel 21

■ Pad 12: P12, ADC Input Channel 23

■ Pad 14: P9, ADC Input Channels 26

■ Pad 15: P17, ADC Input Channels 18

■ Pad 24: P8, ADC Input Channels 27

■ Pad 24: P15, ADC Input Channels 20

■ Pad 27: P28, ADC Input Channels 11

GPIO Port

The CYBT-2X30XX-02 has a maximum of 20 GPIOs. All GPIOs support the following:

■ Programmable pull-up/down of approximately 45 kΩ.

■ Input disable mode, allowing pins to be left floating or analog signals connected without risk of leakage.

■ Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

■ P26/P28/P29 can sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.

Most peripheral functions can be assigned to any GPIO using the ModusToolbox Device Configurator. For details on the functions that are assignable via the ModusToolbox Device Configurator, refer to Table 5.

The following list details the GPIOs that are available on the CYBT-2X30XX-02 module:

■ P0-P6, P8-P15, P17, P26-P29, and P37

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PWM

The CYBT-2X30XX-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:

■ Each of the six PWM channels contains the following registers: ❐ 16-bit initial value register (read/write) ❐ 16-bit toggle register (read/write)

❐ 16-bit PWM counter value register (read)

■ PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used: ❐ To configure each PWM channel ❐ To select the clock of each PWM channel

❐ To change the phase of each PWM channel

The application can access the PWM module through the FW driver.

Figure 13 shows the structure of one PWM channel.

Figure 13. PWM Block Diagram

PDM Microphone

The CYBT-2X30XX-02 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:

■ 8 kHz

■ 16 kHz

The external digital microphone takes in a 2.4-MHz clock generated by the CYBT-2X30XX-02 and outputs a PDM signal, which is registered by the PDM interface with either the rising or falling edge of the 2.4-MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.

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I2S Interface

The CYBT-2X30XX-02 supports a single I2S digital audio port. with both master and slave modes. The I2S signals are:

■ I

S Clock: I2S SCK

■ I

S Word Select: I2S WS

■ I

S Data Out: I2S DO

■ I

S Data In: I2S DI

S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I Specifications. The MSB of each data word is transmitted one bit clock cycle after the I edge of bit clock. Left Channel data is transmitted when I Data bits sent by the CYBT-2X30XX-02 are synchronized with the falling edge of I the rising edge of the I

S SCK.

S WS is low, and right-channel data is transmitted when I2S WS is high.

S WS transition, synchronous with the falling

S SCK and should be sampled by the receiver on

S bus, per I2S

The clock rate in master mode is either one of the following:

■ 32 kHz × 32 bits per frame = 1024 kHz

■ 32 kHz × 50 bits per frame = 1600 kHz

The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

Note: The PCM interface shares HW with the I

S interface and only one can be used at a given time.

PCM Interface

The CYBT-2X30XX-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-2X30XX-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-2X30XX-02.The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

Note: The PCM interface shares HW with the I Note: Only audio source (other than SCO) use cases are supported on 20819 at this time.

S interface and only one can be used at a given time.

Slot Mapping

The CYBT-2X30XX-02 supports up to three simultaneous full-duplex channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The CYBT-2X30XX-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.

Data Formatting

The CYBT-2X30XX-02 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYBT-2X30XX-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

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Electrical Characteristics

The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 11. Silicon Absolute Maximum Ratings

Requirement Parameter

Maximum Junction Temperature – – TBD °C VDDO1/VDDO2 –0.5 – 3.795 V IFVDD/PLLVDD/VCOVDD/VDDC –0.5 – 1.38 V PMUAVDD/SR_PVDD –0.5 – 3.795 V DIGLDO_VDDIN –0.5 – 1.65 V RFLDO_VDDIN –0.5 – 1.65 V MIC_AVDD –0.5 – 3.795 V

Table 12. ESD/Latch-up

Requirement Parameter

ESD Tolerance HBM (Silicon) –2000 – 2000 V ESD Tolerance CDM (Silicon) –500 – 500 V Latch-up – 200 – mA

Table 13. Power Supply Specifications

Parameter Conditions Min. Typical Max. Unit

VDD input Module Input 1.76 3.0 3.63 V VDD Ripple Module Input Ripple (VDD) – – 100 mV VBAT Input Internal to Module (not accessible) 1.90 3.0 3.6 V PMU turn-on time VBAT is ready. – – 300 μs

Min. Nom. Max.

Specification

Unit

Table 14. Shutdown Voltage (Brown Out)

Parameter

SHUT

The CYBT-2X30XX-02 uses an onboard low voltage detector to shut down the device when supply voltage (VBAT) drops below the operating range.

Min. Typ . Max.

1.54 1.62 1.7 V

Specification

Unit

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Current Consumption

Ta bl e 1 5 provides the current consumption measurements taken at the input of LDOIN and VDDIO combined (LDOIN = VDDIO =

3.0 V).

Table 15. Current Consumption

Operational Mode Conditions Typ ica l Unit

HCI

RX Continuous RX 5.9 TX Continuous TX - 4 dBm 5.8 PDS – 16.5

HID-Off (SDS) 32 kHz XTAL on 1.75

48 MHz with Pause 1.3 48 MHz without Pause 2.55

μAePDS All RAM retained 8.7

Silicon Core Buck Regulator

Table 16. Core Buck Regulator

Parameter Conditions Min. Typ. Max. Unit

Input Supply, VBAT DC Range 1.62 3.0 3.63 V

Output Current

Output Voltage

Output Voltage Accuracy

Ripple Voltage

Output Inductor, L Output Capacitor, C Input Capacitor, C Input Supply Voltage Ramp

Time

OUT

Active Mode – < 60 100 PDS Mode – < 60 70 Active Mode 1.1 1.26 1.4

[3]

0.94 Avg

(0.92-0.96)

–+4+2%

2.2 – μH

4.7 – 10 –

1.4

PDS Mode, 40 mV min regulation window. 0.76

Active Mode, includes line and load regulation. Before trim: After trim:

Active Mode

2.2 μH ± 25% inductor, DCR = 114 mΩ ± 20%

4.7 μF ± 10% capacitor, Total ESR < 20 mΩ PDS Mode 40 40 –

Components are included on module.

0 to 3.3 V 40 – – μs

–4 –2

–3–

1.6

3.0

4.0

μF

Note

3. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

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Digital LDO

Note

4. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

Table 17. Digital LDO

Parameter Condition Min Typ Max Unit

Input Supply, DIGLDO_VDDIN Min must be met for correct operation V

Range 0.9 1.2 1.275

Output Voltage, DIGLDO_VDDOUT

Step – 25 – mV

Accuracy after trimming –2 – +2 % Dropout Voltage At max load current – – 20 mV Output Current DC Load 0.075 40 60 mA Quiescent Current At T ≤ 85 °C, V Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 mΩ¶1.55 Line Regulation 1.235 V ≤ V Load Regulation V

Load Step Error

Leakage Current

In-rush Current C LDO Turn On Time C

PSRR

= 1.2 V, V

OUT

step 1 mA ↔ 20 mA @ 1 μs rise/fall,

OUT

= 2.2 μF, V

OUT

Power down Mode, V

= 2.2 μF, V

OUT

= 2.2 μF, V

OUT

= 2.2 μF, 1.235V ≤ VIN ≤ 1.4 V, V

OUT

= 20 mA

OUT

f = 1 kHz

= 1.4 V – – 40 μA

≤ 1.4 V – 5 10 mV/V

= 1.26 V, 1 mA ≤ I

= 1.235 V, V

= 1.4 V, Temp = 25 °C––50nA

= 1.4 V, Temp = 125 °C––2μA

= 1.4 V, V

OUT

≤ 25 mA – – 0.44 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA

= 1.2 V, I

= 20 mA – – 120 μs

OUT

= 1.2 V,

OUT

f = 100 kHz

+ 20 mV 1.26 1.4

OUT

[4]

2.2 – μF

–24 – +24 mV

––dB

RF LDO

Table 18. RF LDO

Parameter Conditions Min. Typ. Max. Unit

Input Supply, RFLDO_VDDIN Min must be met for correct operation V

Range 1.1 1.2 1.275

Output Voltage, RFLDO_VDDOUT

Step – 25 – mV

Accuracy after trimming –2 – +2 % Dropout Voltage At max load current – – 20 mV Output Current DC Load 0.075 20 60 mA Quiescent Current At T ≤ 85 °C, V Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 mΩ¶1.55 Line Regulation 1.235 V ≤ V Load Regulation V

Load Step Error

Leakage Current

In-rush Current C LDO Turn On Time C

= 1.2 V, V

OUT

step 1 mA ↔ 20 mA @ 1 μs rise/fall,

OUT

= 2.2 μF, V

OUT

Power down Mode, V

= 2.2 μF, V

OUT

= 2.2 μF, V

OUT

= 1.4 V – – 40 μA

≤ 1.4 V – 5 10 mV/V

= 1.26 V, 1 mA ≤ I

= 1.235 V, V

= 1.4 V, Temp = 25 ℜ°C––50nA

= 1.4 V, Temp = 125 ℜ°C––2μA

= 1.4 V, V

OUT

≤ 25 mA – – 0.44 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA = 1.2 V, I

= 20 mA – – 120 μs

OUT

+ 20 mV 1.26 1.4

OUT

[4]

2.2 – μF

–24 – +24 mV

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Table 18. RF LDO (continued)

Parameter Conditions Min. Typ. Max. Unit

= 2.2 μF, 1.235 V ≤ VIN ≤ 1.4 V, V

OUT

= 20 mA

PSRR

OUT

f = 1 kHz

f = 100 kHz

Noise

= 2.2 μF, V

OUT

20 mA

f = 30 kHz

= 1.235 V, V

f = 100 kHz

Digital I/O Characteristics

Table 19. Digital I/O Characteristics

Characteristics Symbol Minimum Typical Maximum Unit

Input low voltage (VDD = 3 V) V Input high voltage (VDD = 3 V) V Input low voltage (VDD = 1.8 V) V Input high voltage (VDD = 1.8 V) V Output low voltage V Output high voltage V Input low current I Input high current I Output low current (VDD = 3 V, VOL = 0.4 V) I Output low current (VDD = 3 V, V Output high current (VDD = 3 V, V Output high current (VDD = 1.8 V, VOH = 1.4 V) I Input capacitance C

= 1.8 V) I

= 2.6 V) I

OUT

= 1.2 V,

OUT

––dB

= 1.2 V, I

OUT

––80

––0.8V

2.4 – – V ––0.4V

1.4 – – V ––0.4V

VDDO – 0.4 V – – V

––1.0μA ––1.0μA ––4.0mA ––2.0mA ––8.0mA ––4.0mA ––0.4pF

nV√Hz nV√Hz

ADC Characteristics

Table 20. Electrical Characteristics

Parameter Symbol Conditions/Comments Min. Ty p. Max. Unit

Current consumption I

TOT

––23mA

Power down current – At room temperature – 1 – μA ADC Core Specification ADC reference voltage VREF From BG with ±3% accuracy – 0.85 – V ADC sampling clock – – – 12 – MHz Absolute error – Includes gain error, offset and

––5%

distortion. Without factory calibration. Includes gain error, offset and

––2%

distortion. After factory calibration.

ENOB – For audio application 12 13 – Bit

For static measurement 10 – –

ADC input full scale FS For audio application – 1.6 –

For static measurement 1.8 – 3.6

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Table 20. Electrical Characteristics (continued)

Parameter Symbol Conditions/Comments Min. Ty p. Max. Unit

Conversion rate – For audio application 8 16 – kHz

For static measurement 50 100 –

Signal bandwidth – For audio application 20 – 8K Hz

For static measurement – DC –

Input impedance R

Startup time – For audio application – 10 – ms

MIC PGA Specifications MIC PGA gain range – – 0 – 42 dB MIC PGA gain step – – – 1 – dB MIC PGA gain error – Includes part-to-part gain variation –1 – 1 dB PGA input referred noise – At 42 dB PGA gain A-weighted – – 4 μV Passband gain flatness – PGA and ADC, 100 Hz–4 kHz –0.5 – 0.5 dB MIC Bias Specifications MIC bias output voltage – At 2.5-V supply – 2.1 – V MIC bias loading current – – – – 3 mA MIC bias noise – Refers to PGA input 20 Hz to

MIC bias PSRR – at 1 kHz 40 – – dB ADC SNR – A-weighted 0 dB PGA gain 78 – – dB ADC THD + N – –3 dBFS input 0 dB PGA gain 74 – – dB GPIO input voltage Always lower than avddBAT – – 3.6 V GPIO source impedance

[5]

– Resistance – – 1 kΩ

For audio application 10 – – KW For static measurement 500 – –

For static measurement – 20 – μs

––3μV

8 kHz, A-weighted

Capacitance – – 10 pF

Note

5. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.

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Chipset RF Specifications

Notes

6. The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off.

7. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

8. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

Ta bl e 2 1, Table 22, Ta bl e 2 3, and Ta bl e 2 4 apply to single-ended industrial temperatures. Unused inputs are left open.

Table 21. BR/EDR - Receiver RF Specifications

Parameter Mode and Conditions Min Typ Max Unit

Receiver Section

Frequency range – 2402 – 2480 MHz

[6]

RX sensitivity

GFSK, BR GFSK 0.1% BER, 1 Mbps – –92 EDR 2M – –93.5 – EDR 3M – –87 –

Maximum input – –20 – – dBm

Interference Performance

C/I cochannel GFSK, BR GFSK 0.1% BER C/I 1 MHz adjacent channel GFSK, BR GFSK 0.1% BER C/I 2 MHz adjacent channel GFSK, BR GFSK 0.1% BER C/I ≥ 3 MHz adjacent channel GFSK, BR GFSK 0.1% BER C/I image channel GFSK, BR GFSK 0.1% BER C/I 1 MHz adjacent to image channel GFSK, BR GFSK 0.1% BER

Out-of-Band Blocking Performance (CW)

[8]

[7]

––11.0 ––0.0 – – –30.0 – – –40.0 –––9.0 – – –20.0

30 MHz to 2000 MHz BR GFSK 0.1% BER – –10.0 – 2000 MHz to 2399 MHz BR GFSK 0.1% BER – –27 – 2498 MHz to 3000 MHz BR GFSK 0.1% BER – –27 – 3000 MHz to 12.75 GHz BR GFSK 0.1% BER – –10.0 –

Intermodulation Performance

[7]

BT, interferer signal level BR GFSK 0.1% BER – – –39.0 dBm Spurious Emissions 30 MHz to 1 GHz – – – –57.0 1 GHz to 12.75 GHz – – – –55.0

–dBm

dBm

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Table 22. BR/EDR - Transmitter RF Specifications

Parameter Min Ty p Max Unit

Transmitter Section

Frequency range 2402 – 2480 MHz Class 2: BR TX power – 4.0 – Class 2: EDR 2M and 3M TX power – 0 – 20 dB bandwidth – 930 1000 kHz

Adjacent Channel Power

|M – N| = 2 – – –20 |M – N| ≥ 3

Out-of-Band Spurious Emission

30 MHz to 1 GHz – – –36.0 1 GHz to 12.75 GHz – – –30.0

1.8 GHz to 1.9 GHz – – –47.0

5.15 GHz to 5.3 GHz – – –47.0

LO Performance

Initial carrier frequency tolerance –75 – +75 kHz Frequency Drift DH1 packet –25 – +25

DH5 packet –40 – +40 Drift rate –20 – 20 kHz/50 µs

Frequency Deviation

Average deviation in payload (sequence used is 00001111) 140 – 175 Maximum deviation in payload (sequence used is 10101010) 115 – – Channel spacing – 1 – MHz

[9]

– – –40

dBm

kHzDH3 packet –40 – +40

kHz

Table 23. BLE RF Specifications

Parameter Conditions Minimum Typ ical Maximum Unit

Frequency range N/A 2402 – 2480 MHz

RX sensitivity

TX power N/A – 4.0 – Mod Char: Delta F1 average N/A 225 255 275 kHz Mod Char: Delta F2 max Mod Char: Ratio N/A 0.8 – – %

Notes

9. Meets SIG Specification.

10. Dirty TX is Off.

11. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

[10]

GFSK, BDR GFSK 0.1% BER 0.1% BER, 1 Mbps

[11]

N/A 99.9 – – %

––95–

dBm

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Table 24. BLE2 RF Specifications

Note

12. 255 byte packet.

Parameter Conditions Minimum Typ ical Maximum Unit

RX sensitivity TX power – – 4.0 –

[12]

–––89–

dBm

Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

UART Timing

Table 25. UART Timing Specifications

Reference Characteristics Min. Typ. Max. Unit

1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods 2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods 3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods

Figure 14. UART Timing

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SPI Timing

The SPI interface can be clocked up to 24 MHz.

Ta bl e 2 6 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2.

Table 26. SPI Mode 0 and 2

Reference Characteristics Min. Max. Unit

1 Time from master assert SPI_CSN to first clock edge 45 –

SCK

3 Idle time between subsequent SPI transactions 1 SCK –

Figure 15. SPI Timing, Mode 0 and 2

ns2 Setup time for MOSI data lines 6 ¾

Ta bl e 2 7 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3.

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Table 27. SPI Mode 1 and 3

Reference Characteristics Min. Max. Unit

1 Time from master assert SPI_CSN to first clock edge 45 –

SCK

3 Idle time between subsequent SPI transactions 1 SCK –

Figure 16. SPI Timing, Mode 1 and 3

ns2 Setup time for MOSI data lines 6 ¾

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I2C Compatible Interface Timing

Notes

13. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

14. Time that the CBUS must be free before a new transaction can start.

The specifications in Table 27 references Figure .

Table 28. I2C Interface Timing Specifications (up to 1 MHz)

Reference Characteristics Minimum Maximum Unit

100

1 Clock frequency –

2 START condition setup time 650 – 3 START condition hold time 280 – 4 Clock low time 650 – 5 Clock high time 280 –

[14]

[13]

0 –

650 –

6 Data input hold time 7 Data input setup time 100 – 8 STOP condition setup time 280 – 9 Output valid from clock – 400 10 Bus free time

400 800

1000

kHz

Figure 17.

I2C Interface Timing Diagram

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I2S Interface Timing

I2S timing is shown below in Table 29, Figure 18, and Figure 19.

Table 29. Timing for I

Clock Period T T

HIGH t

LOWt

HIGH t

LOW t

Rise time t

Delay t Hold time t

Setup time t

Hold time t

dtr

htr

S Transmitters and Receivers

Transmitter Receiver

Min Max Min Max Min Max Min Max

–––Tr–––

Master Mode: Clock generated by transmitter or receiver

0.35T

– – – 0.35T

Slave Mode: Clock accepted by transmitter or receiver

–0.35Ttr–––0.35Ttr––

– – 0.15T

– – – 0.8T – – – – [17] 0–––––––[16]

––––0.2Ttr– – – [18]

Transm itte r

Receiver

NotesLower LImit Upper Limit Lower Limit Upper Limit

[15]

– – – [16]

[15]

– – – – [16]

Notes

15. The system clock period T must be greater than T

16. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t respect to T.

17. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35T

18. Because the delay (t t

which means t

tRC is not more than t

19. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time.

20. The data setup and hold time must not be less than the specified receiver setup and hold time.

dtr

becomes zero or negative. Therefore, the transmitter has to guarantee that t

htr

, any clock that meets the requirements can be used.

) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding

, where t

RCmax

and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.

is greater than or equal to zero, so long as the clock rise-time

is not less than 0.15Ttr.

htr

and tLC are specified with

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Figure 18. I2S Transmitter Timing

Figure 19. I

S Receiver Timing

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Environmental Specifications

Note

21. This does not apply to the RF pins (ANT).

Environmental Compliance

This Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBT-2X30XX-02 module is certified under the following RF certification standards:

■ FCC: WAP3063

■ ISED: 7922A-3063

■ MIC: TBD

■ CE

Safety Certification

The CYBT-2X30XX-02 module complies with the following safety regulations:

■ Underwriters Laboratories, Inc. (UL): Filing E331901

■ CSA

■ TUV

Environmental Conditions

Ta bl e 3 0 describes the operating and storage conditions for the Cypress Bluetooth module.

Table 30. Environmental Conditions for CYBT-2X30XX-02

Description Minimum Specification Maximum Specification

Operating temperature −30 °C 85 °C Operating humidity (relative, non-condensation) 5% 85% Thermal ramp rate Storage temperature Storage temperature and humidity

ESD: Module integrated into system Components

[21]

– 10 °C/minute

–40 °C 85 °C

– 85 °C at 85%

–

15 kV Air

2.0 kV Contact

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

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Regulatory Information

FCC

The device CYBT-2X30XX-02 complies with Part 15 of the FCC Rules.

(1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause

Operation is subject to the following two conditions:

undesired operation.

The device meets the requir

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■

Reorient or relocate the receiving antenna.

■

Increase the separation between the equipment and receiver.

■

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help

■

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3063.

In any case the end product must be labeled exterior with “Contains FCC ID: WAP3063”.

ANTENNA WARNING: This device is tested with a standard SMA connector and with the antenna listed in Tab le 7 on page 13. When integrated in the OEMs

product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna not in Tab le 7 on page 13 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

ements for modular transmitter

approval as detailed in FCC public Notice DA00-1407.

RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna

in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.

The radiated output power of CYBT-2X30XX-02 with the integrated PCB trace antenna (FCC ID: WAP3063) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-2X30XX-02 in such a manner that minimizes the potential for human contact during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.

Antenna must be placed or installed to make safety minimum distance of 20cm from human body.

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ISED

Innovation, Science and Economic Development (ISED) Canada Certification

CYBT-2X30XX-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-3063 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antenna listed in Table 7 on page 13, having a maximum gain of -0.5 dBi. Antennas not included in Ta bl e 7 on page 13 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

ISED NOTICE: The device CYBT-2X30XX-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the

requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

L'appareil CYBT-2X30XX-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable.

ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).

Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3063. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3063".

Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend un étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3063. En tout cas, le produit final doit être étiqueté dans son extérieur avec “Contient IC: 7922A-3063”.

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European Declaration of Conformity

Model Name: EZ-BT WICED Module

Part Number: CYBT-273063-02, CYBT-263064-02, CYBT-263065-02

Manufactured by Cyp ress Semiconductor.

TBD

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-2X30XX-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:

All versions of the CYBT-2X30XX-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

MIC Japan

CYBT-2X30XX-02 is certified as a module with certification number TBD. End products that integrate CYBT-2X30XX-02 do not need additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

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Packaging

Table 31. Solder Reflow Peak Temperature

Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles

CYBT-273063-02 35-pad SMT 260 °C 30 seconds 2 CYBT-263064-02 35-pad SMT 260 °C 30 seconds 2 CYBT-263065-02 35-pad SMT 260 °C 30 seconds 2

Table 32. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number Package MSL

CYBT-273063-02 35-pad SMT MSL 3 CYBT-263064-02 35-pad SMT MSL 3 CYBT-263065-02 35-pad SMT MSL 3

The CYBT-2X30XX-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-2X30XX-02.

Figure 20. CYBT-2X30XX-02 Tape Dimensions

Figure 21 details the orientation of the CYBT-2X30XX-02 in the tape as well as the direction for unreeling.

Figure 21. Component Orientation in Tape and Unreeling Direction

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Figure 22 details reel dimensions used for the CYBT-2X30XX-02.

Top View (Seen from Top)

Figure 22. Reel Dimensions

The CYBT-2X30XX-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-2X30XX-02 is detailed in Figure 23.

Figure 23. CYBT-2X30XX-02 Center of Mass

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Ordering Information

Ta bl e 3 3 lists the CYBT-2X30XX-02 part number and features. Tab le 3 3 also lists the target program for the respective module

ordering codes. Tab l e 34 lists the reel shipment quantities for the CYBT-2X30XX-02.

Table 33. Ordering Information

Ordering Part

Number

CYBT-273063-02 96 256 176 Yes Yes Yes Yes Yes 6 14 20 35-SMT Tape and Reel CYBT-263064-02 96 256 176 Yes Yes Yes Yes Yes 6 14 20 35-SMT Tape and Reel CYBT-263065-02 96 256 176 Yes Yes Yes Yes Yes 6 14 20 35-SMT Tape and Reel

Table 34. Tape and Reel Package Quantity and Minimum Order Amount

Description Minimum Reel Quantity Maximum Reel Quantity Comments

Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI)

The CYBT-2X30XX-02 is offered in tape and reel packaging. The CYBT-2X30XX-02 ships in a reel size of 500 units.

For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.

Max CPU

Speed (MHz)

Flash

Size (KB)

RAM

Size

UART I2C SPI I2S PCM PWM

(KB)

500 500 Ships in 500 unit reel quantities. 500 – – 500 – –

ADC

Inputs

GPIOs Package Packaging

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134 U.S. Cypress Headquarter Contact Info (408) 943-2600 Cypress website address www.cypress.com

Document Number: 002-29354 Rev. ** Page 42 of 45

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Acronyms Document Conventions

Table 35. Acronyms Used in this Document

Acronym Description

BLE Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group CE European Conformity CSA Canadian Standards Association EMI electromagnetic interference ESD electrostatic discharge FCC Federal Communications Commission GPIO general-purpose input/output

ISED

IDE integrated design environment KC Korea Certification

MIC

PCB printed circuit board RX receive QDID qualification design ID

SMT

TCPWM timer, counter, pulse width modulator (PWM)

TUV

TX transmit

Innovation, Science and Economic Development (Canada)

Ministry of Internal Affairs and Communications (Japan)

surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs

Germany: Technischer Überwachungs-Verein (Technical Inspection Association)

Units of Measure

Table 36. Units of Measure

Symbol Unit of Measure

°C degree Celsius dB decibel dBi decibels relative to isotropic dBm decibel-milliwatts kV kilovolt mA milliamperes mm millimeters mV millivolt

μA microamperes μm micrometers

MHz megahertz GHz gigahertz Vvolt

Document Number: 002-29354 Rev. ** Page 43 of 45

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

Document History Page

Document Title: CYBT-273063-02, CYBT-263064-02, CYBT-263065-02, EZ-BT™ Module Document Number: 002-29354

Revision ECN

** 6761681 12/26/2019 Preliminary datasheet for CYBT-273063-02, CYBT-263064-02, and CYBT-263065-02

Submission

Date

Description of Change

module.

Document Number: 002-29354 Rev. ** Page 44 of 45

PRELIMINARY

CYBT-273063-02 CYBT-263064-02 CYBT-263065-02

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© Cypress Semiconductor Corporation, 2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Softw are provided in sou rce code form, t o modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-29354 Rev. ** Revised December 26, 2019 Page 45 of 45

Cypress Semiconductor 3063 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Module Description

RF Characteristics

Functional Capabilities

Benefits

Power Consumption

More Information

References

Development Environments

Technical Support

Contents

Overview

Functional Block Diagram

Module Description

Module Dimensions and Drawing

Pad Connection Interface

Recommended Host PCB Layout

Module Connections

Connections and Optional External Components

Power Connections (VDD)

External Reset (XRES)

HCI UART Connections

External Component Recommendation

Power Supply Circuitry

Antenna Matching Network Requirements

Critical Components List

Antenna Design

Qualified Antenna for CYBT-263064-02 and CYBT-263065-02

Bluetooth Baseband Core

Power Management Unit

Integrated Radio Transceiver

Transmitter Path

Digital Modulator

Power Amplifier

Receiver Path

Digital Demodulator and Bit Synchronizer

Receiver Signal Strength Indicator

Local Oscillator

Microcontroller Unit

External Reset

32-kHz Crystal Oscillator

Power Modes

Firmware

Watchdog

Lockout Functionality

True Random Number Generator

Peripherals and Communication Interfaces

HCI UART Interface

Peripheral UART Interface

Serial Peripheral Interface

ADC Port

GPIO Port

PDM Microphone

I2S Interface

PCM Interface

Slot Mapping

Frame Synchronization

Data Formatting

Electrical Characteristics

Current Consumption

Silicon Core Buck Regulator

Digital LDO

RF LDO

Digital I/O Characteristics

ADC Characteristics

Chipset RF Specifications

Timing and AC Characteristics

UART Timing

SPI Timing

I2C Compatible Interface Timing

I2S Interface Timing

Environmental Specifications

Environmental Compliance

RF Certification

Safety Certification

Environmental Conditions