Cypress Semiconductor 3058 Users Manual

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

EZ-BT Module

CYBT-223058-02, EZ-BT Module

General Description

The CYBT-2x305x-02 is a dual-mode Bluetooth BR/EDR and Low Energy (BLE) wireless module solution. The CYBT-223058-02
includes an onboard crystal oscillator, passive components, and the Cypress CYW20819 silicon device. The CYBT-253059-02
includes an onboard crystal oscillator, passive components, and the Cypress CYW20820 silicon device.

The CYBT-2x305x-02 supports a number of peripheral functions (ADC, PWM), as well as multiple serial communication protocols
(UART, SPI, I
× 1.70 mm module form-factor.

The CYBT-2x305x-02 includes 256 KB of on-chip flash memory and is designed for standalone operation. The CYBT-2x305x-02 uses
an integrated power amplifier to achieve Class I or Class II output power capability.

The CYBT-2x305x-02 includes an integrated chip antenna, is qualified by Bluetooth SIG, and includes regulatory certification approval
for FCC, ISED, MIC, and CE.

2

C, I2S/PCM). The CYBT-2x305x-02 includes a royalty-free stack compatible with Bluetooth 5.0 in a small 11.0 ×11.00

Module Description

■ Module size: 11.00 mm × 11.00 mm × 1.70 mm

■ Complies with Bluetooth Core Specification version 5.0 and

includes support for BR, EDR 2/3 Mbps, eSCO, BLE, LE
2 Mbps, as well as Bluetooth Mesh.

❐ QDID: TBD
❐ Declaration ID: TBD

■ Certified to FCC, ISED, MIC, and CE standards

■ 256-KB on-chip Flash, 176-KB on-chip RAM

■ Industrial temperature range: –30 °C to +85 °C

■ Integrated Arm

®

Cortex®-M4 microprocessor core with

floating point unit (FPU)

RF Characteristics

■ Maximum TX output power: +4.0 dBm (CYBT-223058-02);

+10.5 dBm (CYBT-253059-02)

■ BLE RX Receive Sensitivity: –94.5 dBm

Power Consumption

■ TX current consumption
❐ BLE silicon: 5.8 mA (radio only, 4 dBm) (CYBT-223058-02);

22 mA (radio only, 10.5 dBm) (CYBT-253059-02)

■ RX current consumption
❐ Bluetooth silicon: 5.9 mA (radio only)

■ Cypress CYW20819/20 silicon low power mode support
❐ PDS: 16.5 µA with 176 KB RAM retention
❐ ePDS: 8.7 µA

❐ HIDOFF (wake on external or timed interrupt): 1.75 µA

Functional Capabilities

■ Up to 22 GPIOs

2

■ I

C, I2S, UART, and PCM interfaces

■ Two Quad-SPI interfaces

■ Auxiliary ADC with up to 15 analog channels

■ Programmable key scan 20 × 8 matrix

■ General-purpose timers and six PWMs

■ Real-time clock (RTC) and watchdog timers (WDT)

■ Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR)

Support

■ BLE protocol stack supporting generic access profile (GAP)

Central, Peripheral, Observer, or Broadcaster roles

Benefits

CYBT-2x305x-02 is fully integrated and certified solution that
provides all necessary components required to operate
Bluetooth communication standards.

■ Proven hardware design ready to use

■ Ultra-flexible supermux I/O design allows maximum flexibility

for GPIO function assignment

■ Over-the-air update capable for development or field updates

■ Bluetooth SIG qualified.

■ ModusToolbox™ provides an easy-to-use integrated design

environment (IDE) to configure, develop, program, and test
your Bluetooth application

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-29172 Rev. ** Revised December 11, 2019

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.

References

■ Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap

■ Development Kits:
❐ CYBT-223058-EVAL, CYBT-223058-02 Evaluation Board
❐ CYBT-253059-EVAL, CYBT-253059-02 Evaluation Board

■ Test and Debug Tools:
❐ CYSmart, Bluetooth

❐ CYSmart Mobile, Bluetooth

®

LE Test and Debug Tool (Windows)

®

LE Test and Debug Tool

(Android/iOS Mobile App)

❐ Bluetooth Mesh Helper Applications, Bluetooth Mesh Helper

applications for all key platforms - Android, iOS, and Windows

■ Application Notes
❐ Mesh Application Note, Getting Started with Bluetooth Mesh

■ Knowledge Base Article
❐ KBA97095 - EZ-BLE™ Module Placement

❐ RF Regulatory Certifications for CYBT-2x305x-02 EZ-BT

WICED Modules (TBD)

❐ KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐ KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
❐ KBA223428 - Programming an EZ-BT WICED Module
❐ KBA225450 - Putting 2073x, 2070x, and 20719 Based

Devices or Modules in HCI Mode

Development Environments

ModusToolbox Integrated Development Environment (IDE)

ModusToolbox simplifies development for IoT designers. It delivers easy-to-use tools and a familiar microcontroller (MCU) integrated

development environment (IDE) for Windows
wireless connectivity libraries, power analysis, application-specific configurators for Bluetooth

®

, macOS®, and Linux®. It provides a sophisticated environment for system setup,

®

Low Energy (BLE), CapSense®, as

well as other peripherals.
In addition, code examples, documentation, technical support and community forums are available to help your IoT development

process along. These tools and features enable an IoT designer to develop innovative IoT applications efficiently and with ease.

Technical Support

■ Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share, and engage with both Cypress experts and other embedded engineers
around the world.

■ Frequently Asked Questions (FAQs): Learn more about our Bluetooth ecosystem.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: [phone]. Select option 2 at the prompt.

Document Number: 002-29172 Rev. ** Page 2 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Contents

Overview ............................................................................4

Functional Block Diagram ...........................................4

Module Description ......................................................4

Pad Connection Interface ................................................6

Recommended Host PCB Layout ...................................7

Module Connections ........................................................9

Connections and Optional External Components ....... 11

Power Connections (VDD) ........................................11

External Reset (XRES) ..............................................11

HCI UART Connections ............................................11

External Component Recommendation .................... 11

Critical Components List ............................................... 13

Antenna Design ..............................................................13

Bluetooth Baseband Core ............................................. 13

Power Management Unit ................................................14

Integrated Radio Transceiver ........................................15

Transmitter Path ........................................................15

Receiver Path ............................................................15

Local Oscillator ..........................................................15

Microcontroller Unit .......................................................16

External Reset ...........................................................16

32-kHz Crystal Oscillator ...........................................16

Power Modes ............................................................17

Firmware ...................................................................17

Watchdog ..................................................................17

Lockout Functionality .................................................17

True Random Number Generator .............................17

Peripherals and Communication Interfaces ................ 18

I2C .............................................................................18

HCI UART Interface ..................................................18

Peripheral UART Interface ........................................18

Serial Peripheral Interface .........................................18

Keyboard Scanner ..................................................... 18

Mouse Quadrature Signal Decoder ...........................18

ADC Port ................................................................... 19

GPIO Port ..................................................................19

PWM .......................................................................... 20

PDM Microphone .......................................................20

I2S Interface ..............................................................21

PCM Interface ...........................................................21

Electrical Characteristics ...............................................22

Current Consumption ................................................23

Silicon Core Buck Regulator ..................................... 23

Digital LDO ................................................................24

RF LDO ..................................................................... 24

PA LDO (CYBT-253059-02 only) .............................. 25

Digital I/O Characteristics ..........................................26

ADC Characteristics .................................................. 26

Chipset RF Specifications .............................................28

Timing and AC Characteristics ..................................... 31

UART Timing ............................................................. 31

SPI Timing ................................................................. 32

I2C Compatible Interface Timing ...............................33

I2S Interface Timing ..................................................34

Environmental Specifications .......................................36

Environmental Compliance .......................................36

RF Certification ..........................................................36

Safety Certification ....................................................36

Environmental Conditions .........................................36

ESD and EMI Protection ........................................... 36

Regulatory Information .................................................. 37

FCC ...........................................................................37

ISED ..........................................................................38

European Declaration of Conformity ......................... 39

MIC Japan .................................................................39

Packaging ........................................................................ 40

Ordering Information ......................................................42

Acronyms ........................................................................43

Document Conventions .................................................43

Units of Measure .......................................................43

Document History Page ................................................. 44

Sales, Solutions, and Legal Information ...................... 45

Worldwide Sales and Design Support ....................... 45

Products .................................................................... 45

PSoC® Solutions ......................................................45

Cypress Developer Community .................................45

Technical Support ..................................................... 45

Document Number: 002-29172 Rev. ** Page 3 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Overview

CYW20819/20

Silicon Device

Functional Block Diagram

Figure 1 illustrates the CYBT-2x305x-02 functional block diagram.

Figure 1. Functional Block Diagram

Note: GPIO pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Tab l e 5 in the Module Connections section.
Note: The total number of GPIOs available on the CYBT-2x305x-02 is 22. Peripheral and/or Serial communication functions are implemented using these 22 GPIOs.

Module Description

The CYBT-2x305x-02 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. The CYBT-2x305x-02 will be held within
the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions

PCB thickness Height (H) 0.50 ± 0.10 mm
Shield height Height (H) 1.20 mm typical
Maximum component height Height (H) 0.80 mm typical
Total module thickness (bottom of module to top of shield) Height (H) 1.70 mm typical

See Figure 2 for the mechanical reference drawing for CYBT-2x305x-02.

Length (X) 11.00 ± 0.15 mm

Width (Y) 11.00 ± 0.15 mm

Length (X) 6.58 mm

Width (Y) 2.50 mm

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CYBT-223058-02
CYBT-253059-02

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (Seen from Top)

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on the
recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

Document Number: 002-29172 Rev. ** Page 5 of 45

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CYBT-223058-02
CYBT-253059-02

Pad Connection Interface

Solder Pad Connections (Seen from Bottom)

Optional Host PCB Keep Out Area
Around PCB Antenna
(Seen from Bottom)

As shown in the bottom view of Figure 2 on page 5, the CYBT-2x305x-02 has 35 connections to a host board via solder pads (SP).

Ta bl e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-2x305x-02 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 35 Solder Pad 1.06 mm 0.41 mm 0.76 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB antenna
located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to

AN96841 for module placement best practices.

3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB antenna may
contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the
host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).

Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-2x305x-02 PCB Antenna

Document Number: 002-29172 Rev. ** Page 6 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure 7, and Ta bl e 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBT-2x305x-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.06 mm (0.53 mm from center of the pad on
either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-2x305x-02 Host Layout (Dimensioned) Figure 6. CYBT-2x305x-02 Host Layout (Relative to Origin)

Document Number: 002-29172 Rev. ** Page 7 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Ta bl e 3 provides the center location for each solder pad on the CYBT-2x305x-02. All dimensions are referenced to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure 7 for the location of each module solder pad.

Table 3. Module Solder Pad Location

Solder Pad

(Center of Pad)

1 (0.28, 0.51) (11.02, 20.08)
2 (0.28, 1.27) (11.02, 50.00)
3 (0.28, 2.03) (11.02, 79.92)
4 (0.28, 2.79) (11.02, 109.84)
5 (0.28, 3.56) (11.02, 140.16)
6 (0.28, 4.32) (11.02, 170.08)
7 (0.28, 5.08) (11.02, 200.00)
8 (0.28, 5.84) (11.02, 229.92)

9 (0.28, 6.60) (11.02, 259.84)
10 (0.28, 7.37) (11.02, 290.16)
11 (0.28, 8.13) (11.02, 320.08)
12 (0.28, 8.89) (11.02, 350.00)
13 (0.28, 9.65) (11.02, 379.92)
14 (0.93, 10.72) (36.61, 422.05)
15 (1.69, 10.72) (66.54, 422.05)
16 (2.45, 10.72) (96.46, 422.05)
17 (3.21, 10.72) (126.38, 422.05)
18 (3.98, 10.72) (156.69, 422.05)
19 (4.74, 10.72) (186.61, 422.05)
20 (5.50, 10.72) (216.54, 422.05)
21 (6.26, 10.72) (246.46, 422.05)
22 (7.02, 10.72) (276.38, 422.05)
23 (7.79, 10.72) (306.69, 422.05)
24 (8.55, 10.72) (336.61, 422.05)
25 (9.31, 10.72) (366.53, 422.05)
26 (10.07, 10.72) (396.46, 422.05)
27 (10.72, 9.65) (422.05, 379.92)
28 (10.72, 8.89) (422.05, 350.00)
29 (10.72, 8.13) (422.05, 320.08)
30 (10.72, 7.37) (422.05, 290.16)
31 (10.72, 6.60) (422.05, 259.84)
32 (10.72, 5.84) (422.05, 229.92)
33 (10.72, 5.08) (422.05, 200.00)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

Table 3. Module Solder Pad Location (continued)

Solder Pad

(Center of Pad)

34 (10.72, 4.32) (422.05, 170.08)
35 (10.72, 3.56) (422.05, 140.16)

Figure 7. Solder Pad Reference Location

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

Document Number: 002-29172 Rev. ** Page 8 of 45

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CYBT-223058-02
CYBT-253059-02

Module Connections

Ta bl e 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available

on the CYBT-2x305x-02 can be configured to any of the input or output functions listed in Tab le 5 . Table 4 specifies any function that
is required to be used on a specific solder pad, and also identifies SuperMux capable GPIOs that can be configured using the
ModusToolbox device configurator.

Table 4. CYBT-2x305x-02 Solder Pad Connection Definitions

Pad Pad Name Silicon Pin Name XTALI/O ADC GPIO SuperMux Capable

1 GND GND Ground

2 VDD VDDIO Power Supply Input (1.71V ~ 3.63V)

3P32 P32 - IN7 ✓✓ see Table 5

4 XRES RST_N External Reset (Active Low)

5P27 P27 - - ✓

6P37 P37 - IN2 ✓

7 P29 P29 - IN10 ✓

8P26 P26 - - ✓

9P0 P0 - IN29 ✓

10 P1 P1 - IN28 ✓

11 P 10 P1 0 - IN 25 ✓

12 P13 P13 - IN22 ✓

13 P12 P12 - IN23 ✓

14 P11 P11 - IN24 ✓

15 P9 P9 - IN26 ✓

16 P14 P14 - IN21 ✓

17 P17 P17 - IN18 ✓

18 P5 P5 - - ✓

19 P2 P2 - - ✓

20 P3 P3 - - ✓

21 XTALI_32K XTALI_32K

22 XTALO_32K XTALO_32K

23 P8 P8 - IN27 ✓

25 P6 P6 - - ✓

26 GND GND Ground

27 P4 P4 - - ✓

28 P28 P28 - IN11 ✓

29 UART_CTS_N UART_CTS_N UART (HCI UART) Clear To Send Input Only

30 UART_RTS_N UART_RTS_N UART (HCI UART) Request To Send Output Only

31 HOST_WAKE HOST_WAKE

32 UART_RXD UART_RXD UART (HCI UART) Receive Data Only

33 UART_TXD UART_TXD UART (HCI UART) Transmit Data Only

34 DEV_WAKE DEV_WAKE A signal from the host to the CYBT-2x305x-02 module indicating that the host requires attention.

35 GND GND Ground

Note

2. The CYBT-2x305x-02 can configure GPIO connections to any Input/Output function described in Tab le 5 using the ModusToolbox Device Configurator.

External Oscillator Input

(32KHz)

External Oscillator

Output (32KHz)

A signal from the CYBT-2x305x-02 module to the host indicating that the Bluetooth device requires

-- -

-- -

attention.

✓ see Table 5

✓ see Table 524 P15 P15 - IN20 ✓

✓ see Table 5

[2]

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CYBT-253059-02

Ta bl e 5 details the available Input and Output functions that are configurable to any solder pad (in this table) that are marked as

SuperMux capable.

Table 5. GPIO SuperMux Input and Output Functions

Function Input or Output Function Type

SPI 1 Input/Output

SPI 2 Input/Output

Input Serial Communication Input

PUART

Output Serial Communication Output

2

C Input/Output

I

PCM In Input Audio Input Communication 3

PCM Out Output

2

S In Input Audio Input Communication 3

I

2

S Out Output

I

PDM Input Microphone 1 ~ 2

PWM Output Pulse Width Modulator 1 ~ 6

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

Audio Output

Communication

Audio Output

Communication

GPIOs

Required

4 ~ 7

4 ~ 7

4

2

3

3

Function Connection Description

SPI 1 Clock

SPI 1 Chip Select

SPI 1 MOSI

SPI 1 MISO

SPI 1 I/O 2 (Quad SPI)

SPI 1 I/O 3 (Quad SPI)

SPI 1 Interrupt

SPI 2 Clock

SPI 2 Chip Select

SPI 2 MOSI

SPI 2 MISO

SPI 2 I/O 2 (Quad SPI)

SPI 2 I/O 3 (Quad SPI)

SPI 2 Interrupt

Peripheral UART RX

Peripheral UART CTS

Peripheral UART TX

Peripheral UART RTS

I2C Clock

I2C Data

PCM Input

PCM Clock

PCM Sync

PCM Output

PCM Clock

PCM Sync

I2S DI, Data Input

I2S WS, Word Select

I2S Clock

I2S DO, Data Output

I2S WS, Word Select

I2S Clock

PDM Input Channel 1

PDM Input Channel 2

PWM Channel 0

PWM Channel 1

PWM Channel 2

PWM Channel 3

PWM Channel 4

PWM Channel 5

Document Number: 002-29172 Rev. ** Page 10 of 45

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CYBT-253059-02

Connections and Optional External Components

Power Connections (VDD)

The CYBT-223058-02 contains one power supply connection, VDD. VDD accepts a supply input of 1.71 V to 3.63 V. Table 12 provides
this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Ta b le 1 2 . The CYBT-253059-02
contains one power supply connection, VDD. VDD accepts a supply input of 2.6 V to 3.63 V. Table 12 provides this specification. The
maximum power supply ripple for this power connection is 100 mV, as shown in Table 12.

External Reset (XRES)

The CYBT-2x305x-02 has an integrated power-on reset circuit which completely resets all circuits to a known power-on state. This
action can also be invoked by an external reset signal, forcing it into a power-on reset state. XRES is an active-low input signal on
the CYBT-2x305x-02 module (solder pad 3). The CYBT-2x305x-02 does not require external pull-up resistors on the XRES input.
Refer to Figure 10 on page 16 for Power On and XRES operation and timing requirements during power on events.

HCI UART Connections

The recommendations in this section apply to the HCI UART (Solder Pads 29, 30, 32, and 33). For full UART functionality, all UART
signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired
or capable, then the following connection considerations should be followed for UART RTS and CTS:

■ UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.

■ UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the

module.

External Component Recommendation

Power Supply Circuitry

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to the
module pad connection.

If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).

Figure 8 illustrates the CYBT-2x305x-02 schematic.

Document Number: 002-29172 Rev. ** Page 11 of 45

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CYBT-253059-02

Figure 8. CYBT-2x305x-02 Schematic Diagram

P32

XRES

P27

P37

P29

P26

P0

P1

P13

P10

P12

P11

P9

P14

P17

P5

P2

P3

XTALI_32K

XTALO_32K

P8

P15

P6

P4

P28

UART_CTS_N

UART_RTS_N

HOST_WAKE

UART_RXD

UART_TXD

DEV_WAKE

VDD

Pin 1 is For Radiator Electrode
Pin 3 is For Feeding

Filter

L1 2.7nH,0201

C5

1.8pF

P0
P1
P2
P3
P4
P5
P6
P8
P9
P10
P11
P12
P13
P14
P15
P17
P26
P27
P28
P29
P32
P37

MODULE PAD ASSIGNMENT

XRES

UART_CTS_N
UART_RTS_N
UART_RXD
UART_TXD

HOST_WAKE

DEV_WAKE

LC2

5.6nH,0201

G1

C7
E6
D7
D6

D8

E7

A8

G2

1 3

C1

0.1uF

RST_N

UART_CTS_N
UART_RTS_N
UART_RXD
UART_TXD

HOST_WAKE

DEV_WAKE

ADC_AVSS

JTAG_SEL

A1

2

Antenna

C2

0.1uF

D1

VDDO2

Antenna Matching

LC1 5.6nH,0201

LC4

DNI,0201

DIGLDO_OUTVDD

C3

0.1uF

B8

VDDO1

VSSC1

VSSC3

VSSC2

E3

C6

C3

C8

VDDC1

E1

VDDC2

P10
P11
P12
P13
P14
P15
P17
P26
P27
P28
P29
P32
P37

P0
P1
P2
P3
P4
P5
P6
P8
P9

LC3

1.0pF,0201

C4

0.1uF

U1A
CYW20820_B62

D2
C1
B5
A5
C5
B4
A4
A6
A2
C2
B2
A1
B1
B3
B6
A3
D4
F1
C4
D3
F2
E2

VDD

C8

4.7uF,0402

C7

10uF,0402

H3

H2

G3

SR_PVDD

PMU_AVDD

BT_RF

H6

26

GND

P4

P28

UART_CTS_N

UART_RTS_N

HOST_WAKE

UART_RXD

UART_TXD

DEV_WAKE

GND

E4

P6

P15

RF

PMU_LDO_ONLY_STRAP

P8

P3

XTALO_32K

XTALI_32K

P2

P5

C6

1.8pF

27

35

Castellated solder pad

DIGLDO_OUT

L2

2.2uH,0603

C9

2.2uF,0201

E5

SR_VLX

RFLDO_DIGLDO_VDDIN

14

P9

P14

P17

P11

P12

13

P13

P10

P1

P0

P26

P29

P37

P27

XRES

P32

VDD

GND

1

(BOTTOM VIEW)

RFLDO_OUTCBUCK_OUT

C10

2.2uF,0201

G4

DIGLDO_VDDOUT

PMU_AVSS

F4

F7

PAVDD

PALDO_OUT

VDD

C17

C18

0.1uF

2.2uF,0201

C11

0.1uF

G5

F5

H4

RFLDO_VDDOUT

NC_0 (PALDO_VDDIN)

PAVSS

PLLVSS

IFVSS

VCOVSSG7SR_PVSS

H1

H7

G6

RFLDO_OUT

For CYBT-223058-02, install R1;
For CYBT-253059-02, install R2.

NC_1 (PALDO_VDDOUT)

PAVDD

R1

0ohm,0201

H5

PAVDD

0ohm,0201

XTALI_32K

B7

XTALI_32K

PALDO_OUT

R2

FB1 600@100M

C12

0.1uF

F6

IFVDD

XTALO_32K

A7

XTALO_32K

0.1uF

G8

C13

PLLVDD

RFLDO_OUT

FB2
600@100M

H8

VCOVDD

XTALO

XTALI

C14

10pF,0201

U1B
CYW20820_B62

E8

F8

C15

12pF,0201

Y1

24MHz

C16

12pF,0201

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

TP20

TP21

TP22

TP23

TP24

TP25

TP26

TP27

TP28

TP29

TP30

TP31

TP32

TP33

TP34

TP35

Document Number: 002-29172 Rev. ** Page 12 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Critical Components List

Ta bl e 6 details the critical components used in the CYBT-2x305x-02 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 62-pin QFN Bluetooth Silicon Device - CYW20819/20
Crystal Y1 24.000 MHz, 8 PF
Chip Antenna A1 Antenna, 2.4 GHz

Antenna Design

Ta bl e 7 details the chip antenna used in the CYBT-2x305x-02 module.

Table 7. PCB Antenna Specifications

Item Description

Frequency Range 2400 – 2500 MHz
Peak Gain -2.5 dBi typical
Return Loss 10 dB minimum

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The
BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities
including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host
controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward
error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and
data whitening/dewhitening.

Table 8. Bluetooth Features

Bluetooth 1.0 Bluetooth 1.2 Bluetooth 2.0

Basic Rate Interlaced Scans EDR 2 Mbps and 3 Mbps
SCO Adaptive Frequency Hopping –
Paging and Inquiry eSCO –
Page and Inquiry Scan – –
Sniff – –

Bluetooth 2.1 Bluetooth 3.0 Bluetooth 4.0

Secure Simple Pairing Unicast Connectionless Data Bluetooth Low Energy
Enhanced Inquiry Response Enhanced Power Control –
Sniff Subrating eSCO –

Bluetooth 4.1 Bluetooth 4.2 Bluetooth 5.0

Low Duty Cycle Advertising Data Packet Length Extension LE 2 Mbps
Dual Mode LE Secure Connection Slot Availability Mask
LE Link Layer Topology Link Layer Privacy High Duty Cycle Advertising

Document Number: 002-29172 Rev. ** Page 13 of 45

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CYBT-253059-02

Power Management Unit

Figure 9 shows the CYW20819/20 power management unit (PMU) block diagram. The CYW20819/20 includes an integrated buck

regulator, a digital LDO for the digital core, a PA LDO for internal PA (CYW20820 only), and an RF LDO for the Radio. The PMU also
includes a brownout detector which places the part in shutdown when input voltage is below a certain threshold.

Figure 9. Default Usage Mode

Document Number: 002-29172 Rev. ** Page 14 of 45

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CYBT-223058-02
CYBT-253059-02

Integrated Radio Transceiver

The CYBT-2x305x-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally
available 2.4 GHz unlicensed ISM band.

Transmitter Path

CYBT-2x305x-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYBT-2x305x-02 has an integrated power amplifier (PA) that can transmit up to +10.5 dBm for class 1 operation.

Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in
the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-2x305x-02 to be
used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYBT-2x305x-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the
controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether
the transmitter should increase or decrease its output power.

Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the band. The CYBT-2x305x-02 uses an internal
loop filter.

Document Number: 002-29172 Rev. ** Page 15 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Microcontroller Unit

The CYBT-2x305x-02 includes a Cortex-M4 processor with 1 MB of program ROM, 176 KB of RAM, and 256 KB of flash. The CM4
has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code execution from flash at
near maximum speed and low power consumption.

The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack
layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.

External Reset

Figure 10 shows power on and reset timing of the CYBT-2x305x-02. After VBAT is applied and reset is inactive, the internal buck turns

on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows the digital core to come out of reset.
As shown in the figure, external reset can be applied at any time subsequent to power up.

Figure 10. Reset Timing

32-kHz Crystal Oscillator

The CYBT-2x305x-02 includes connections for an external 32-kHz oscillator to provide accurate timing during low power operations.

Figure 11 shows the 32-kHz XTAL oscillator with external components and Ta bl e 9 lists the oscillator characteristics. This oscillator

can be operated with a 32 kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must
have an accuracy of ±250 ppm or better per the BT spec over temperature and including aging. The external component values should
be: R1 = 10 MΩ and C1 = C2 = 6 pF. The values of C1 and C2 are used to fine-tune the oscillator. A XTAL meeting the C1 and C2
values should be used.

Figure 11. 32 kHz Oscillator Block Diagram

Document Number: 002-29172 Rev. ** Page 16 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Table 9. XTAL Oscillator Characteristics

Parameter Symbol Conditions Min Typ Max Unit

Output frequency F

oscout

– – 32.768 – kHz
Frequency tolerance – Over temperature and aging – – 250 ppm
XTAL drive level P
XTAL series resistance R
XTAL shunt capacitance C
Load capacitance C

drv

series

shunt

l

For crystal selection – – 0.5 µW
For crystal selection – – 70 kΩ
For crystal selection – – 2.2 pF
For crystal selection – 6 – pF

Power Modes

The CYBT-2x305x-02 support the following HW power modes are supported:

■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.

■ Idle mode - CPU is paused.

■ Sleep mode - All system clocks are idle except for the LPO. The device can wake up either after a programmed period of time has

expired or if an external event is received via one of the GPIOs. In Sleep mode, the CPU is in WFI (wait for interrupt) and the HCLK
is not running. The PMU determines if the other clocks can be turned off and does accordingly. The state of the device is retained,
the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.

■ Power Down Sleep (PDS) mode - Radio powered down and digital core mostly powered down except for RAM, registers, and

some core logic. CYBT-2x305x-02 can wake up either after a programmed period of time has expired or if an external event is
received via one of the GPIO.

■ Extended PDS (ePDS) - This is an extension of PDS Mode. In this mode, only the main RAM and ePDS control circuitry retains

power. As in other modes, the CYBT-2x305x-02 can wake up either after a programmed period or upon receiving an external event.

■ HID-OFF (Deep Sleep) mode - Core, radio, and regulators powered down. Only the GPIO domain is powered. In this mode, the

CYBT-2x305x-02 can be woken up either by an external event on one of the GPIOs or after a programmed period of time has
expired. The lowest power option for HID-Off mode is to wake by external event, allowing all clocking sources to remain off. If a
timed wake HID-Off state is desired, this is accomplished by powering the external or internal LPO. Current consumption will increase
slightly in timed wake HID-Off mode to account for the LPO power. After wakeup, the part will go through full FW initialization although
it will retain enough information to determine that it came out of HID-Off and the event that caused the wake up.

Transition between power modes is handled by the on-chip firmware with host/application involvement. In general, ePDS is the most
power-efficient mode for active use cases. HID-Off is preferable for non-connectable beacon use cases (long advertisement intervals).

Firmware

The CYBT-2x305x-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all
on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes
drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power
modes. The ROM also supports OTA firmware update.

The CYBT-2x305x-02 is fully supported by the Cypress ModusToolbox IDE. ModusToolbox releases provide latest ROM patches,
drivers, and sample applications allowing customized applications using the CYBT-2x305x-02 to be built quickly and efficiently.

Watchdog

CYBT-2x305x-02 includes an onboard watchdog with a period of approximately 4 seconds. The watchdog generates an interrupt to
the Firmware after 2 seconds of inactivity and resets the device after 4 seconds.

Lockout Functionality

The CYBT-2x305x-02 powers up with SWD access to flash and RAM is disabled. After reset, FW checks OCF for the presence of a
security lockout field. If present, FW leaves SWD Flash and RAM access disabled and also blocks any HCI commands from reading
the raw contents of the RAM or Flash. This provides an effective way of protection against tampering, dumping, probing, or reverse
engineering of the user application stored in the on-chip flash. The only firmware upgrade path in this scenario is secure over-the-air
(OTA) update. The security field can be programmed in the factory after all programming and testing has been done.

True Random Number Generator

The CYBT-2x305x-02 includes a hardware TRNG (True Random Number Generator). Applications can access the random number
generator via firmware APIs.

Document Number: 002-29172 Rev. ** Page 17 of 45

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CYBT-223058-02
CYBT-253059-02

Peripherals and Communication Interfaces

I2C

The CYBT-2x305x-02 provides a 2-pin I2C master/slave interface to communicate with I2C compatible peripherals. The following
transfer clock rates are supported:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I

■ 1 MHz (Compatibility with high-speed I

The I2C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where
read/write can be up to 64 bytes.

SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 5), allowing for flexible system configuration.
When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I
multimaster capability or flexible wait-state insertion by either master or slave devices.

HCI UART Interface

CYBT-2x305x-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with
an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from
115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also
available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command.
The CYBT-2x305x-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±5%. The UART interface CYBT-2x305x-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced
data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-2x305x-02 or allow the CYBT-2x305x-02 to sleep
when radio activities permit. The CYBT-2x305x-02 can also wake up the host as needed or allow the host to sleep via the
HOST_WAKE signal. Combined, the two signals allow the host and the CYBT-2x305x-02 to optimize system power consumption by
allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific
command.

The FW UART driver allows applications to select different baud rates.

2

C-compatible speed)

2

C-compatible devices is not guaranteed)

2

C does not support

Peripheral UART Interface

The CYBT-2x305x-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the same
as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be configured
individually and separately for each functional pin. The CYBT-2x305x-02 can map the peripheral UART to any GPIO.

Serial Peripheral Interface

The CYBT-2x305x-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI operations.
Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more
flexibility for user applications, the CYBT-2x305x-02 has optional I/O ports that can be configured individually and separately for each
functional pin.

SPI IO voltage depends on VDDO.

Keyboard Scanner

The CYBT-2x305x-02 includes a HW key scanner that supports a maximum matrix size of 20 × 8. The scanner has eight inputs (also
referred to as rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down sequentially and
sampling the rows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also operate in Sleep
and PDS modes allowing low power operation while continuing to detect/store all key strokes, up or down. In other low power modes,
the scanner can continue to monitor the matrix and initiate exit to Active Mode upon detecting a change of state.

The application can access the key scanner via the associated firmware driver. Refer to the Firmware section for more details.

Mouse Quadrature Signal Decoder

The CYBT-2x305x-02 includes one double-axis and one single axis quadrature decoders. There are two input lines for each axis and
a programmable control signal that can be active high or low.

The application can access the quadrature interface via the driver included in the firmware.

Document Number: 002-29172 Rev. ** Page 18 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

ADC Port

The CYBT-2x305x-02 includes a Σ-Δ ADC designed for audio and DC measurements. The ADC can measure the voltage on 15
GPIOs (P0, P1, P8-P15, P17, P28, P29, P32, P37). When used for analog inputs, the GPIOs must be placed in digital input disable
mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap reference has ±5% accuracy without
calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement
accuracy in Direct Current (DC) Mode.

The application can access the ADC through the ADC driver included in the firmware.
The following CYBT-2x305x-02 module solder pads can be used as ADC inputs:

■ Pad 3: P32, ADC Channel Input 7

■ Pad 6: P37, ADC Channel Input 2

■ Pad 7: P29, ADC Channel Input 10

■ Pad 9: P0, ADC Channel Input 29

■ Pad 10: P1, ADC Channel Input 28

■ Pad 11: P10, ADC Channel Input 25

■ Pad 12: P13, ADC Channel Input 22

■ Pad 13: P12, ADC Channel Input 23

■ Pad 14: P11, ADC Channel Input 24

■ Pad 15: P9, ADC Channel Input 26

■ Pad 16: P14, ADC Channel Input 21

■ Pad 17: P17, ADC Channel Input 18

■ Pad 23: P8, ADC Channel Input 27

■ Pad 24: P15, ADC Channel Input 20

■ Pad 28: P28, ADC Channel Input 11

GPIO Port

The CYBT-2x305x-02 has a maximum of 22 GPIOs. All GPIOs support the following:

■ Programmable pull-up/down of approximately 45 kΩ.

■ Input disable mode, allowing pins to be left floating or analog signals connected without risk of leakage.

■ Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

■ P26/P27/P28/P29 can sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.

Most peripheral functions can be assigned to any GPIO using the ModusToolbox Device Configurator. For details on the functions
that are assignable via the ModusToolbox Device Configurator, refer to Table 5.

The following list details the GPIOs that are available on the CYBT-2x305x-02 module:

■ P0-P6, P8-P15, P17, P26-P29, P32, and P37

Document Number: 002-29172 Rev. ** Page 19 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

PWM

The CYBT-2x305x-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:

■ Each of the six PWM channels contains the following registers:
❐ 16-bit initial value register (read/write)
❐ 16-bit toggle register (read/write)

❐ 16-bit PWM counter value register (read)

■ PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used:
❐ To configure each PWM channel
❐ To select the clock of each PWM channel

❐ To change the phase of each PWM channel

The application can access the PWM module through the FW driver.

Figure 12 shows the structure of one PWM channel.

Figure 12. PWM Block Diagram

PDM Microphone

The CYBT-2x305x-02 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either
8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate
digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:

■ 8 kHz

■ 16 kHz

The external digital microphone takes in a 2.4-MHz clock generated by the CYBT-2x305x-02 and outputs a PDM signal, which is
registered by the PDM interface with either the rising or falling edge of the 2.4-MHz clock selectable through a programmable control
bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.

Document Number: 002-29172 Rev. ** Page 20 of 45

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

I2S Interface

The CYBT-2x305x-02 supports a single I2S digital audio port. with both master and slave modes.

2

The I

S signals are:

2

■ I

S Clock: I2S SCK

2

■ I

S Word Select: I2S WS

2

■ I

S Data Out: I2S DO

2

■ I

S Data In: I2S DI

2

I

S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel
word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I
Specifications. The MSB of each data word is transmitted one bit clock cycle after the I
edge of bit clock. Left Channel data is transmitted when I
Data bits sent by the CYBT-2x305x-02 are synchronized with the falling edge of I
the rising edge of the I

2

S SCK.

2

S WS is low, and right-channel data is transmitted when I2S WS is high.

2

S WS transition, synchronous with the falling

2

S SCK and should be sampled by the receiver on

2

S bus, per I2S

The clock rate in master mode is either one of the following:

■ 32 kHz × 32 bits per frame = 1024 kHz

■ 32 kHz × 50 bits per frame = 1600 kHz

The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock rate is supported up
to a maximum of 3.072 MHz.

Note: The PCM interface shares HW with the I

2

S interface and only one can be used at a given time.

PCM Interface

The CYBT-2x305x-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master
mode, the CYBT-2x305x-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another
master on the PCM interface and are inputs to the CYBT-2x305x-02.The configuration of the PCM interface may be adjusted by the
host through the use of vendor-specific HCI commands.

Note: The PCM interface shares HW with the I
Note: Only audio source (other than SCO) use cases are supported on CYW20819/20 at this time.

2

S interface and only one can be used at a given time.

Slot Mapping

The CYBT-2x305x-02 supports up to three simultaneous full-duplex channels through the PCM Interface. These three channels are
time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is
divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz).
The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. The PCM data output driver tristates its
output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after
the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The CYBT-2x305x-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchro­nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and
is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects
the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.

Data Formatting

The CYBT-2x305x-02 may be configured to generate and accept several different data formats. For conventional narrow band speech
mode, the CYBT-2x305x-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to
support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a
sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

Document Number: 002-29172 Rev. ** Page 21 of 45

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CYBT-223058-02
CYBT-253059-02

Electrical Characteristics

The absolute maximum ratings in Table 10 indicate levels where permanent damage to the device can occur, even if these limits are
exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum
conditions for extended periods can adversely affect long-term reliability of the device.

Table 10. Silicon Absolute Maximum Ratings

Requirement Parameter

Maximum Junction Temperature TBD TBD – °C
VDDO1/VDDO2 –0.5 – 3.795 V
IFVDD/PLLVDD/VCOVDD/VDDC –0.5 – 1.38 V
PMUAVDD/SR_PVDD –0.5 – 3.795 V
DIGLDO_VDDIN –0.5 – 1.65 V
RFLDO_VDDIN –0.5 – 1.65 V
MIC_AVDD –0.5 – 3.795 V
PALDO_VDDIN (CYBT-253059-02 only) –0.5 – 3.79 V
PAVDD (CYBT-253059-02 only) –0.5 – 2.75 V

Table 11. ESD/Latch-up

Requirement Parameter

ESD Tolerance HBM (Silicon) –2000 – 2000 V
ESD Tolerance CDM (Silicon) –500 – 500 V
Latch-up – 200 – mA

Table 12. Power Supply Specifications

Min Nom Max

Min Nom Max

Specification

Specification

Unit

Unit

Parameter Conditions Min Typ Max Unit

VDD input Module Input 1.71 (CYBT-223058-02)

VDD Ripple Module Input Ripple (VDD) – – 100 mV

Table 13. Shutdown Voltage (Brown Out)

Parameter

V

SHUT

The CYBT-2x305x-02 uses an onboard low voltage detector to shut down the device when supply voltage (VBAT) drops below the
operating range.

Document Number: 002-29172 Rev. ** Page 22 of 45

Min Typ Max

1.5 1.56 1.7 V

2.6 (CYBT-253059-02)

Specification

3.0 3.63 V

Unit

PRELIMINARY

CYBT-223058-02
CYBT-253059-02

Current Consumption

Ta bl e 1 4 provides the current consumption measurements taken at the input of LDOIN and VDDIO combined (LDOIN = VDDIO =

3.0 V).

Table 14. Current Consumption

Operational Mode Conditions Typical Unit

HCI

RX Continuous RX 5.9 mA

TX

PDS – 16.5 µA
ePDS All RAM retained 8.7 µA
HID-Off (SDS) 32 kHz XTAL on 1.75 µA

48 MHz with Pause 1.3 mA
48 MHz without Pause 2.55 mA

Continuous TX –4 dBm (CYBT-223058-02)
Continuous TX –10.5 dBm (CYBT-253059-02)

5.8 (CYBT-223058-02)

22.0 (CYBT-253059-02)

mA

Silicon Core Buck Regulator

Table 15. Core Buck Regulator

Parameter Conditions Min Typ Max Unit

Input Supply, VBAT DC Range 1.71 3.0 3.63 V

Output Current

Output Voltage

Output Voltage Accuracy

Ripple Voltage

Output Inductor, L
Output Capacitor, C
Input Capacitor, C
Input Supply Voltage Ramp

Time

Note

3. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

OUT

IN

Active Mode – < 60 100 mA
PDS Mode – < 60 70 mA
Active Mode 1.1 1.26 1.4 V
PDS Mode, 40 mV min regulation window. 0.76 0.94 Avg 1.4 V
Active Mode, includes line and load regulation.

Before trim:
Active Mode

2.2 μH ± 25% inductor, DCR = 114 mΩ ± 20%

4.7 μF ± 10% capacitor, Total ESR < 20 mΩ
PDS Mode – – – mV

Refer to the Recommended Component section for more
details.

0 to 3.3 V 40 – – µs

–4 – +4

–3–mV

[3]

1.6

3.0

4.0

[3]

[3]

2.2 – µH

4.7 – µF
10 – µF

%

Document Number: 002-29172 Rev. ** Page 23 of 45

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CYBT-253059-02

Digital LDO

Note

4. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

Table 16. Digital LDO

Parameter Conditions Min Ty p Max Unit

Input Supply, DIGLDO_VDDIN Min must be met for correct operation V

Range 0.9 1.2 1.275 V

Output Voltage, DIGLDO_VDDOUT

Step – 25 – mV

Accuracy after trimming –2 – +2 %
Dropout Voltage At max load current – – 20 mV
Output Current DC Load 0.075 40 60 mA
Quiescent Current At T ≤ 85 °C, V
Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 mٶ1.55
Line Regulation 1.235 V ≤ V
Load Regulation V

Load Step Error

Leakage Current

In-rush Current C
LDO Turn On Time C

PSRR

= 1.2 V, V

OUT

I

step 1 mA ↔ 20 mA @ 1 µs rise/fall,

OUT

C

= 2.2 µF, V

OUT

Power down Mode, V

Power down Mode, V

= 2.2 µF, V

OUT

= 2.2 µF, V

OUT

C

= 2.2 µF, 1.235V ≤ VIN ≤ 1.4 V, V

OUT

= 20 mA

I

OUT

f = 1 kHz

= 1.4 V – – 40 µA

IN

≤ 1.4 V – 5 10 mV/V

IN

= 1.26 V, 1 mA ≤ I

IN

= 1.235 V, V

IN

= 1.4 V, Temp = 25 °C––50nA

IN

= 1.4 V, Temp = 125 °C – –2µA

IN

= 1.4 V, V

IN

= 1.4 V, V

IN

OUT

OUT

OUT

≤ 25 mA – – 0.44 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA

= 1.2 V, I

= 20 mA – – 120 µs

OUT

= 1.2 V,

OUT

f = 100 kHz

+ 20 mV 1.26 1.4 V

OUT

[4]

2.2 – µF

–24 – +24 mV

25

––dB

13

dB

RF LDO

Table 17. RF LDO

Parameter Conditions Min Typ Max Unit

Input Supply, RFLDO_VDDIN Min must be met for correct operation V

Range 1.1 1.2 1.275 V

Output Voltage, RFLDO_VDDOUT

Step – 25 – mV

Accuracy –4 – +4 %
Dropout Voltage At max load current – – 20 mV
Output Current DC Load – 20 60 mA
Quiescent Current At T ≤ 85 °C, V
Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 mٶ1.55
Line Regulation 1.235 V ≤ V
Load Regulation V

Load Step Error

Leakage Current

In-rush Current C
LDO Turn On Time C

= 1.2 V, V

OUT

I

step 1 mA ↔ 20 mA @ 1 µs rise/fall,

OUT

= 2.2 µF, V

C

OUT

Power down Mode, V

Power down Mode, V

= 2.2 µF, V

OUT

= 2.2 µF, V

OUT

= 1.4 V – – 50 µA

IN

≤ 1.4 V – – 10 mV/V

IN

= 1.26 V, 1 mA ≤ I

IN

= 1.235 V, V

IN

= 1.4 V, Temp = 25 °C––50nA

IN

= 1.4 V, Temp = 125 °C––2µA

IN

= 1.4 V, V

IN

= 1.4 V, V

IN

OUT

OUT

OUT

≤ 25 mA – – 1 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA
= 1.2 V, I

= 20 mA – – 120 µs

OUT

+ 20 mV 1.26 1.4 V

OUT

[4]

2.2 – µF

–24 – +24 mV

Document Number: 002-29172 Rev. ** Page 24 of 45

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Table 17. RF LDO (continued)

Note

5. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effect.

Parameter Conditions Min Typ Max Unit

PSRR

= 2.2 µF, 1.235 V ≤ VIN ≤ 1.4 V, V

C

OUT

I

= 20 mA

OUT

f = 1 kHz
f = 100 kHz

OUT

= 1.2 V,

25
13

––dB

dB

PA LDO (CYBT-253059-02 only)

Table 18. PA LDO (CYBT-253059-02 only)

Parameter Conditions Min. Typ. Max. Unit

Input Supply, PALDO_VDDIN

VDDIN min must be greater than V
load current for proper regulation

+100mV under max

OUT

Range 1.5 2.45 3.0 V

Output Voltage,
PALDO_VDDOUT

Step 100 mV

Accuracy -4 – +4 %
HTOL Output Voltage –3.3– V
Dropout Voltage At max load current – – 100 mV
Output Current DC Load 0 30 60 mA
Quiescent Current At T ≤ 85 °C, V
Output Load Capacitor, C

OUT

Line Regulation 2.7 V ≤ VIN ≤ 3.63 V, V
Load Regulation V

Load Step Error

Leakage Current

In-rush Current C
LDO Turn On Time C

PSRR

= 3.3 V, V

IN

I

step 1 mA↔20 mA @ 1μs rise/fall, C

OUT

V

= 3.3 V, V

IN

Power-down mode, V

Power-down mode, V

= 2.2 μF, V

OUT

= 2.2 μF, V

OUT

C

= 2.2 μF, V

OUT

= 1 kHz

f

f

= 100 kHz 25 – – dB

= 3.3 V – – 110 μA

IN

= 2.5 V – – 25 mV/V

OUT

= 2.5V, 0mA ≤ I

OUT

= 2.5 V

OUT

IN

IN

= 3.3 V, V

IN

= 3.3 V, V

IN

= 3.3 V, V

IN

= 3.6 V, Temp = 25 °C––1.6μA
= 3.6 V, Temp = 125 °C––4.9μA

OUT

OUT

OUT

≤ 30 mA – – 1 mV/mA

OUT

= 2.2 μF,

OUT

= 2.5 V – – 140 mA
= 2.5 V, I
= 2.5 V, I

= 20 mA – – 140 μs

OUT

= 20 mA

OUT

2.6 3.3 3.63 V

[5]

1.2

2.2 – μF

-25 – 25 mV

45 – – dB

Document Number: 002-29172 Rev. ** Page 25 of 45

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Digital I/O Characteristics

Table 19. Digital I/O Characteristics

Characteristics Symbol Min Typ Max Unit

Input low voltage (VDD = 3 V) V
Input high voltage (VDD = 3 V) V
Input low voltage (VDD = 1.8 V) V
Input high voltage (VDD = 1.8 V) V
Output low voltage V
Output high voltage V
Input low current I
Input high current I
Output low current (VDD = 3 V, V
Output low current (VDD = 3 V, V
Output high current (VDD = 3 V, V

= 0.4 V) I

OL

= 1.8 V) I

OL

= 2.6 V) I

OH

Output high current (VDD = 1.8 V, VOH = 1.4 V) I
Input capacitance C

IL

IH

IL

IH

OL

OH

IL

IH

OL

OL

OH

OH

IN

––0.8V

2.4 – – V
––0.4V

1.4 – – V
––0.4V

VDDO – 0.4 V – – V

––1.0µA
––1.0µA
––4.0mA
––2.0mA
––8.0mA
––4.0mA
––0.4pF

ADC Characteristics

Table 20. Electrical Characteristics

Parameter Symbol Conditions/Comments Min Typ Max Unit

Current consumption I

TOT

Power down current – At room temperature – 1 – µA

ADC Core Specification

ADC reference voltage VREF From BG with ±3% accuracy – 0.85 – V
ADC sampling clock – – – 12 – MHz
Absolute error – Includes gain error, offset and

ENOB – For audio application 12 13 –

ADC input full scale FS For audio application – 1.6 –

Conversion rate – For audio application 8 16 – kHz

Signal bandwidth –

Input impedance R

IN

Startup time –

MIC PGA Specifications

MIC PGA gain range – – 0 – 42 dB
MIC PGA gain step – – – 1 – dB
PGA input referred noise – At 42 dB PGA gain A-weighted – – 4 µV

––23mA

––5%

distortion. Without factory calibration.
Includes gain error, offset and

––2%

distortion. After factory calibration.

For static measurement 10 – –

Bit

For static measurement 1.8 – 3.6

For audio application 20 – 8K
For static measurement – DC –
For audio application 10 – –
For static measurement 500 – –

Hz

KΩ

For audio application – 10 – ms
For static measurement – 20 – µs

Document Number: 002-29172 Rev. ** Page 26 of 45

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Table 20. Electrical Characteristics (continued)

Parameter Symbol Conditions/Comments Min Typ Max Unit

MIC Bias Specifications

MIC bias output voltage – At 3-V supply, 25 °C, default settings – 2.4 – V
MIC bias loading current – – – – 3 mA

MIC bias noise –

MIC bias PSRR – At 1 kHz 40 – – dB

ADC SNR –

ADC THD + N –

GPIO input voltage Always lower than avddBAT – – 3.6 V

GPIO source impedance

Note

6. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.

[6]

–

Refers to PGA input 20 Hz to
8 kHz, A-weighted

A-weighted 0 dB PGA gain,
Temperature = 25 °C

–3 dBFS input 0 dB PGA gain,
Temperature = 25 °C

Resistance – – 1 kΩ
Capacitance – – 10 pF

––3µV

–78–dB

–70–dB

Document Number: 002-29172 Rev. ** Page 27 of 45

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Chipset RF Specifications

Ta bl e 2 1 through Table 24 apply to single-ended industrial temperatures. Unused inputs are left open.

Table 21. BR/EDR - Receiver RF Specifications

Parameter Mode and Conditions Min Typ Max Unit

Receiver Section

Frequency range – 2402 – 2480 MHz

[7]

–dBm

dB

11.0

dB

dBm

dBm

RX sensitivity

GFSK, BDR GFSK 0.1% BER, 1
Mbps

EDR 2M – –94.0 –

–92.0 (CYBT-223058-02)

–

–91.0 (CYBT-253059-02)

EDR 3M – –88.0 –

Maximum input – –20 – – dBm

Interference Performance

C/I cochannel GFSK, BDR GFSK 0.1% BER
C/I 1 MHz adjacent

channel
C/I 2 MHz adjacent

channel
C/I ≥ 3 MHz adjacent

channel

GFSK, BDR GFSK 0.1% BER

GFSK, BDR GFSK 0.1% BER

GFSK, BDR GFSK 0.1% BER

C/I image channel GFSK, BDR GFSK 0.1% BER
C/I 1 MHz adjacent to

image channel

Out-of-Band Blocking Performance (CW)

GFSK, BDR GFSK 0.1% BER

[9]

[8]

–

[8]

– –4.0

[8]

– –31.5

[8]

– –42.5

[8]

– –24.0

[8]

– –35.0

TBD

30 MHz to 2000 MHz BDR GFSK 0.1% BER – –10.0 –
2000 MHz to 2399

MHz
2498 MHz to 3000

MHz
3000 MHz to 12.75

GHz

Intermodulation Performance

BT, interferer signal
level

BDR GFSK 0.1% BER – –27 –

BDR GFSK 0.1% BER – –27 –

BDR GFSK 0.1% BER – –10.0 –

[8]

BDR GFSK 0.1% BER – – –39.0 dBm

Spurious Emissions

30 MHz to 1 GHz – – – –57.0
1 GHz to 12.75 GHz – – – –47.0

Notes

7. The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off.

8. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

9. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

Document Number: 002-29172 Rev. ** Page 28 of 45

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Table 22. BR/EDR - Transmitter RF Specifications

Parameter Min Typ Max Unit

Transmitter Section

Frequency range 2402 – 2480 MHz

Class 21: BR TX power –

Class 21: EDR 2M and 3M TX power – – –
20 dB bandwidth – 930 1000 kHz

Adjacent Channel Power

|M – N| = 2 – – –20
|M – N| ≥ 3

Out-of-Band Spurious Emission

30 MHz to 1 GHz – – –36.0
1 GHz to 12.75 GHz – – –30.0

1.8 GHz to 1.9 GHz – – –47.0

5.15 GHz to 5.3 GHz – – –47.0

LO Performance

Initial carrier frequency tolerance –75 – +75 kHz
Frequency Drift
DH1 packet –25 – +25

DH5 packet –40 – +40
Drift rate –20 – 20 kHz/50 µs

Frequency Deviation

Average deviation in payload (sequence used is 00001111) 140 – 175
Maximum deviation in payload (sequence used is 10101010) 115 – –
Channel spacing – 1 – MHz

Note

10. Meet SIG Specification.

[10]

– – –40

4.0 (CYBT-223058-02)

10.5 (CYBT-253059-02)

–

dBm

dBm

dBm

kHzDH3 packet –40 – +40

kHz

Document Number: 002-29172 Rev. ** Page 29 of 45

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Table 23. BLE RF Specifications

Notes

11. Meets SIG Specification.

12. Dirty TX is Off.

13. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

14. 255 byte packet.

Parameter Conditions Min Typ Max Unit

Frequency range N/A 2402 – 2480 MHz

RX sensitivity

[12]

GFSK, BDR GFSK 0.1% BER

0.1% BER, 1 Mbps

TX power N/A –

–

–95.0 (CYBT-223058-02)
–94.5 (CYBT-253059-02)

4.0 (CYBT-223058-02)

10.5 (CYBT-253059-02)

–dBm

–dBm

Mod Char: Delta F1 average N/A 225 255 275 kHz

[13]

Mod Char: Delta F2 max

N/A 99.9 – – %

Mod Char: Ratio N/A 0.8 – – %

Table 24. BLE2 RF Specifications

Parameter Conditions Min Typ Max Unit

RX sensitivity

[14]

– – –89.0 (CYBT-223058-02)

–dBm

–89.5 (CYBT-253059-02)

TX power – – 4.0 (CYBT-223058-02)

–dBm

10.5 (CYBT-253059-02)

Document Number: 002-29172 Rev. ** Page 30 of 45

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Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

UART Timing

Table 25. UART Timing Specifications

Reference Characteristics Min Ty p Max Unit

1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods
2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods
3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods

Figure 13. UART Timing

Document Number: 002-29172 Rev. ** Page 31 of 45

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SPI Timing

The SPI interface can be clocked up to 24 MHz.

Ta bl e 2 6 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2.

Table 26. SPI Mode 0 and 2

Reference Characteristics Min Max Unit

1 Time from master assert SPI_CSN to first clock edge 45 – ns
2 Setup time for MOSI data lines 6 ¾
3 Idle time between subsequent SPI transactions 1 SCK – ns

Figure 14. SPI Timing, Mode 0 and 2

SCK ns

Ta bl e 2 7 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3.

Table 27. SPI Mode 1 and 3

Reference Characteristics Min Max Unit

1 Time from master assert SPI_CSN to first clock edge 45 – ns
2 Setup time for MOSI data lines 6 ¾ SCK ns
3 Idle time between subsequent SPI transactions 1 SCK – ns

Document Number: 002-29172 Rev. ** Page 32 of 45

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Figure 15. SPI Timing, Mode 1 and 3

I2C Compatible Interface Timing

The specifications in Table 27 references Figure 16.

Table 28. I2C Interface Timing Specifications (up to 1 MHz)

Reference Characteristics Min Max Unit

100 kHz

1 Clock frequency –

2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold time
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns

10 Bus free time

Notes

15. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

16. Time that the CBUS must be free before a new transaction can start.

[15]

[16]

0 – ns

650 – ns

400 kHz
800 kHz

1000 kHz

Document Number: 002-29172 Rev. ** Page 33 of 45

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Figure 16. I

2

C Interface Timing Diagram

I2S Interface Timing

I2S timing is shown below in Table 29, Figure 17, and Figure 18.

Table 29. Timing for I2S Transmitters and Receivers

Transmitter Receiver

NotesLower LImit Upper Limit Lower Limit Upper Limit

Min Max Min Max Min Max Min Max

Clock Period T

T

tr

–––

Master Mode: Clock generated by transmitter or receiver

HIGH t

LOWt

HC

LC

0.35T

0.35T

tr

tr

–––

–––

Slave Mode: Clock accepted by transmitter or receiver

HIGH t

HC

LOW t

LC

Rise time t

RC

–

–

––

0.35T

0.35T

tr

tr

–––

–––

0.15T

tr

– – – – [18]

Transm itte r

Delay t

dtr

Hold time t

htr

– – – 0.8T – – – – [19]
0–––––––[18]

Receiver

Setup time t

Hold time t

Notes

17. The system clock period T must be greater than T

18. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t
respect to T.

19. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum
periods are greater than 0.35T

20. Because the delay (t
t

RC

tRC is not more than t

21. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient
setup time.

22. The data setup and hold time must not be less than the specified receiver setup and hold time.

sr

hr

which means t

, any clock that meets the requirements can be used.

r

) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding

dtr

becomes zero or negative. Therefore, the transmitter has to guarantee that t

htr

RCmax

, where t

––––

––––

and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.

tr

is not less than 0.15Ttr.

RCmax

T

r

0.35T

tr

0.35T

tr

0.2T

tr

0.2T

tr

is greater than or equal to zero, so long as the clock rise-time

htr

–––[17]

– – – [18]

– – – [18]

0.35T

0.35T

tr

tr

––[17]

––[17]

– – – [20]

– – – [20]

and tLC are specified with

HC

Document Number: 002-29172 Rev. ** Page 34 of 45

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Figure 17. I2S Transmitter Timing

Figure 18. I

2

S Receiver Timing

Document Number: 002-29172 Rev. ** Page 35 of 45

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Environmental Specifications

Note

23. This does not apply to the RF pins (ANT).

Environmental Compliance

This Cypress Bluetooth module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free
(HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBT-2x305x-02 module is certified under the following RF certification standards:

■ FCC: WAP3058

■ ISED: 7922A-3058

■ MIC: TBD

■ CE

Safety Certification

The CYBT-2x305x-02 module complies with the following safety regulations:

■ Underwriters Laboratories, Inc. (UL): Filing E331901

■ CSA

■ TUV

Environmental Conditions

Ta bl e 3 0 describes the operating and storage conditions for the Cypress Bluetooth module.

Table 30. Environmental Conditions for CYBT-2x305x-02

Description Minimum Specification Maximum Specification

Operating temperature −30 °C 85 °C
Operating humidity (relative, non-condensation) 5% 85%
Thermal ramp rate
Storage temperature
Storage temperature and humidity

ESD: Module integrated into system Components

[23]

– 10 °C/minute

–40 °C 85 °C

– 85 °C at 85%

–

15 kV Air

2.0 kV Contact

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.

Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Document Number: 002-29172 Rev. ** Page 36 of 45

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Regulatory Information

FCC

FCC NOTICE:
The device CYBT-2x305x-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter

approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■

Reorient or relocate the receiving antenna.

■

Increase the separation between the equipment and receiver.

■

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

■

Consult the dealer or an experienced radio/TV technician for help

This module is only FCC authorized for the specific rule FCC 15.247 listed on the grant, and that the host product manufacturer is
responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of
certification, final host product requires Part 15 Subpart B compliance testing with the modular transmitter installed.

LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP3058.

In any case the end product must be labeled exterior with “Contains FCC ID: WAP3058”.

ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 13. When integrated in the OEMs

product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna
not in Table 7 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna

in Table 7, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about
the integrated radio module is not allowed.

The radiated output power of CYBT-2x305x-02 with the integrated PCB trace antenna (FCC ID: WAP3058) is far below the FCC radio
frequency exposure limits. Nevertheless, use CYBT-2x305x-02 in such a manner that minimizes the potential for human contact during
normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance. This equipment should be installed and operated with
minimum distance 8mm between the radiator & your body.

Document Number: 002-29172 Rev. ** Page 37 of 45

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ISED

Innovation, Science and Economic Development (ISED) Canada Certification

CYBT-2x305x-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada.
License: IC: 7922A-3058
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antenna listed in Table 7 on page 13, having a maximum gain of -0.5 dBi. Antennas
not included in Table 7 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.

ISED NOTICE:
The device CYBT-2x305x-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the

requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This
device may not cause harmful interference, and (2) This device must accept any interference received, including interference that
may cause undesired operation.

L'appareil CYBT-2x305x-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux
exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions
suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y
compris les interférences pouvant entraîner un fonctionnement indésirable.

ISED INTERFERENCE STATEMENT FOR CANADA
This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).

Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any
interference, including interference that may cause undesired operation of the device.

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de
licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur
de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le
fonctionnement.

ISED RADIATION EXPOSURE STATEMENT FOR CANADA
This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be

installed and operated with minimum distance 15mm between the radiator & your body.

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. Cet
équipement doit être installé et utilisé avec un minimum de 15mm de distance entre la source de rayonnement et votre corps.

LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as
the ISED Notices above. The IC identifier is 7922A-3058. In any case, the end product must be labeled in its exterior with “Contains

IC:

7922A-3058”.

Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend une
étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit
ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3058. En tout cas, le produit final doit être étiqueté dans son extérieur
avec “Contient

Document Number: 002-29172 Rev. ** Page 38 of 45

IC:

7922A-3058”.

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CYBT-223058-02
CYBT-253059-02

European Declaration of Conformity

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-2x305x-02 complies with the essential requirements and
other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive
2014, the end-customer equipment should be labeled as follows:

All versions of the CYBT-2x305x-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus,
Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta,
Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

MIC Japan

CYBT-2x305x-02 is certified as a module with certification number TBD. End products that integrate CYBT-2x305x-02 do not need
additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

Document Number: 002-29172 Rev. ** Page 39 of 45

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CYBT-253059-02

Packaging

Table 31. Solder Reflow Peak Temperature

Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles

CYBT-2x305x-02 35-pad SMT 260 °C 30 seconds 2

Table 32. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number Package MSL

CYBT-2x305x-02 35-pad SMT MSL 3

The CYBT-2x305x-02 is offered in tape and reel packaging. Figure 19 details the tape dimensions used for the CYBT-2x305x-02.

Figure 19. CYBT-2x305x-02 Tape Dimensions TBD

Figure 20 details the orientation of the CYBT-2x305x-02 in the tape as well as the direction for unreeling.

Figure 20. Component Orientation in Tape and Unreeling Direction TBD

Document Number: 002-29172 Rev. ** Page 40 of 45

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CYBT-253059-02

Figure 21 details reel dimensions used for the CYBT-2x305x-02.

Top View (Seen from Top)

Figure 21. Reel Dimensions TBD

The CYBT-2x305x-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBT-2x305x-02 is detailed in Figure 22.

Figure 22. CYBT-2x305x-02 Center of Mass TBD

Document Number: 002-29172 Rev. ** Page 41 of 45

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CYBT-253059-02

Ordering Information

Ta bl e 3 3 lists the CYBT-2x305x-02 part number and features. Ta bl e 3 3 also lists the target program for the respective module ordering

codes.

Table 33. Ordering Information

Ordering Part

Number

CYBT-223058-02 96 256 176 Yes Yes Yes Yes Yes 6 15 22 35-SMT Tape and Reel
CYBT-253059-02 96 256 176 Yes Yes Yes Yes Yes 6 15 22 35-SMT Tape and Reel

Ta bl e 3 4 lists the reel shipment quantities for the CYBT-2x305x-02.

Table 34. Tape and Reel Package Quantity and Minimum Order Amount

Description Minimum Reel Quantity Maximum Reel Quantity Comments

Reel Quantity 500 500 Ships in 500 unit reel quantities.
Minimum Order Quantity (MOQ)
Order Increment (OI)

The CYBT-2x305x-02 is offered in tape and reel packaging. The CYBT-2x305x-02 ships in a reel size of 500 units.

For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.

Max CPU

Speed

(MHz)

Flash

Size

(KB)

RAM

UART I2C SPI I2S PCM PWM

Size

(KB)

500 – –
500 – –

ADC

Inputs

GPIOs Package Packaging

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134
U.S. Cypress Headquarter Contact Info [phone]
Cypress website address www.cypress.com

Document Number: 002-29172 Rev. ** Page 42 of 45

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CYBT-253059-02

Acronyms Document Conventions

Table 35. Acronyms Used in this Document

Acronym Description

BLE Bluetooth Low Energy
Bluetooth SIG Bluetooth Special Interest Group
CE European Conformity
CSA Canadian Standards Association
EMI electromagnetic interference
ESD electrostatic discharge
FCC Federal Communications Commission
GPIO general-purpose input/output

ISED

IDE integrated design environment
KC Korea Certification

MIC

PCB printed circuit board
RX receive
QDID qualification design ID

SMT

TCPWM timer, counter, pulse width modulator (PWM)

TUV

TX transmit

Innovation, Science and Economic Devel­opment (Canada)

Ministry of Internal Affairs and Communications
(Japan)

surface-mount technology; a method for
producing electronic circuitry in which the
components are placed directly onto the surface
of PCBs

Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)

Units of Measure

Table 36. Units of Measure

Symbol Unit of Measure

°C degree Celsius
dB decibel
dBi decibels relative to isotropic
dBm decibel-milliwatts
kV kilovolt
mA milliamperes
mm millimeters
mV millivolt
µA microamperes
µm micrometers
MHz megahertz
GHz gigahertz
Vvolt

Document Number: 002-29172 Rev. ** Page 43 of 45

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CYBT-253059-02

Document History Page

Document Title: CYBT-223058-02, CYBT-253059-02, EZ-BT Module
Document Number: 002-29172

Revision ECN

** 6744579 12/11/2019 Preliminary datasheet for CYBT-223058-02, CYBT-253059-02 EZ-BT Module.

Submission

Date

Description of Change

Document Number: 002-29172 Rev. ** Page 44 of 45

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CYBT-223058-02
CYBT-253059-02

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

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Document Number: 002-29172 Rev. ** Revised December 11, 2019 Page 45 of 45