Cypress Semiconductor 3052 User Manual

CYBT-343052-02

EZ-BT WICED Module

CYBT-343052-02, EZ-BT WICED Module

Note

1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +12.0 dBm. Actual range will vary based on end product design, environment, receive sensitivity, and transmit output power of the central device.

General Description

The CYBT-343052-02 is a fully integrated Bluetooth Smart Ready wireless module. The CYBT-343052-02 includes an onboard crystal oscillator, passive components, flash memory, and the Cypress CYW20735 silicon device. Refer to the CYW20735 datasheet for additional details on the capabilities of the silicon device used in this module.

The CYBT-343052-02 supports peripheral functions (ADC and PWM), UART, I2C, and SPI communication, and a PCM/I2S audio interface. The CYBT-343052-02 includes a royalty-free Bluetooth stack compatible with Bluetooth 5.0 in a 13.3 × 22.4 × 1.95 mm package.

The CYBT-343052-02 includes 512 KB of onboard serial flash memory and is designed for standalone operation. The CYBT-343052-02 uses an integrated power amplifier to achieve Class I or Class II output power capability.

The CYBT-343052-02 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost-optimized Bluetooth wireless connectivity.

Module Description

■ Module size: 13.3 mm × 22.4 mm × 1.95 mm

■ Bluetooth 5.0 Qualified Smart Ready module ❐ QDID: TBD

❐ Declaration ID: TBD

■ Certified to FCC, ISED, MIC, and CE regulations

■ Castelated solder pad connections for ease-of-use

■ 512-KB on-module serial flash memory

■ Up to 24 GPIOs

■ Temperature range: –30 °C to +85 °C

■ Cortex-M4 32-bit processor

■ Maximum TX output power ❐ +10 dbm for Bluetooth Classic ❐ +12 dBm for Bluetooth Low Energy

• BLE connection range of up to 250 meters at 12 dBm

■ RX receive sensitivity: ❐ Bluetooth Classic: –91.5 dBm

❐ –94.5 dBm for Bluetooth Low Energy

Power Consumption

■ BLE Current Consumption ❐ RX current: 8 mA

❐ TX current: 18 mA @ 12 dBm ❐ Interval BLE ADV average current consumption: 30 µA ❐ HIDOFF (Deep Sleep): 1 µA

Functional Capabilities

■ 1x MIPI DMI-C interface

■ 6x 16-bit PWMs

■ Programmable key-scan matrix interface, up to 8x20 key

scanning matrix

■ Quadrature decoder

■ Watchdog timer (WDT)

■ 1x peripheral UART, 1x UART for programming and HCI

■ 1x SPI (master or slave mode)

■ 1x I2C master

■ One ADC (10-ENoB for DC measurement and 12-ENOB for

Audio measurement)

■ Hardware security engine

[1]

Benefits

CYBT-343052-02 provides all necessary components required to operate BLE and/or BR communication standards.

■ Proven ready-to-use hardware design

■ Dual-mode operation eliminates the need for multiple modules

■ Cost optimized for applications without space constraints

■ Nonvolatile memory for self-sufficient operation and

over-the-air updates

■ Bluetooth SIG listed with QDID and Declaration ID

■ Fully certified module eliminates the time needed for design,

development, and certification processes

■ WICED

Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-28053 Rev. ** Revised August 23, 2019

CYBT-343052-02

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.

References

■ Overview: EZ-BLE/BT Module Portfolio, Module Roadmap

■ CYW20735 BT Silicon Datasheet

■ Development Kits: ❐ CYBT-343052-EVAL, CYBT-343052-02 Evaluation Board

■ Test and Debug Tools: ❐ CYSmart, Bluetooth

❐ CYSmart Mobile, Bluetooth

LE Test and Debug Tool (Windows)

LE Test and Debug Tool

(Android/iOS Mobile App)

■ Knowledge Base Article ❐ KBA97095 - EZ-BLE™ Module Placement

❐ TBD - TBD ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐ KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules ❐ TBD - Platform Files for CYBT-343026-EVAL ❐ KBA223428 - Programming an EZ-BT WICED Module

Development Environments

Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)

Cypress' WICED® is a full-featured platform with proven Software Development Kits (SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth

WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards.

connectivity in system design.

Technical Support

■ Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share, and engage with both Cypress experts and other embedded engineers around the world.

■ Frequently Asked Questions (FAQs): Learn more about our Bluetooth ecosystem.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-28053 Rev. ** Page 2 of 47

CYBT-343052-02

Overview ............................................................................4

Functional Block Diagram ...........................................4

Module Description ......................................................4

Pad Connection Interface ................................................6

Recommended Host PCB Layout ...................................7

Module Connections ........................................................9

Connections and Optional External Components ....... 12

Power Connections (VDDIN) .....................................12

External Reset (XRES) ..............................................12

Multiple-Bonded GPIO Connections .........................13

Critical Components List ...........................................15

Antenna Design .........................................................15

Functional Description ...................................................16

Bluetooth Baseband Core .........................................16

Microcontroller Unit ................................................... 17

External Reset (XRES) ..............................................18

Integrated Radio Transceiver ........................................19

Transmitter Path ........................................................19

Receiver Path ............................................................19

Local Oscillator Generation .......................................19

Calibration .................................................................19

Peripheral and Communication Interfaces .................. 20

I2C Communication Interface ....................................20

HCI UART Interface ..................................................20

Triac Control ..............................................................21

Peripheral UART Interface ........................................21

Serial Peripheral Interface .........................................21

Infrared Modulator .....................................................22

PDM Microphone .......................................................22

Security Engine ......................................................... 22

Keyboard Scanner .......................................................... 23

Mouse Quadrature Signal Decoder ...........................24

ADC Port ...................................................................24

Clock Frequencies ..........................................................25

GPIO Port ........................................................................25

PWM .................................................................................25

Power Management Unit ................................................ 26

RF Power Management ............................................26

Host Controller Power Management ......................... 26

BBC Power Management ..........................................26

Electrical Characteristics ...............................................27

Chipset RF Specifications .............................................28

Timing and AC Characteristics ..................................... 30

UART Timing ............................................................. 30

SPI Timing ................................................................. 31

I2C Interface Timing .................................................. 33

Environmental Specifications .......................................36

Environmental Compliance .......................................36

RF Certification ..........................................................36

Safety Certification ....................................................36

Environmental Conditions .........................................36

ESD and EMI Protection ...........................................36

Regulatory Information .................................................. 37

FCC ...........................................................................37

ISED ..........................................................................38

European Declaration of Conformity ......................... 39

MIC Japan .................................................................39

Packaging ........................................................................ 40

Ordering Information ......................................................42

Acronyms ........................................................................43

Document Conventions .................................................45

Units of Measure .......................................................45

Document History Page ................................................. 46

Sales, Solutions, and Legal Information ...................... 47

Worldwide Sales and Design Support ....................... 47

Products ....................................................................47

PSoC® Solutions ......................................................47

Cypress Developer Community .................................47

Technical Support ..................................................... 47

Document Number: 002-28053 Rev. ** Page 3 of 47

CYBT-343052-02

Overview

CYW20735

Silicon Device

Passive Components

(RES, CAP, IND)

512KB

SERIAL FLASH

24 MHz

XTAL

XRES

UART

SPI

12C

PCM/12S

ADC

UPto6PWMs

UPto24GPIOs

32kHzLPO_In

(Optional)

1xMIPIDMI‐C

interface

Functional Block Diagram

Figure 1 illustrates the CYBT-343052-02 functional block diagram.

Figure 1. Functional Block Diagram (GPIOs)

Module Description

The CYBT-343052-02 module is a complete module designed to be soldered to the application’s main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna connection location dimensions

PCB thickness Height (H) 0.50 ± 0.05 mm Shield height Height (H) 1.45-mm typical Maximum component height Height (H) 1.45-mm typical Total module thickness (bottom of module to highest component) Height (H) 1.95-mm typical

See Figure 2 for the mechanical reference drawing for CYBT-343052-02.

Document Number: 002-28053 Rev. ** Page 4 of 47

Length (X) 13.31 ± 0.15 mm

Width (Y) 22.40 ± 0.15 mm

Length (X) 13.31 mm

Width (Y) 7.42 mm

CYBT-343052-02

Figure 2. Module Mechanical Drawing

Bottom View

Side View

Top View (Seen from Top)

Notes

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

3. The CYBT-343052-02 includes castellated pad connections, denoted as the circular openings at the pad location above.

Document Number: 002-28053 Rev. ** Page 5 of 47

CYBT-343052-02

Pad Connection Interface

As shown in the bottom view of Figure 2 on page 5, the CYBT-343052-02 connects to the host board via solder pads on the backside of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-343052-02 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 42 Solder Pads 1.01 mm 0.61 mm 0.90 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must not contain ground or signal traces. This keepout area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace antenna located at the far corner. This placement minimizes the additional recommended keepout area stated in item 2. Refer to

AN96841 for module placement best practices.

Figure 4. Recommended Host PCB Keepout Area Around the CYBT-343052-02 Antenna

Document Number: 002-28053 Rev. ** Page 6 of 47

CYBT-343052-02

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure , and Tab l e provide details that can be used for the recommended host PCB layout pattern for the

CYBT-343052-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure . It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-343052-02 Host Layout (Dimensioned) Figure 6. CYBT-343052-02 Host Layout (Relative to Origin)

Document Number: 002-28053 Rev. ** Page 7 of 47

CYBT-343052-02

Ta bl e 3 provides the center location for each solder pad on the CYBT-343052-02. All dimensions are referenced to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure for the location of each module solder pad.

Table 3. Module Solder Pad Location

Solder Pad

(Center of Pad)

25 (9.81, 22.02) (386.22, 866.93)

26 (10.71, 22.02) (421.65, 866.93)

27 (11.61, 22.02) (457.09, 866.93)

28 (12.93, 20.35) (509.05, 801.18)

29 (12.93, 19.44) (509.05, 765.35)

30 (12.93, 18.54) (509.05, 729.92)

31 (12.93, 17.64) (509.05, 694.49)

32 (12.93, 16.74) (509.05, 659.05)

33 (12.93, 15.84) (509.05, 623.62)

34 (12.93, 14.94) (509.05, 588.19)

35 (12.93, 14.03) (509.05, 552.36)

36 (12.93, 13.13) (509.05, 516.93)

37 (12.93, 12.23) (509.05, 481.50)

38 (12.93, 11.33) (509.05, 446.06)

39 (12.93, 10.43) (509.05, 410.63)

Location (X,Y) from

Orign (mm)

(0.38, 7.72) (14.96, 303.94)

(0.38, 8.62) (14.96, 339.37)

(0.38, 9.53) (14.96, 375.20)

(0.38, 10.43) (14.96, 410.63)

(0.38, 11.33) (14.96, 446.06)

(0.38, 12.23) (14.96, 481.50)

(0.38, 13.13) (14.96, 516.93)

(0.38, 14.03) (14.96, 552.36)

(0.38, 14.94) (14.96, 588.19)

(0.38, 15.84) (14.96, 623.62)

(0.38, 16.74) (14.96, 659.05)

(0.38, 17.64) (14.96, 694.49)

(0.38, 18.54) (14.96, 729.92)

(0.38, 19.44) (14.96, 765.35)

(0.38, 20.35) (14.96, 801.18)

(1.70, 22.02) (66.93, 866.93)

(2.60, 22.02) (102.36, 866.93)

(3.50, 22.02) (137.80, 866.93)

(4.40, 22.02) (173.23, 866.93)

(5.30, 22.02) (208.66, 866.93)

(6.20, 22.02) (244.09, 866.93)

(7.11, 22.02) (279.92, 866.93)

(8.01, 22.02) (315.35, 866.93)

(8.91, 22.02) (350.79, 866.93)

Dimension from

Orign (mils)

Table 3. Module Solder Pad Location

Solder Pad

(Center of Pad)

40 (12.93, 9.53) (509.05, 375.20)

41 (12.93, 8.62) (509.05, 339.37)

42 (12.93, 7.72) (509.05, 303.94)

Location (X,Y) from

Orign (mm)

Figure 7. Solder Pad Reference Location

Dimension from

Orign (mils)

Document Number: 002-28053 Rev. ** Page 8 of 47

CYBT-343052-02

Module Connections

Ta bl e 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-343052-02 module. Ta bl e 4 lists the solder pads on the CYBT-343052-02 module, the silicon device pin, and denotes what functions are available for each

solder pad.

Table 4.

Module Pad Name Pad Number Silicon Pin Name I/O Power Domain Description

Microphone Microphone

MIC_AVDD 23 MIC_AVDD I MIC_AVDD Microphone supply MIC_BIAS 26 MICBIAS O MIC_AVDD Microphone bias supply MIC_N 24 MICN I MIC_AVDD Microphone negative input MIC_P 25 MICP I MIC_AVDD Microphone positive input GND_A 22 27 Analog ground for microphone

Power Supply

VDD 2 2.5V~3.6V

Ground Pins Ground Pins

GND 1 18 21 42 HS-VSS I VSS Digital ground

UART UART

UART_CTS_N 28 UART_CTS_N I, PU VDDO CTS for HCI UART interface: NC if

UART_RTS_N 29 UART_RTS_N O, PU VDDO RTS for HCI UART interface. NC if

UART_RXD 31 UART_RXD I VDDO UART serial input. Serial data input for th e

UART_TXD 30 UART_TXD O, PU VDDO UART serial input. Serial data input f or th e

Interface Serial Peripheral

Interface

NA NA SPI_MISO I VDDO SPI Master In Slave Out SPI_MOSI 32 SPI_MOSI O VDDO SPI Master Out Slave In NA NA SPI_CSN O VDDO SPI Chip Select NA NA SPI_CLK O VDDO SPI Clock

Crystal Crystal

NA NA BT_XTALI I PLLVDD1P2 Crystal oscillator input: see “Crystal Oscil-

NA NA BT_XTALO O PLLVDD1P2 Crystal oscillator output XTALI_32K 19 XTALI_32K I VDDO Low-power oscillator input XTALO_32K 20 XTALO_32K O VDDO Low-power oscillator output

Others Others

NA NA DEFAULT_STRAP I VDDO Connect to VDDO

unused.

HCI UART interface.

lator” on page 12 for options

Document Number: 002-28053 Rev. ** Page 9 of 47

CYBT-343052-02

Table 4. (continued)

Module Pad Name Pad Number Silicon Pin Name I/O Power Domain Description

HOST_WAKE 35 BT_HOST_WAKE O VDDO Host wake-up. This is a signal from the

Bluetooth device to the host indicating that the Bluetooth device requires attention.

■ Asserted: Host device must wake up or

remain awake

■ Deasserted: Host device may sleep

when sleep awake criteria is met. The polarity of this signal is software config-

urable and can be asserted high or low. NA NA BT_RF I/O PAVDD2P5 RF antenna port NA NA JTAG_SEL – – ARM JTAG debug mode control: connect

to GND for all applications

XRES 3 RST_N I VDDO Active-low system reset with open-drain

output and internal pull-up resistor

Table 5.

Module pad

Name

P0 10 P0 Input Floating VDDO GPIO: P0

P1 9 P1 Input Floating VDDO GPIO: P1

P2 33 P2 Input Floating VDDO GPIO: P2

P3 34 P3 Input Floating VDDO GPIO: P3

P4 36 P4 Input Floating VDDO GPIO: P4

P5 37 P5 Input Floating VDDO GPIO: P5

P6 38 P6 Input Floating VDDO GPIO: P6

P7 39 P7 Input Floating VDDO GPIO: P7

P8 40 P8 Input Floating VDDO GPIO: P8

P9 17 P9 Input Floating VDDO GPIO: P9

P10 16 P10 Input Floating VDDO GPIO: P10

P11 15 P11 Input Floating VDDO GPIO: P11

P12 14 P12 Input Floating VDDO GPIO: P12

P13 13 P13 Input Floating VDDO GPIO: P13

P14 41 P14 Input Floating VDDO GPIO: P14

Pad

Number

Silicon

Pin Name

Direction

Default

POR State

Power

Domain

Default Alternate Function Description

A/D converter input 29 Note Not available during TM1 = 1.

A/D converter input 28

A/D converter input 27

A/D converter input 26

A/D converter input 25

A/D converter input 24

A/D converter input 23

A/D converter input 22

A/D converter input 21

Document Number: 002-28053 Rev. ** Page 10 of 47

CYBT-343052-02

Table 5. (continued)

Notes

4. The CYBT-343052-02 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface.

5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in Table .

Module pad

Name

P15 19 P15 Input Floating VDDO GPIO: P15

NA NA P16 Input Floating VDDO GPIO: P16

P26 6 P26 Input Floating VDDO GPIO: P26

P27 5 P27 Input Floating VDDO GPIO: P27

P28 12 P28 Input Floating VDDO GPIO: P28

P29 11 P29 Input Floating VDDO GPIO: P29

P32 4 P32 Input Floating VDDO GPIO: P32

P34 8 P34 Input Floating VDDO GPIO: P34

P38 7 P38 Input Floating VDDO GPIO: P38

NA NA P39 Input Floating VDDO Reserved for system use. Leave this GPIO unconnected

Pad

Number

Silicon

Pin Name

PWM0 Current: 16 mA sink

PWM1 Current: 16 mA sink

PWM2 A/D converter input 11

PWM3 A/D converter input 10

Direction

Default

POR State

Power

Domain

Default Alternate Function Description

A/D converter input 20

A/D converter input 19

Current: 16 mA sink

A/D converter input 7

A/D converter input 5

A/D converter input 1

Document Number: 002-28053 Rev. ** Page 11 of 47

CYBT-343052-02

Connections and Optional External Components

Power Connections (VDDIN)

The CYBT-343052-02 contains one power supply connection, VDDIN, which accepts a supply input range of 2.3 V to 3.6 V for CYBT-343052-02. Table 12 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 12.

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330 , 100 MHz.

Considerations and Optional Components for Brown Out (BO) Conditions

Power supply design must be completed to ensure that the CYBT-343052-02 module does not encounter a Brown Out condition, which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the following range:

VDDIN V

Refer to Table 13 for the VIL and V System design should ensure that the condition above is not encountered when power is removed from the system. In the event that

this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to

Figure 8 for the recommended circuit design when using an external voltage detection IC.

Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC

specifications.

In the event that the module does encounter a Brown Out condition, and is operating erratically or is not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition.

External Reset (XRES)

The CYBT-343052-02 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-343052-02 module (solder pad 3). The CYBT-343052-02 module resistor on the XRES input

During power-on operation, the XRES connection to the CYBT-343052-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:

■ The host device should connect a GPIO to the XRES of the Cypress CYBT-343052-02 module and pull XRES low until VDD is

stable. XRES is recommended to be released 50 ms after VDDIN is stable.

■ If the XRES connection of the CYBT-343052-02 module is not used in the application, a 10-µF capacitor may be connected to the

XRES solder pad of the CYBT-343052-02 to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms after VDDIN stability.

■ The XRES release timing may be controlled by an external voltage detection IC. XRES should be released 50 ms after VDD is stable.

Refer to Figure on page 18 for XRES operating and timing requirements during power-on events.

Document Number: 002-28053 Rev. ** Page 12 of 47

does not require an external pull-up

CYBT-343052-02

Multiple-Bonded GPIO Connections

The CYBT-343052-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used, only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio SDK. For details on the features and functions that each of these multiple-bonded GPIOs provide, refer to Table .

The following list details the multiple-bonded GPIOs available on the CYBT-343052-02 module:

■ PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available)

■ PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available)

■ PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available)

■ PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available)

■ PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available)

■ PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available)

■ PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available)

■ PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available)

■ PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available)

■ PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available)

■ PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available)

Document Number: 002-28053 Rev. ** Page 13 of 47

CYBT-343052-02

Figure 9 illustrates the CYBT-343052-02 schematic.

Figure 9. CYBT-343052-02 Schematic Diagram

Document Number: 002-28053 Rev. ** Page 14 of 47

CYBT-343052-02

Critical Components List

Ta bl e 6 details the critical components used in the CYBT-343052-02 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 60-pin QFN BT/BLE Silicon Device - CYW20735 Silicon U2 8-pin TDF8N, 512K Serial Flash

Crystal Y1 24.000 MHz, 12PF

Antenna Design

Ta bl e 7 details trace antenna used in the CYBT-343052-02 module. For more information, see Tab le 7 .

Table 7. Trace Antenna Specifications

Item Description

Frequency Range 2400–2500 MHz Peak Gain 0 dBi typical Return Loss 10-dB minimum

Document Number: 002-28053 Rev. ** Page 15 of 47

+ 32 hidden pages

Cypress Semiconductor 3052 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Module Description

Power Consumption

Functional Capabilities

Benefits

More Information

References

Development Environments

Technical Support

Contents

Overview

Functional Block Diagram

Module Description

Module Dimensions and Drawing

Pad Connection Interface

Recommended Host PCB Layout

Module Connections

Connections and Optional External Components

Power Connections (VDDIN)

Considerations and Optional Components for Brown Out (BO) Conditions

External Reset (XRES)

Multiple-Bonded GPIO Connections

Critical Components List

Antenna Design