Cypress Semiconductor 3047 User Manual
PRELIMINARY
CYBT-3330xx-02
EZ-BT™ WICED Module
General Description
Note
1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +9.0 dBm. Actual range will
vary based on end product design, environment, receive sensitity and transmit output power of the central deivce.
The CYBT-3330xx-02 is a fully integrated Bluetooth Smart
Ready wireless module. The CYBT-3330xx-02 includes an
onboard crystal oscillator, passive components, flash memory,
and the Cypress CYW20706 silicon device. Refer to the
CYW20706 datasheet for additional details on the capabilities of
the silicon device used in this module.
The CYBT-3330xx-02 supports peripheral functions (ADC and
PWM), UART, I2C, and SPI communication, and a PCM/I2S
audio interface. The CYBT-3330xx-02 includes a royalty-free
Bluetooth stack compatible with Bluetooth 5.0 in a 12.0 × 13.5 ×
1.95 mm package.
The CYBT-3330xx-02 includes 512 KB of onboard serial flash
memory and is designed for standalone operation. The
CYBT-3330xx-02 uses an integrated power amplifier to achieve
Class I or Class II output power capability.
The CYBT-3330xx-02 is offered in two certified versions. The
CYBT-333032-02 supports an external antenna through an RF
solder pad output. The CYBT-333047-02 supports an external
antenna via a u-FL connector.
Module Description
n Module size: 12.00 mm × 13.50 mm × 1.95 mm
n Bluetooth 5.0 Qualified Smart Ready module
p QDID: TBD
p Declaration ID: TBD
n Certified to FCC, ISED, MIC, and CE regulations
n Castelated solder pad connections for ease-of-use
n 512-KB on-module serial flash memory
n Up to 11 GPIOs
n Temperature range: –30 °C to +85 °C
n Cortex-M3 32-bit processor
n Maximum TX output power
p +12 dbm for Bluetooth Classic
p +9 dBm for Bluetooth Low Energy
• BLE connection range of up to 250 meters at 9 dBm
n RX Receive Sensitivity:
p Bluetooth Classic:
• –93.5 dBm at 1 Mbps, GFSK
• –95.5 dBm at 2 Mbps,
π/4-DQPSK
• –89.5 dBm at 3 Mbps, 8-DPSK
p –96.5 dBm for Bluetooth Low Energy
[1]
Power Consumption
n Enhanced Data Rate (EDR) at 8 dBm
p Peak TX current: 52.5 mA
p Peak RX current consumption: 26.4 mA
n Bluetooth Low Energy (BLE) at 0 dBm
p 1-second interval BLE ADV average current consumption:
315 uA
n Low power mode support
p Deep Sleep: 2.69 uA
Functional Capabilities
n Σ-Δ ADC for audio (12 bits) and DC measurement (10 bits)
n Serial Communications interface compatible with I
n Serial Peripheral Interface (SPI) support for both master and
2
C slaves
slave modes
n HCI interface through UART
n PCM/I2S Audio interface
n Two-wire Global Coexistence Interface (GCI)
n Integrated peripherals such as PWM, ADC
n Programmable output power control
n Supports extended synchronous connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets
n Bluetooth wideband speech support
Benefits
CYBT-3330xx-02 provides all necessary components required to
operate BLE and/or BR/EDR communication standards.
n Proven hardware design ready to use
n Dual-mode operation eliminates the need for multiple modules
n Cost optimized for applications without space constraints
n Nonvolatile memory for self-sufficient operation and
Over-the-air updates
n Bluetooth SIG Listed with QDID and Declaration ID
n Fully certified module eliminates the time needed for design,
development and certification processes
n WICED™ STUDIO provides an easy-to-use integrated design
environment (IDE) to configure, develop, and program a
Bluetooth application
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-25196 Rev. ** Revised September 18, 2018
PRELIMINARY
CYBT-3330xx-02
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
References
n Overview: EZ-BLE/BT Module Portfolio, Module Roadmap
n CYW20706 BT Silicon Datasheet
n Development Kits:
p CYBT-333047-EVAL, CYBT-333047-02 Evaluation Board
n Test and Debug Tools:
p CYSmart, Bluetooth
p CYSmart Mobile, Bluetooth
®
LE Test and Debug Tool (Windows)
®
LE Test and Debug Tool
(Android/iOS Mobile App)
n Knowledge Base Article
p KBA97095 - EZ-BLE™ Module Placement
p KBA213260- RF Regulatory Certifications for
CYBT-343026-01 EZ-BT™ WICED Modules
p KBA213976 - FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
p KBA210802 - Queries on BLE Qualification and Declaration
Processes
p KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
p KBA221025 - Platform Files for CYBT-343026-EVAL
p KBA223428 - Programming an EZ-BT WICED Module
Development Environments
Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)
Cypress' WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design.
WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development
environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also
leverages many common industry standards.
Technical Support
n Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress
Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers
around the world.
n Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.
n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-25196 Rev. ** Page 2 of 52
PRELIMINARY
CYBT-3330xx-02
Contents
Overview............................................................................ 4
Functional Block Diagram ........................................... 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 7
Module Connections ........................................................ 9
Connections and Optional External Components....... 10
Power Connections (VDDIN)..................................... 10
External Reset (XRES).............................................. 10
Multiple-Bonded GPIO Connections ......................... 11
Critical Components List ........................................... 13
Qualified Antenna for CYBT-3330xx-02 .................... 13
Functional Description................................................... 14
Bluetooth Baseband Core ......................................... 14
Microcontroller Unit ................................................... 16
External Reset (XRES).............................................. 17
Integrated Radio Transceiver........................................ 18
Transmitter Path........................................................ 18
Receiver Path............................................................ 18
Local Oscillator Generation....................................... 18
Calibration ................................................................. 18
Internal LDO.............................................................. 19
Collaborative Coexistence............................................. 19
Global Coexistence Interface ........................................ 19
SECI I/O .................................................................... 19
Peripheral and Communication Interfaces .................. 20
I2C Communication Interface.................................... 20
HCI UART Interface .................................................. 20
Peripheral UART Interface ........................................ 21
Serial Peripheral Interface......................................... 21
PCM Interface ........................................................... 21
Clock Frequencies.......................................................... 21
GPIO Port ........................................................................ 22
PWM................................................................................. 22
Power Management Unit................................................ 24
RF Power Management ............................................ 24
Host Controller Power Management ......................... 24
BBC Power Management.......................................... 24
Electrical Characteristics............................................... 25
Chipset RF Specifications ............................................. 27
Timing and AC Characteristics ..................................... 30
UART Timing............................................................. 30
SPI Timing.....................................................
I2C Interface Timing.................................................. 33
PCM Interface Timing................................................ 34
I2S Interface Timing .................................................. 38
Environmental Specifications ....................................... 41
Environmental Compliance ....................................... 41
RF Certification.......................................................... 41
Safety Certification .................................................... 41
Environmental Conditions ......................................... 41
ESD and EMI Protection ........................................... 41
Regulatory Information.................................................. 42
FCC........................................................................... 42
ISED.......................................................................... 43
European Declaration of Conformity ......................... 44
MIC Japan................................................................. 44
Packaging........................................................................ 45
Ordering Information...................................................... 47
Acronyms........................................................................ 48
Document Conventions ................................................. 50
Units of Measure ....................................................... 50
Document History Page................................................. 51
Sales, Solutions, and Legal Information...................... 52
Worldwide Sales and Design Support....................... 52
Products .................................................................... 52
PSoC® Solutions ...................................................... 52
Cypress Developer Community................................. 52
Technical Support ..................................................... 52
............ 31
Document Number: 002-25196 Rev. ** Page 3 of 52
PRELIMINARY
CYBT-3330xx-02
Overview
Functional Block Diagram
Figure 1 illustrates the CYBT-3330xx-02 functional block diagram.
Figure 1. Functional Block Diagram
Module Description
The CYBT-3330xx-02 module is a complete module designed to be soldered to the application’s main board.
Module Dimensions and Drawing
Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the
physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item Specification
Module dimensions
PCB thickness Height (H) 0.50 ± 0.05 mm
Shield height Height (H) 1.45 mm typical
Maximum component height Height (H) 1.45 mm typical
Total module thickness (bottom of module to highest component) Height (H) 1.95 mm typical
See Figure 2 for the mechanical reference drawing for CYBT-3330xx-02.
Length (X) 12.00 ± 0.15 mm
Width (Y) 13.50 ± 0.15 mm
Document Number: 002-25196 Rev. ** Page 4 of 52
PRELIMINARY
CYBT-3330xx-02
Figure 2. Module Mechanical Drawing
Bottom View
Side View
Top View (Seen from Top)
Notes
2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.
3. The CYBT-3330xx-02 includes castellated pad connections, denoted as the circular openings at the pad location above.
Document Number: 002-25196 Rev. ** Page 5 of 52
PRELIMINARY
CYBT-3330xx-02
Pad Connection Interface
As shown in the bottom view of Figure 2 on page 5, the CYBT-3330xx-02 connects to the host board via solder pads on the backside
of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-3330xx-02 module.
Table 2. Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 26 Solder Pads 1.02 mm 0.71 mm 1.22 mm
Figure 3. Solder Pad Dimensions (Seen from Bottom
Document Number: 002-25196 Rev. ** Page 6 of 52
PRELIMINARY
CYBT-3330xx-02
Recommended Host PCB Layout
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Figure 4, Figure 5, Figure 6, and Tabl e 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBT-3330xx-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. CYBT-3330xx-02 Host Layout (Dimensioned) Figure 5. CYBT-3330xx-02 Host Layout (Relative to Origin)
Document Number: 002-25196 Rev. ** Page 7 of 52
PRELIMINARY
CYBT-3330xx-02
Ta bl e 3 provides the center location for each solder pad on the CYBT-3330xx-02. All dimensions are referenced to the center of the
Top View (Seen on Host PCB)
solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location
Solder Pad
(Center of Pad)
1 (0.38, 3.02) (14.96, 118.90)
2 (0.38, 4.24) (14.96, 166.93)
3 (0.38, 5.46) (14.96, 214.96)
4 (0.38, 6.68) (14.96, 262.99)
5 (0.38, 7.90) (14.96, 311.02)
6 (0.38, 9.12) (14.96, 359.05)
7 (0.38, 10.34) (14.96, 407.09)
8 (0.38, 11.56) (14.96, 455.12)
9 (1.73, 13.09) (68.11, 515.35)
10 (2.95, 13.09) (116.14, 515.35)
11 (4.17, 13.09) (164.17, 515.35)
12 (5.39, 13.09) (212.20, 515.35)
13 (6.61, 13.09) (260.24, 515.35)
14 (7.83, 13.09) (308.27, 515.35)
15 (9.05, 13.09) (356.30, 515.35)
16 (10.27, 13.09) (404.33, 515.35)
17 (11.62, 11.56) (457.48, 455.12)
18 (11.62, 10.34) (457.48, 407.09)
19 (11.62, 9.12) (457.48, 359.05)
20 (11.62, 7.90) (457.48, 311.02)
21 (11.62, 6.68) (457.48, 262.99)
22 (11.62, 5.46) (457.48, 214.96)
23 (11.62, 4.24) (457.48, 166.93)
24 (11.62, 3.02) (457.48, 118.90)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
Document Number: 002-25196 Rev. ** Page 8 of 52
PRELIMINARY
CYBT-3330xx-02
Module Connections
Note
4. The CYBT-3330xx-02 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface.
5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in the table above.
Ta bl e 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-3330xx-02 module.
Ta bl e 4 lists the CYBT-3330xx-02 solder pads, the silicon device pin, and denotes what functions are available for each solder pad.
Table 4. CYBT-3330xx-02 Solder Pad Connection Definitions
Pad Name
Pad
1P0/P34 C8
2 I2C_SCL A8
3XRES
4 I2C_SDA C7
5 P2/P37/P28 B7
6 SPI2_CS_N D7 N/A No Connect (Used for on-module memory SPI interface for CYBT-3330xx-02)
7 GND GND GND Ground
8 SPI2_MISO D8 N/A No Connect (Used for on-module memory SPI interface for CYBT-3330xx-02)
9 SPI2_MOSI E8 N/A No Connect (Used for on-module memory SPI interface for CYBT-3330xx-02)
10 SPI2_CLK E7 N/A No Connect (Used for on-module memory SPI interface for CYBT-3330xx-02)
11 GPI O_0 F8
12 GPIO_1 F7
13 GND GND GND Ground
14 GPIO_4 D6
15 P4/P24 G8
16 UART_TXD F4 BT_UART_TXD HCI UART Transmit Data
17 UART_CTS G4 BT_UART_CTS HCI UART Clear To Send Input
18 UART_RTS F3 BT_UART_RTS HCI UART Request To Send Output
19 GPIO_7 C6
20 UART_RXD F5 BT_UART_RXD HCI UART Receive Data
21 VDDIN G1 VDDIN VDDIN (2.3V ~ 3.6V)
22 GPIO_3 C5
23 GPIO_6 B6
24 GND GND GND Ground
25 GND GND GND Ground - Only functional for CYBT-333032-02; No Connect for CYBT-333047-02
26 ANT A2 RFOP RF Antenna Port Input/Output - Only functional for CYBT-333032-02; No Connect for CYBT-333047-02
Silicon
Pin
Name
RESET
_N
Silicon
Port-Pin Name
PCM_Sync/
I2S_WS/P0/P34
I2S_DO/
PCM_Out/P3/
P29/P35
RESET_N External Reset (Active Low)
PCM_IN/
I2S_DI/P12
PCM_CLK/
I2S_CLK/P2/
P28/P37
BT_GPIO_0/
P36/P38
BT_GPIO_1/
P25/P32
BT_GPIO_4/P6/
P31/LPO_IN
BT_CLK_REQ/
P4/P24
BT_GPIO_7/
P30
BT_GPIO_3/
P27/P33
BT_GPIO_6/
P11/P26
UART SPI
PUART_TX/P0
PUART_RX/P34
PUART_CTS/
P3 or P35
PUART_RX/P2
PUART_RX/P25
PUART_TX/P32
PUART_RTS/P6
PUART_TX/P31
PUART_RX/P4
PUART_TX/P24
PUART_RTS/
P30
PUART_RX/P33
SPI1_CS(slave)/P2
SPI1_MOSI(master)/P2
SPI1_MISO(slave)/P37
[4,5]
SPI1_MOSI/P0
(master/slave)
SPI1_CLK/P3
(master/slave)
SPI1_CLK/P36
SPI1_MOSI/P38
(master/slave)
SPI1_MISO/P25
(master/slave)
SPI1_CS/P32
(slave)
SPI1_CS/P6
(slave)
SPI1_MOSI/P4
(master/slave)
SPI1_CLK/P24
(master/slave)
SPI1_MOSI/P27
(master/slave)
SPI1_MOSI/P33
(slave)
SPI1_CS/P26
(slave)
I2C ADC COEX
IN29/P0
IN5/P34
SCL
IN4/P35
SDA/
IN10/29
P35
SDA IN23/P12
SCL/
IN11/P28
P37
IN2/P37
IN3/P36
IN1/P38
IN7/P32
IN8/P31 3
IN9/P30
IN6/P33
IN24/P11
3(GCI_SE
CI_OUT)
3(GCI_SE
CI_IN)
CLK/
XTAL
ACLK1
/P37
ACLK0
/P36
ACLK0
/P32
ACLK1
/P33
GPIO
3 PCM_Sync
3
(P3/P29
/P35)
3
(P12)
3
3
(DevWa
ke)
3
(HostWa
ke)
3
(CLK_R
EQ)
3
3
3
I2S_WS
I2S_DO
PCM_Out
PWM3 (P29)
PCM_IN
PWM2 (P28)
I2S_CLK
PCM_CLK
Ext LPO In
PWM1 (P27)
PWM0 (P26)
Other
I2S_DI
Document Number: 002-25196 Rev. ** Page 9 of 52
PRELIMINARY
CYBT-3330xx-02
Connections and Optional External Components
Power Connections (VDDIN)
The CYBT-3330xx-02 contains one power supply connection, VDDIN. VDDIN accepts a supply input range of 2.3 V to 3.6 V for
CYBT-3330xx-02. Ta b le 11 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as
shown in Table 11.
It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned
as close as possible to the module pin connection and the recommended ferrite bead value is 330 Ω, 100 MHz.
Considerations and Optional Components for Brown Out (BO) Conditions
Power supply design must be completed to ensure that the CYBT-3330xx-02 module does not encounter a Brown Out condition,
which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the
module during power up or reset is in the following range:
V
≤ VDDIN ≤ V
IL
Refer to Table 12 for the VIL and V
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that
this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an
external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to
Figure 7 for the recommended circuit design when using an external voltage detection IC.
Figure 7. Reference Circuit Block Diagram for External Voltage Detection IC
specifications.
IH
IH
In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the
module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues
that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition.
External Reset (XRES)
The CYBT-3330xx-02 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This
action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,
which is an input to the CYBT-3330xx-02 module (solder pad 3). The CYBT-3330xx-02 module
resistor on the XRES input
During power-on operation, the XRES connection to the CYBT-3330xx-02 is required to be held low 50 ms after the VDD power supply
input to the module is stable. This can be accomplished in the following ways:
n The host device should connect a GPIO to the XRES of the Cypress CYBT-3330xx-02 module and pull XRES low until VDD is
stable. XRES is recommended to be released 50 ms after VDDIN is stable.
n If the XRES connection of the CYBT-3330xx-02 module is not used in the application, a 10-µF capacitor may be connected to the
XRES solder pad of the CYBT-3330xx-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The capacitor
value should result in an XRES release timing of 50 ms after VDDIN stability.
n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.
Refer to Figure 10 on page 17 for XRES operating and timing requirements during power-on events.
Document Number: 002-25196 Rev. ** Page 10 of 52
does not require an external pull-up
PRELIMINARY
CYBT-3330xx-02
Multiple-Bonded GPIO Connections
The CYBT-3330xx-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used,
only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED
Studio SDK. For details on the features and functions that each of these multiple-bonded GPIOs provide, refer to Table 4.
The list below details the multiple-bonded GPIOs available on the CYBT-3330xx-02 module:
n PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available)
n PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available)
n PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available)
n PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available)
n PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available)
n PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available)
n PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available)
n PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available)
n PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available)
n PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available)
n PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available)
Document Number: 002-25196 Rev. ** Page 11 of 52
PRELIMINARY
CYBT-3330xx-02
Figure 8 illustrates the CYBT-3330xx-02 schematic.
Figure 8. CYBT-3330xx-02 Schematic Diagram
Document Number: 002-25196 Rev. ** Page 12 of 52
PRELIMINARY
CYBT-3330xx-02
Critical Components List
Ta bl e 5 details the critical components used in the CYBT-3330xx-02 module.
Table 5. Critical Component List
Component Reference Designator Description
Silicon U1 49-pin FBGA BT/BLE Silicon Device - CYW20706
Silicon U2 8-pin TDF8N, 512K Serial Flash
Crystal Y1 24.000 MHz, 12PF
Qualified Antenna for
The CYBT-3330xx-02 module has been designed to work with a standard 2.2 dBi dipole antenna. Any antenna of equivalent or less
gain can be used without additional application and testing for FCC regulations. Ta b le 6 details the approved antennas for the
CYBT-3330xx-02 module for Bluetooth operation.
Table 6. Qualified Antennas
Manufacturer Part Number Gain
Antenova B4844-01 2.2 dBi
Pulse W1030 2.0 dBi
* Cable loss (between antenna and module) is 1 dB
CYBT-3330xx-02
Document Number: 002-25196 Rev. ** Page 13 of 52
PRELIMINARY
CYBT-3330xx-02
Functional Description
Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and
packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition
to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions
are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:
n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
Table 7. Bluetooth Features
Bluetooth 1.0 Bluetooth 1.2 Bluetooth 2.0
Basic Rate Interlaced Scans EDR 2 Mbps and 3 Mbp
SCO Adaptive Frequency Hopping –
Paging and Inquiry eSCO –
Page and Inquiry Scan – –
Sniff – –
Bluetooth 2.1 Bluetooth 3.0 Bluetooth 4.0
Secure Simple Pairing Unicast Connectionless Data Bluetooth Low Energy
Enhanced Inquiry Response Enhanced Power Control –
Sniff Subrating eSCO –
Bluetooth 4.1 Bluetooth 4.2
Low Duty Cycle Advertising Data Packet Length Extension
Dual Mode LE Secure Connection
LE Link Layer Topology Link Layer Privacy
Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth
Link Controller.
n States:
p Standby
p Connection
p Page
p Page Scan
p Inquiry
p Inquiry Scan
p Sniff
p Advertising
p Scanning
Document Number: 002-25196 Rev. ** Page 14 of 52
PRELIMINARY
CYBT-3330xx-02
Test Mode Support
The CYBT-3330xx-02 fully supports Bluetooth Test mode as described in
Part I:1 of the Specification of the Bluetooth System Version
3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYBT-3330xx-02 also supports enhanced testing features to simplify RF
debugging and qualification and type-approval testing. These features include:
n Fixed frequency carrier wave (unmodulated) transmission
p Simplifies some type-approval measurements (Japan)
p Aids in transmitter performance analysis
n Fixed frequency constant receiver mode
p Receiver output directed to I/O pin
p Allows for direct BER measurements using standard RF test equipment
p Facilitates spurious emissions testing for receive mode
n Fixed frequency constant transmission
p 8-bit fixed pattern or PRBS-9
p Enables modulated signal measurements with standard RF test equipment.
Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth
clock, and device address.
Document Number: 002-25196 Rev. ** Page 15 of 52
PRELIMINARY
CYBT-3330xx-02
Microcontroller Unit
The microprocessor unit in CYBT-3330xx-02 runs software from the link control (LC) layer up to the host controller interface (HCI).
The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The
microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and
patch RAM code.
The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At
power-up, the lower layer protocol stack is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches
can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an
external serial flash memory.
NVRAM Configuration Data and Storage
NVRAM contains configuration information about the customer application, including the following:
n Fractional-N information
n BD_ADDR
n UART baud rate
n SDP service record
n File system information used for code, code patches, or data. The CYBT-3330xx-02 uses SPI Serial Flash for NVRAM storage.
One-Time Programmable Memory
The microprocessor unit in CYBT-3330xx-02 includes 2 KB of one-time programmable (OTP) memory allow manufacturing customization and to avoid the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed.
Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to
store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after
the CYBT-3330xx-02 boots and is ready for host transport communication.
The OTP contents are limited to:
n Parameters required prior to downloading the user configuration to RAM.
n Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key).
n VDDIN for the module must be kept to 3.0 V to 3.6 V power supply range if OTP is used in the application.
Document Number: 002-25196 Rev. ** Page 16 of 52
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