Cypress Semiconductor 3043 User Manual

PRELIMINARY

CYBT-213043-02

EZ-BT™ Module

General Description

The CYBT-213043-02 is a dual-mode Bluetooth BR/EDR and
Low Energy (BLE) wireless module solution. The
CYBT-213043-02 includes an onboard crystal oscillator, passive
components, and the Cypress CYW20819 silicon device.

The CYBT-213043-02 supports a number of peripheral functions
(ADC, PWM), as well as multiple serial communication protocols
(UART, SPI, I
royalty-free stack compatible with Bluetooth 5.0 in a 12.0 × 16.61
× 1.70 mm module form-factor.

The CYBT-213043-02 includes an integrated PCB trace
antenna, is qualified by Bluetooth SIG, and includes regulatory
certification approval for FCC, ISED, MIC, and CE.

Module Description

■ Module size: 12.00 mm × 16.61 mm × 1.70 mm

■ Complies with Bluetooth Core Specification version 5.0 and

includes support for BR, EDR 2/3 Mbps, eSCO, BLE, LE
2 Mbps, as well as Bluetooth Mesh.

❐ QDID: TBD
❐ Declaration ID: TBD

■ Certified to FCC, ISED, MIC, and CE standards

■ 256-KB on-chip Flash, 176-KB on-chip RAM

■ Industrial temperature range: –30 °C to +85 °C

■ Integrated Arm

floating point unit (FPU)

RF Characteristics

■ Maximum TX output power: +4.0 dBm

■ BLE RX Receive Sensitivity: –95.0 dBm

2

C, I2S/PCM). The CYBT-213043-02 includes a

®

Cortex®-M4 microprocessor core with

Functional Capabilities

■ Up to 22 GPIOs

2

■ I

C, I2S, UART, and PCM interfaces

■ Two Quad-SPI interfaces

■ Auxiliary ADC with up to 15 analog channels

■ Programmable key scan 20 × 8 matrix

■ General-purpose timers and PWM

■ Real-time clock (RTC) and watchdog timers (WDT)

■ Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR)

Support

■ BLE protocol stack supporting generic access profile (GAP)

Central, Peripheral, or Broadcaster roles

■ Hardware Security Engine

Benefits

CYBT-213043-02 is fully integrated and certified solution that
provides all necessary components required to operate
Bluetooth communication standards.

■ Proven hardware design ready to use

■ Ultra-flexible supermux I/O design allows maximum flexibility

for GPIO function assignment

■ Over-the-air update capable for development or field updates

■ Bluetooth SIG qualified.

■ ModusToolbox™ provides an easy-to-use integrated design

environment (IDE) to configure, develop, program, and test
your Bluetooth application

Power Consumption

■ TX current consumption
❐ BLE silicon: 5.8 mA (radio only, 4 dBm)

■ RX current consumption
❐ Bluetooth silicon: 5.9 mA (radio only)

■ Cypress CYW20819 silicon low power mode support
❐ PDS: 16.5 A with 176 KB RAM retention

❐ ePDS: 8.7 A
❐ HIDOFF (External Interrupt): 1.75 A

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-26540 Rev. ** Revised February 21, 2019

PRELIMINARY

CYBT-213043-02

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.

References

■ Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap

■ Development Kits:
❐ CYBT-213043-EVAL, CYBT-213043-02 Evaluation Board
❐ CYBT-213043-MESH, Mesh Evaluation Kit

❐ CYW920819Q40EVB-01, Evaluation Kit for CYW20819

silicon device

■ Test and Debug Tools:
❐ CYSmart, Bluetooth

❐ CYSmart Mobile, Bluetooth

®

LE Test and Debug Tool (Windows)

®

LE Test and Debug Tool

(Android/iOS Mobile App)

■ Knowledge Base Article
❐ KBA97095 - EZ-BLE™ Module Placement

❐ RF Regulatory Certifications for CYBT-213034-02 EZ-BT

WICED Modules (TBD)

❐ KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐ KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
❐ KBA223428 - Programming an EZ-BT WICED Module
❐ KBA225450 - Putting 2073x, 2070x, and 20719 Based De-

vices or Modules in HCI Mode

Development Environments

ModusToolbox Integrated Development En viro nme nt (IDE)

ModusToolbox simplifies development for IoT designers. It delivers easy-to-use tools and a familiar microcontroller (MCU) integrated

development environment (IDE) for Windows
wireless connectivity libraries, power analysis, application-specific configurators for Bluetooth
well as other peripherals.

In addition, code examples, documentation, technical support and community forums are available to help your IoT development
process along. These tools and features enable an IoT designer to develop innovative IoT applications efficiently and with ease.

®

, macOS®, and Linux®. It provides a sophisticated environment for system setup,

®

Low Energy (BLE), CapSense®, as

Technical Support

■ Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share, and engage with both Cypress experts and other embedded engineers
around the world.

■ Frequently Asked Questions (FAQs): Learn more about our Bluetooth ecosystem.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: [phone]. Select option 2 at the prompt.

Document Number: 002-26540 Rev. ** Page 2 of 45

PRELIMINARY

CYBT-213043-02

Contents

Overview............................................................................ 4

Functional Block Diagram ........................................... 4

Module Description...................................................... 4

Pad Connection Interface ................................................ 6

Recommended Host PCB Layout ................................... 7

Module Connections ........................................................ 9

Connections and Optional External Components ..... 11

Power Connections (VDD) ........................................ 11

External Reset (XRES).............................................. 11

HCI UART Connections ............................................ 11

External Component Recommendation .................... 11

Critical Components List ...........................................13

Antenna Design......................................................... 13

Bluetooth Baseband Core ............................................. 14

BQB and Regulatory Testing Support....................... 14

Power Management Unit................................................ 15

Integrated Radio Transceiver........................................ 16

Transmitter Path........................................................ 16

Receiver Path............................................................ 16

Local Oscillator.......................................................... 16

Microcontroller Unit ....................................................... 17

External Reset........................................................... 17

32-kHz Crystal Oscillator........................................... 17

Power Modes ............................................................ 18

Firmware ................................................................... 18

Peripherals and Communication Interfaces ................ 19

I2C............................................................................. 19

HCI UART Interface .................................................. 19

Peripheral UART Interface ........................................ 19

Serial Peripheral Interface......................................... 19

ADC Port ................................................................... 20

GPIO Port.................................................................. 20

PWM.......................................................................... 21

PDM Microphone....................................................... 21

I2S Interface ..............................................................22

PCM Interface ........................................................... 22

Electrical Characteristics............................................... 23

Current Consumption ................................................ 24

Silicon Core Buck Regulator ..................................... 24

Digital LDO................................................................ 25

RF LDO ..................................................................... 25

Digital I/O Characteristics.......................................... 26

ADC Characteristics.................................................. 26

Chipset RF Specifications ............................................. 28

Timing and AC Characteristics ..................................

UART Timing............................................................. 30

SPI Timing................................................................. 31

I2C Compatible Interface Timing............................... 33

I2S Interface Timing .................................................. 34

Environmental Specifications ....................................... 36

Environmental Compliance ....................................... 36

RF Certification.......................................................... 36

Safety Certification .................................................... 36

Environmental Conditions ......................................... 36

ESD and EMI Protection ........................................... 36

Regulatory Information.................................................. 37

FCC........................................................................... 37

ISED.......................................................................... 38

European Declaration of Conformity ......................... 39

MIC Japan................................................................. 39

Packaging........................................................................ 40

Ordering Information...................................................... 42

Acronyms........................................................................ 43

Document Conventions ................................................. 43

Units of Measure ....................................................... 43

Document History Page................................................. 44

Sales, Solutions, and Legal Information...................... 45

Worldwide Sales and Design Support....................... 45

Products .................................................................... 45

PSoC® Solutions ...................................................... 45

Cypress Developer Community................................. 45

Technical Support ..................................................... 45

... 30

Document Number: 002-26540 Rev. ** Page 3 of 45

PRELIMINARY

CYBT-213043-02

Overview

Functional Block Diagram

Figure 1 illustrates the CYBT-213043-02 functional block diagram.

Figure 1. Functional Block Diagram

Note: General Purpose Input/Output pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Tab le 5 in the Module

Connections section.

Note: Connections shown in Figure 1 are maximum number of connections per function. The total number of GPIOs available on the CYBT-213043-02 is 22.

Module Description

The CYBT-213043-02 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. The CYBT-213043-02 will be held within
the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions

PCB thickness Height (H) 0.50 ± 0.10 mm
Shield height Height (H) 1.20 mm typical
Maximum component height Height (H) 0.80 mm typical
Total module thickness (bottom of module to top of shield) Height (H) 1.70 mm typical

See Figure 2 for the mechanical reference drawing for CYBT-213043-02.

Length (X) 12.00 ± 0.15 mm

Width (Y) 16.61 ± 0.15 mm

Length (X) 12.00 mm

Width (Y) 4.55 mm

Document Number: 002-26540 Rev. ** Page 4 of 45

PRELIMINARY

CYBT-213043-02

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (Seen from Top)

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on the
recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

Document Number: 002-26540 Rev. ** Page 5 of 45

PRELIMINARY

CYBT-213043-02

Pad Connection Interface

Solder Pad Connections

(Seen from Bottom)

Optional Host PCB Keep

Out Area Around PCB An-

tenna

(Seen from Bottom)

As shown in the bottom view of Figure 2 on page 5, the CYBT-213043-02 has 28 connections to a host board via solder pads (SP).

Ta bl e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-213043-02 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 35 Solder Pad 1.02 mm 0.61 mm 0.90 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB antenna
located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to

AN96841 for module placement best practices.

3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB antenna may
contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the
host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).

Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-213043-02 PCB Antenna

Document Number: 002-26540 Rev. ** Page 6 of 45

PRELIMINARY

CYBT-213043-02

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure 7, and Ta bl e 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBT-213043-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.633 mm from center of the pad
on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-213043-02 Host Layout (Dimensioned) Figure 6. CYBT-213043-02 Host Layout (Relative to Origin)

Document Number: 002-26540 Rev. ** Page 7 of 45

PRELIMINARY

CYBT-213043-02

Ta bl e 3 provides the center location for each solder pad on the CYBT-213043-02. All dimensions are referenced to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure 7 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location

Solder Pad

(Center of Pad)

1 (0.38, 4.85) (14.96, 190.94)
2 (0.38, 5.75) (14.96, 226.38)
3 (0.38, 6.65) (14.96, 261.81)
4 (0.38, 7.56) (14.96, 297.64)
5 (0.38, 8.46) (14.96, 333.07)
6 (0.38, 9.36) (14.96, 368.50)
7 (0.38, 10.26) (14.96, 403.94)
8 (0.38, 11.16) (14.96, 439.37)

9 (0.38, 12.07) (14.96, 475.20)
10 (0.38, 12.97) (14.96, 510.63)
11 (0.38, 13.87) (14.96, 546.06)
12 (0,38, 14.77) (14.96, 581.49)
13 (1.49, 16.23) (58.66, 638.98)
14 (2.39, 16.23) (94.09, 638.98)
15 (3.30, 16.23) (129.92, 638.98)
16 (4.20, 16.23) (165.35, 638.98)
17 (5.10, 16.23) (200.79, 638.98)
18 (6.00, 16.23) (236.22, 638.98)
19 (6.90, 16.23) (271.65, 638.98)
20 (7.80, 16.23) (307.09, 638.98)
21 (8.71, 16.23) (342.91, 638.98)
22 (9.61, 16.23) (378.35, 638.98)
23 (10.51, 16.23) (413.78, 638.98)
24 (11.62, 14.47) (457.48, 581.49)
25 (11.62, 13.87) (457.48, 546.06)
26 (11.62, 12.97) (457.48, 510.63)
27 (11.62, 12.07) (457.48, 475.20)
28 (11.62, 11.16) (457.48, 439.37)
29 (11.62, 10.26) (457.48, 403.94)
30 (11.62, 9.36) (457.48, 368.50)
31 (11.62, 8.46) (457.48, 333.07)
32 (11.62, 7.56) (457.48, 297.64)
33 (11.62, 6.65) (457.48, 261.81)
34 (11.62, 5.75) (457.48, 226.38)
35 (11.62, 4.85) (457.48, 190.94)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

Document Number: 002-26540 Rev. ** Page 8 of 45

PRELIMINARY

CYBT-213043-02

Module Connections

Note

2. The CYBT-213043-02 can configure GPIO connections to any Input/Output function described in Tab l e 5 using the ModusToolbox Device Configurator.

Ta bl e 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available

on the CYBT-213043-02 can be configured to any of the input or output functions listed in Table 5 . Table 4 specifies any function that
is required to be used on a specific solder pad, and also identifies SuperMux capable GPIOs that can be configured using the
ModusToolbox device configurator.

Table 4. CYBT-213043-02 Solder Pad Connection Definitions

Pad Pad Name Silicon Pin Name XTALI/O ADC GPIO SuperMux Capable

1 GND GND Ground
2 VDD VDDIO Power Supply Input (1.71V ~ 3.63V)
3 XRES RST_N External Reset (Active Low)
4 P29 P29 - IN10 ✓✓ see Table 5
5P32 P32 - IN7 ✓✓ see Table 5
6P27 P27 - - ✓✓ see Table 5
7P37 P37 - IN2 ✓✓ see Table 5
8P28 P28 - IN11 ✓✓ see Table 5

9P0 P0 - IN29 ✓✓ see Table 5
10 P1 P1 - IN28 ✓✓ see Table 5
11 P 10 P1 0 - IN 25 ✓✓ see Table 5
12 P13 P13 - IN22 ✓✓ see Table 5
13 GND GND Ground
14 P12 P12 - IN23 ✓✓ see Table 5
15 P11 P11 - IN24 ✓✓ see Table 5
16 P9 P9 - IN26 ✓✓ see Table 5
17 P14 P14 - IN21 ✓✓ see Table 5
18 P17 P17 - IN18 ✓✓, see Ta bl e 5
19 P5 P5 - - ✓✓ see Table 5
20 P6 P6 - - ✓✓ see Table 5
21 P4 P4 - - ✓ ✓ see Table 5
22 P2 P2 - - ✓✓ see Table 5
23 P3 P3 - - ✓✓ see Table 5

24 XTALI_32K XTALI_32K

25 XTALO_32K XTALO_32K

26 P15 P15 - IN20 ✓✓ see Table 5
27 P8 P8 - IN27 ✓✓ see Table 5
28 UART_CTS_N UART_CTS_N UART (HCI UART) Clear To Send Input Only
29 UART_RTS_N UART_RTS_N UART (HCI UART) Request To Send Output Only
30 UART_TXD UART_TXD UART (HCI UART) Transmit Data Only
31 UART_RXD UART_RXD UART (HCI UART) Receive Data Only

32 HOST_WAKE HOST_WAKE

33 DEV_WAKE DEV_WAKE
34 P26 P26 - - ✓✓ see Table 5
35 GND GND Ground

External Oscillator Input

(32KHz)

External Oscillator

Output (32KHz)

A signal from the CYBT-213043-02 module to the host indicating that the Bluetooth device requires

A signal from the host to the CYBT-213043-02 module indicating that the host requires attention.

-- -

-- -

attention.

[2]

Document Number: 002-26540 Rev. ** Page 9 of 45

PRELIMINARY

CYBT-213043-02

Ta bl e 5 details the available Input and Output functions that are configurable to any solder pad in Table 4 that are marked as SuperMux

capable.

Table 5. GPIO SuperMux Input and Output Functions

Function Input or Output Function Type GPIOs Required Function Connection Description

SPI 1 Clock

SPI 1 Chip Select

SPI 1 Input/Output

SPI 2 Input/Output

Input Serial Communication Input

PUART

Output Serial Communication Output

2

C Input/Output

I

PCM In Input Audio Input Communication 3

PCM Out Output Audio Output Communication 3

2

S In Input Audio Input Communication 3

I

2

S Out Output Audio Output Communication 3

I

PDM Input Microphone 1 ~ 2

PWM Output Pulse Width Modulator 1 ~ 6

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

Serial Communication

(Master or Slave)

4 ~ 7

4 ~ 7

4

2

SPI 1 MOSI

SPI 1 MISO
SPI 1 I/O 2 (Quad SPI)
SPI 1 I/O 3 (Quad SPI)

SPI 1 Interrupt

SPI 2 Clock

SPI 2 Chip Select

SPI 2 MOSI

SPI 2 MISO
SPI 2 I/O 2 (Quad SPI)
SPI 2 I/O 3 (Quad SPI)

SPI 2 Interrupt

Peripheral UART RX

Peripheral UART CTS

Peripheral UART TX

Peripheral UART RTS

I2C Clock

I2C Data

PCM Input

PCM Clock

PCM Sync

PCM Output

PCM Clock

PCM Sync

I2S DI, Data Input

I2S WS, Word Select

I2S Clock
I2S DO, Data Output
I2S WS, Word Select

I2S Clock

PDM Input Channel 1
PDM Input Channel 2

PWM Channel 0
PWM Channel 1
PWM Channel 2
PWM Channel 3
PWM Channel 4
PWM Channel 5

Document Number: 002-26540 Rev. ** Page 10 of 45

PRELIMINARY

CYBT-213043-02

Connections and Optional External Components

Power Connections (VDD)

The CYBT-213043-02 contains one power supply connection, VDD. VDD accepts a supply input of 1.71 V to 3.63 V. Ta bl e 1 2 provides
this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Tab l e 1 2 .

External Reset (XRES)

The CYBT-213043-02 has an integrated power-on reset circuit which completely resets all circuits to a known power-on state. This
action can also be invoked by an external reset signal, forcing it into a power-on reset state. XRES is an active-low input signal on
the CYBT-213043-02 module (solder pad 3). The CYBT-213043-02 does not require external pull-up resistors on the XRES input
Refer to Figure 10 on page 17 for Power On and XRES operation and timing requirements during power on events.

HCI UART Connections

The recommendations in this section apply to the HCI UART (Solder Pads 28, 29, 30, and 31). For full UART functionality, all UART
signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired
or capable, then the following connection considerations should be followed for UART RTS and CTS:

■ UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.

■ UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the

module.

External Component Recommendation

Power Supply Circuitry

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to the
module pad connection.

If used, the recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D).

Document Number: 002-26540 Rev. ** Page 11 of 45

PRELIMINARY

CYBT-213043-02

Figure 8 illustrates the CYBT-213043-02 schematic.

Figure 8. CYBT-213043-02 Schematic Diagram

Document Number: 002-26540 Rev. ** Page 12 of 45

PRELIMINARY

CYBT-213043-02

Critical Components List

Ta bl e 6 details the critical components used in the CYBT-213043-02 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 62-pin QFN Bluetooth Silicon Device - CYW20819
Crystal Y1 24.000 MHz, 8PF

Antenna Design

Ta bl e 7 details the PCB trace antenna used in the CYBT-213043-02 module.

Table 7. PCB Antenna Specifications

Item Description

Frequency Range 2400–2500 MHz
Peak Gain –0.5 dBi typical
Return Loss 10 dB minimum

Document Number: 002-26540 Rev. ** Page 13 of 45

PRELIMINARY

CYBT-213043-02

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The
BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities
including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host
controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward
error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and
data whitening/dewhitening.

Table 8. Bluetooth Features

Bluetooth 1.0 Bluetooth 1.2 Bluetooth 2.0

Basic Rate Interlaced Scans EDR 2 Mbps and 3 Mbps
SCO Adaptive Frequency Hopping –
Paging and Inquiry eSCO –
Page and Inquiry Scan – –
Sniff – –

Bluetooth 2.1 Bluetooth 3.0 Bluetooth 4.0

Secure Simple Pairing Unicast Connectionless Data Bluetooth Low Energy
Enhanced Inquiry Response Enhanced Power Control –
Sniff Subrating eSCO –

Bluetooth 4.1 Bluetooth 4.2 Bluetooth 5.0

Low Duty Cycle Advertising Data Packet Length Extension LE 2 Mbps
Dual Mode LE Secure Connection Slot Availability Mask
LE Link Layer Topology Link Layer Privacy High Duty Cycle Advertising

BQB and Regulatory Testing Support

The CYBT-213043-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version

3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYBT-213043-02 also supports enhanced testing features to simplify RF

debugging and qualification and type-approval testing. These features include:

■ Fixed frequency carrier wave (unmodulated) transmission
❐ Simplifies some type-approval measurements (Japan)

❐ Aids in transmitter performance analysis

■ Fixed frequency constant receiver mode
❐ Receiver output directed to I/O pin
❐ Allows for direct BER measurements using standard RF test equipment

❐ Facilitates spurious emissions testing for receive mode

■ Fixed frequency constant transmission
❐ 8-bit fixed pattern or PRBS-9

❐ Enables modulated signal measurements with standard RF test equipment

Document Number: 002-26540 Rev. ** Page 14 of 45

PRELIMINARY

CYBT-213043-02

Power Management Unit

Figure 9 shows the CYW20819 power management unit (PMU) block diagram. The CYW20819 includes an integrated buck regulator,

a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck
once V

The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.

supply falls below 2.1 V.

bat

Figure 9. Default Usage Mode

Document Number: 002-26540 Rev. ** Page 15 of 45

PRELIMINARY

CYBT-213043-02

Integrated Radio Transceiver

The CYBT-213043-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally
available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the require­ments to provide the highest communication link quality of service.

Transmitter Path

CYBT-213043-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYBT-213043-02 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in
the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-213043-02 to be
used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYBT-213043-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the
controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether
the transmitter should increase or decrease its output power.

Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the band. The CYBT-213043-02 uses an internal
loop filter.

Document Number: 002-26540 Rev. ** Page 16 of 45

PRELIMINARY

CYBT-213043-02

Microcontroller Unit

The CYBT-213043-02 includes a Cortex-M4 processor with 1 MB of program ROM, 160 KB of data RAM, 16 KB of patch RAM, and
256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code
execution from flash at near maximum speed and low power consumption.

The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack
layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.

External Reset

Figure 10 shows power on and reset timing of the CYBT-213043-02. After VBAT is applied and reset is inactive, the internal buck

turns on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows the digital core to come out of
reset. As shown in the figure, external reset can be applied at any time subsequent to power up.

Figure 10. Reset Timing

32-kHz Crystal Oscillator

The CYBT-213043-02 includes connections for an external 32-kHz oscillator to provide accurate timing during low power operations.

Figure 11 shows the 32-kHz XTAL oscillator with external components and Ta bl e 9 lists the oscillator characteristics. This oscillator

can be operated with a 32 kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must
have an accuracy of ±250 ppm or better per the BT spec over temperature and including aging. The default component values are:
R1 = 10 MO and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 11. 32 kHz Oscillator Block Diagram

Document Number: 002-26540 Rev. ** Page 17 of 45

PRELIMINARY

CYBT-213043-02

Table 9. XTAL Oscillator Characteristics

Parameter Symbol Conditions Minimum Ty pic al Maximum Unit

Output frequency F

oscout

– – 32.768 – kHz
Frequency tolerance – Over temperature and aging – – 250 ppm
XTAL drive level P
XTAL series resistance R
XTAL shunt capacitance C
Load capacitance C

drv

series

shunt

l

For crystal selection – – 0.5 W
For crystal selection – – 70 k
For crystal selection – – 2.2 pF
For crystal selection – –6 - pF

Power Modes

The CYBT-213043-02 support the following HW power modes are supported:

■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.

■ Idle mode - CPU is paused.

■ Sleep mode - All systems clocks idle except for LPO. The device can wake up either after a programmed period of time has expired

or if an external event is received via one of the GPIOs. In Sleep mode, the CPU is in WFI (wait for interrupt) and the HCLK is not
running. The PMU determines if the other clocks can be turned off and does accordingly. The state of the device is retained, the
internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.

■ PDS (Power Down Sleep) mode - radio powered down and digital core mostly powered down except for RAM, registers, and some

core logic. CYBT-213043-02 can wake up either after a programmed period of time has expired or if an external event is received
via one of the GPIO.

■ ePDS (extended PDS) - This power mode is an extension of PDS Mode. In this mode, only the main RAM and ePDS control circuitry

retains power. As in other modes, the CYBT-213043-02 can wake up either after a programmed period or upon receiving an external
event.

■ HIDOFF (Deep Sleep) mode - Core, radio, and regulators powered down. Only the LHL IO domain is powered. In this mode, the

CYBT-213043-02 can be woken up either by an event on one of the GPIOs or after a certain amount of time has expired. After
wakeup, the part will go through full FW initialization although it will retain enough information to determine that it came out of HID-Off
and the event the caused the wake up. The LPO and RTC are turned off in the HIDOFF power mode.

Transition between power modes is handled by the on-chip firmware with host/application involvement. Refer to Firmware Section for
details.

Firmware

The CYBT-213043-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all
on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes
drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power
modes. The ROM also supports OTA firmware update.

The CYBT-213043-02 is fully supported by the Cypress ModusToolbox IDE. ModusToolbox releases provide latest ROM patches,
drivers, and sample applications allowing customized applications using the CYBT-213043-02 to be built quickly and efficiently.

Watchdog

CYBT-213043-02 includes an onboard watchdog with a period of approximately 4 seconds. The watchdog generates an interrupt to
the Firmware after 2 seconds of inactivity and resets the device after 4 seconds.

Lockout Functionality
The CYBT-213043-02 powers up with JTAG and SWD access to flash and RAM is disabled. After reset, FW checks OCF for the

presence of a security lockout field. If present, FW leaves JTAG and SWD Flash and RAM access disabled and also blocks any HCI
commands from reading the raw contents of the RAM or Flash. This provides an effective way of protection against tampering,
dumping, probing, or reverse engineering of the user application stored in the on-chip flash. The only firmware upgrade path in this
scenario is secure over-the-air (OTA) update.

The security field can be programmed in the factory after all programming and testing has been done.

True Random Number Generator

The CYBT-213043-02 includes a hardware TRNG (True Random Number Generator). Applications can access the random number
generator via the firmware driver.

Document Number: 002-26540 Rev. ** Page 18 of 45

PRELIMINARY

CYBT-213043-02

Peripherals and Communication Interfaces

I2C

The CYBT-213043-02 provides a 2-pin I2C master/slave interface to communicate with I2C compatible peripherals. The following
transfer clock rates are supported:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I

■ 1 MHz (Compatibility with high-speed I

The I2C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where
read/write can be up to 64 bytes.

SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 4), allowing for flexible system configuration.
When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. BSC does not
support multimaster capability or flexible wait-state insertion by either master or slave devices.

HCI UART Interface

CYBT-213043-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with
an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from
115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also
available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command.
The CYBT-213043-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±5%. The UART interface CYBT-213043-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced
data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-213043-02 or allow the CYBT-213043-02 to
sleep when radio activities permit. The CYBT-213043-02 can also wake up the host as needed or allow the host to sleep via the
HOST_WAKE signal. Combined, the two signals allow the host and the CYBT-213043-02 to optimize system power consumption by
allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific
command.

The FW UART driver allows applications to select different baud rates.

2

C-compatible speed)

2

C-compatible devices is not guaranteed)

Peripheral UART Interface

The CYBT-213043-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the same
as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be configured
individually and separately for each functional pin. The CYBT-213043-02 can map the peripheral UART to any LHL GPIO.

Serial Peripheral Interface

The CYBT-213043-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI operations.
Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more
flexibility for user applications, the CYBT-213043-02 has optional I/O ports that can be configured individually and separately for each
functional pin.

SPI IO voltage depends on VDDO/VDDM.

Document Number: 002-26540 Rev. ** Page 19 of 45

PRELIMINARY

CYBT-213043-02

ADC Port

The CYBT-213043-02 includes a - ADC designed for audio and DC measurements. The ADC can measure the voltage on 15
GPIOs (P0, P1, P8-P15, P17, P28, P29, P32, P37). When used for analog inputs, the GPIOs must be placed in digital input disable
mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap reference has ±5% accuracy without
calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement
accuracy in Direct Current (DC) Mode.

The application can access the ADC through the ADC driver included in the firmware.
The following CYBT-213043-02 module solder pads can be used as ADC inputs:

■ Pad 4: P29, ADC Input Channel 10

■ Pad 5: P32, ADC Input Channel 7

■ Pad 7: P37, ADC Input Channel 2

■ Pad 8: P28, ADC Input Channel 11

■ Pad 9: P0, ADC Input Channel 29

■ Pad 10: P13, ADC Input Channels 28

■ Pad 11: P10, ADC Input Channel 25

■ Pad 12: P13, ADC Input Channel 22

■ Pad 14: P12, ADC Input Channel 23

■ Pad 15: P11, ADC Input Channels 24

■ Pad 16: P9, ADC Input Channels 26

■ Pad 17: P14, ADC Input Channels 21

■ Pad 18: P17, ADC Input Channels 18

■ Pad 26: P15, ADC Input Channels 20

■ Pad 27: P8, ADC Input Channels 27

GPIO Port

The CYBT-213043-02 has a maximum of 22 GPIOs. All GPIOs support the following:

■ Programmable pull-up/down of approximately 45 KW.

■ Input disable, allowing pins to be left floating or analog signals connected without risk of leakage.

■ Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

■ P26/P27/P28/P29 can sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.

Most peripheral functions can be assigned to any GPIO using the ModusToolbox Device Configurator. For details on the functions
that are assignable via the ModusToolbox Device Configurator, refer to Table 5.

The following list details the GPIOs that are available on the CYBT-213043-02 module:

■ P0-P6, P8-P15, P17, P26-P29, P32, and P37

Document Number: 002-26540 Rev. ** Page 20 of 45

PRELIMINARY

CYBT-213043-02

PWM

The CYBT-213043-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:

■ Each of the six PWM channels contains the following registers:
❐ 16-bit initial value register (read/write)
❐ 16-bit toggle register (read/write)

❐ 16-bit PWM counter value register (read)

■ PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used:
❐ To configure each PWM channel
❐ To select the clock of each PWM channel

❐ To change the phase of each PWM channel

The application can access the PWM module through the FW driver.

Figure 12 shows the structure of one PWM channel.

Figure 12. PWM Block Diagram

PDM Microphone

The CYBT-213043-02 accepts a -based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either
8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate
digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:

■ 8 kHz

■ 16 kHz

The external digital microphone takes in a 2.4-MHz clock generated by the CYBT-213043-02 and outputs a PDM signal, which is
registered by the PDM interface with either the rising or falling edge of the 2.4-MHz clock selectable through a programmable control
bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.

Document Number: 002-26540 Rev. ** Page 21 of 45

PRELIMINARY

CYBT-213043-02

I2S Interface

The CYBT-213043-02 supports a single I2S digital audio port. with both master and slave modes. The I2S signals are:

2

■ I

S Clock: I2S SCK

2

■ I

S Word Select: I2S WS

2

■ I

S Data Out: I2S DO

2

■ I

S Data In: I2S DI

2

I

S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel
word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I
Specifications. The MSB of each data word is transmitted one bit clock cycle after the I
edge of bit clock. Left Channel data is transmitted when I
Data bits sent by the CYBT-213043-02 are synchronized with the falling edge of I
the rising edge of the I

2

S SCK.

2

S WS is low, and right-channel data is transmitted when I2S WS is high.

2

S WS transition, synchronous with the falling

2

S SCK and should be sampled by the receiver on

2

S bus, per I2S

The clock rate in master mode is either one of the following:

■ 32 kHz × 32 bits per frame = 1024 kHz

■ 32 kHz × 50 bits per frame = 1600 kHz

The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock rate is supported up
to a maximum of 3.072 MHz.

Note: The PCM interface shares HW with the I

2

S interface and only one can be used at a given time.

PCM Interface

The CYBT-213043-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master
mode, the CYBT-213043-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another
master on the PCM interface and are inputs to the CYBT-213043-02.The configuration of the PCM interface may be adjusted by the
host through the use of vendor-specific HCI commands.

Note: The PCM interface shares HW with the I
Note: Only audio source (other than SCO) use cases are supported on 20819 at this time.

2

S interface and only one can be used at a given time.

Slot Mapping

The CYBT-213043-02 supports up to three simultaneous full-duplex channels through the PCM Interface. These three channels are
time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is
divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz).
The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. The PCM data output driver tristates its
output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after
the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The CYBT-213043-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchro­nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and
is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects
the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.

Data Formatting

The CYBT-213043-02 may be configured to generate and accept several different data formats. For conventional narrow band speech
mode, the CYBT-213043-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to
support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a
sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

Document Number: 002-26540 Rev. ** Page 22 of 45

PRELIMINARY

CYBT-213043-02

Electrical Characteristics

The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these
limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute
maximum conditions for extended periods can adversely affect long-term reliability of the device.

.

Table 10. Silicon Absolute Maximum Ratings

Requirement Parameter

Maximum Junction Temperature – – TBD °C
VDDO1/VDDO2 –0.5 – 3.795 V
IFVDD/PLLVDD/VCOVDD/VDDC –0.5 – 1.38 V
PMUAVDD/SR_PVDD –0.5 – 3.795 V
DIGLDO_VDDIN –0.5 – 1.65 V
RFLDO_VDDIN –0.5 – 1.65 V
MIC_AVDD –0.5 – 3.795 V

Table 11. ESD/Latch-up

Requirement Parameter

ESD Tolerance HBM (Silicon) –2000 – 2000 V
ESD Tolerance CDM (Silicon) –500 – 500 V
Latch-up – 200 – mA

Table 12. Power Supply Specifications

Parameter Conditions Min. Typical Max. Unit

VDD input Module Input 1.76 3.0 3.63 V
VDD Ripple Module Input Ripple (VDD) – – 100 mV
VBAT Input Internal to Module (not accessible) 1.90 3.0 3.6 V
PMU turn-on time VBAT is ready. – – 300 s

Min. Nom. Max.

Min. Nom. Max.

Specification

Specification

Unit

Unit

Table 13. Shutdown Voltage (Brown Out)

Parameter

V

SHUT

The CYBT-213043-02 uses an onboard low voltage detector to shut down the device when supply voltage (VDDBAT3V) drops below
the operating range.

Document Number: 002-26540 Rev. ** Page 23 of 45

Min. Typ. Max.

1.54 1.62 1.7 V

Specification

Unit

PRELIMINARY

CYBT-213043-02

Current Consumption

Ta bl e 1 4 provides the current consumption measurements taken at the input of LDOIN and VDDIO combined (LDOIN = VDDIO =

3.0 V).

Table 14. Current Consumption

Operational Mode Conditions Typ ica l Unit

HCI

RX Continuous RX 5.9

48 MHz with Pause 1.3
48 MHz without Pause 2.55

mA

TX Continuous TX - 4 dBm 5.8
PDS – 16.5

AePDS All RAM retained 8.7

HID-Off (SDS) 32 kHz XTAL on 1.75

Silicon Core Buck Regulator

Table 15. Core Buck Regulator

Parameter Conditions Min. Typ. Max. Unit

Input Supply, VBAT DC Range 1.62 3.0 3.63 V

Output Current

Output Voltage

Output Voltage Accuracy

Ripple Voltage

Output Inductor, L
Output Capacitor, C
Input Capacitor, C

OUT

IN

Input Supply Voltage Ramp
Time

Active Mode – < 60 100
PDS Mode – < 60 70

mA

Active Mode 1.1 1.26 1.4

PDS Mode, 40 mV min regulation window. 0.76

0.94 Avg

(0.92-0.96)

1.4

Active Mode, includes line and load regulation.
Before trim:
After trim:

–4
–2

–+4+2%

%

Active Mode

2.2 H ± 25% inductor, DCR = 114 m ± 20%

4.7 F ± 10% capacitor, Total ESR < 20 m

–3–

mV

PDS Mode 40 40 –

[3]

Components are included on module.

1.6

3.0

4.0

[3]

[3]

2.2 – H

4.7 –
10 –

F

0 to 3.3 V 40 – – s

V

Note

3. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

Document Number: 002-26540 Rev. ** Page 24 of 45

PRELIMINARY

CYBT-213043-02

Digital LDO

Note

4. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.

Table 16. Digital LDO

Parameter Condition Min Typ Max Unit

Input Supply, DIGLDO_VDDIN Min must be met for correct operation V

Range 0.9 1.2 1.275

Output Voltage, DIGLDO_VDDOUT

Step – 25 – mV

Accuracy after trimming –2 – +2 %
Dropout Voltage At max load current – – 20 mV
Output Current DC Load 0.075 40 60 mA
Quiescent Current At T  85 C, V
Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 m¶1.55
Line Regulation 1.235 V  V
Load Regulation V

Load Step Error

Leakage Current

In-rush Current C
LDO Turn On Time C

PSRR

= 1.2 V, V

OUT

step 1 mA 20 mA @ 1 s rise/fall,

I

OUT

= 2.2 F, V

C

OUT

Power down Mode, V

Power down Mode, V

= 2.2 F, V

OUT

= 2.2 F, V

OUT

= 2.2 F, 1.235V  VIN  1.4 V, V

C

OUT

= 20 mA

I

OUT

f = 1 kHz

= 1.4 V – – 40 A

IN

 1.4 V – 5 10 mV/V

IN

= 1.26 V, 1 mA  I

IN

= 1.235 V, V

IN

= 1.4 V, Temp = 25 C––50nA

IN

= 1.4 V, Temp = 125 C––2A

IN

= 1.4 V, V

IN

= 1.4 V, V

IN

OUT

OUT

OUT

 25 mA – – 0.44 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA

= 1.2 V, I

= 20 mA – – 120 s

OUT

= 1.2 V,

OUT

f = 100 kHz

+ 20 mV 1.26 1.4

OUT

[4]

2.2 – F

–24 – +24 mV

25

––dB

13

V

dB

RF LDO

Table 17. RF LDO

Parameter Conditions Min. Typ. Max. Unit

Input Supply, RFLDO_VDDIN Min must be met for correct operation V

Range 1.1 1.2 1.275

Output Voltage, RFLDO_VDDOUT

Step – 25 – mV

Accuracy after trimming –2 – +2 %
Dropout Voltage At max load current – – 20 mV
Output Current DC Load 0.075 20 60 mA
Quiescent Current At T  85 C, V
Output Load Capacitor, C

OUT

Total trace + cap ESR must be < 80 m¶1.55
Line Regulation 1.235 V  V
Load Regulation V

Load Step Error

Leakage Current

In-rush Current C
LDO Turn On Time C

= 1.2 V, V

OUT

step 1 mA 20 mA @ 1 s rise/fall,

I

OUT

= 2.2 F, V

C

OUT

Power down Mode, V

Power down Mode, V

= 2.2 F, V

OUT

= 2.2 F, V

OUT

= 1.4 V – – 40 A

IN

 1.4 V – 5 10 mV/V

IN

= 1.26 V, 1 mA  I

IN

= 1.235 V, V

IN

= 1.4 V, Temp = 25 C––50nA

IN

= 1.4 V, Temp = 125 C––2A

IN

= 1.4 V, V

IN

= 1.4 V, V

IN

OUT

OUT

OUT

 25 mA – – 0.44 mV/mA

OUT

= 1.2 V

= 1.2 V – – 100 mA

= 1.2 V, I

= 20 mA – – 120 s

OUT

+ 20 mV 1.26 1.4

OUT

[4]

2.2 – F

–24 – +24 mV

V

Document Number: 002-26540 Rev. ** Page 25 of 45

PRELIMINARY

CYBT-213043-02

Table 17. RF LDO (continued)

Parameter Conditions Min. Typ. Max. Unit

= 2.2 F, 1.235 V  VIN  1.4 V, V

C

OUT

I

= 20 mA

PSRR

OUT

f = 1 kHz

f = 100 kHz

Noise

= 2.2 F, V

C

OUT

20 mA

f = 30 kHz

= 1.235 V, V

IN

f = 100 kHz

Digital I/O Characteristics

Table 18. Digital I/O Characteristics

Characteristics Symbol Minimum Typical Maximum Unit

Input low voltage (VDD = 3 V) V
Input high voltage (VDD = 3 V) V
Input low voltage (VDD = 1.8 V) V
Input high voltage (VDD = 1.8 V) V
Output low voltage V
Output high voltage V
Input low current I
Input high current I
Output low current (VDD = 3 V, VOL = 0.4 V) I
Output low current (VDD = 3 V, V
Output high current (VDD = 3 V, V
Output high current (VDD = 1.8 V, VOH = 1.4 V) I
Input capacitance C

= 1.8 V) I

OL

= 2.6 V) I

OH

OL

OH

IL

IH

OL

OL

OH

OH

IH

IH

IN

IL

IL

OUT

= 1.2 V,

OUT

25

––dB

13

= 1.2 V, I

OUT

=

––80

––0.8V

2.4 – – V
––0.4V

1.4 – – V
––0.4V

VDDO – 0.4 V – – V

––1.0A
––1.0A
––4.0mA
––2.0mA
––8.0mA
––4.0mA
––0.4pF

70

dB

nVHz
nVHz

ADC Characteristics

Table 19. Electrical Characteristics

Parameter Symbol Conditions/Comments Min. Typ . Max. Unit

Current consumption I

TOT

Power down current – At room temperature – 1 – A
ADC Core Specification
ADC reference voltage VREF From BG with ±3% accuracy – 0.85 – V
ADC sampling clock – – – 12 – MHz
Absolute error – Includes gain error, offset and

ENOB – For audio application 12 13 – Bit

ADC input full scale FS For audio application – 1.6 –

Document Number: 002-26540 Rev. ** Page 26 of 45

––23mA

––5%

distortion. Without factory calibration.
Includes gain error, offset and

––2%

distortion. After factory calibration.

For static measurement 10 – –

For static measurement 1.8 – 3.6

PRELIMINARY

CYBT-213043-02

Table 19. Electrical Characteristics (continued)

Parameter Symbol Conditions/Comments Min. Typ . Max. Unit

Conversion rate – For audio application 8 16 – kHz

For static measurement 50 100 –

Signal bandwidth – For audio application 20 – 8K Hz

For static measurement – DC –

Input impedance R

Startup time – For audio application – 10 – ms

MIC PGA Specifications
MIC PGA gain range – – 0 – 42 dB
MIC PGA gain step – – – 1 – dB
MIC PGA gain error – Includes part-to-part gain variation –1 – 1 dB
PGA input referred noise – At 42 dB PGA gain A-weighted – – 4 V
Passband gain flatness – PGA and ADC, 100 Hz–4 kHz –0.5 – 0.5 dB
MIC Bias Specifications
MIC bias output voltage – At 2.5-V supply – 2.1 – V
MIC bias loading current – – – – 3 mA
MIC bias noise – Refers to PGA input 20 Hz to

MIC bias PSRR – at 1 kHz 40 – – dB
ADC SNR – A-weighted 0 dB PGA gain 78 – – dB
ADC THD + N – –3 dBFS input 0 dB PGA gain 74 – – dB
GPIO input voltage Always lower than avddBAT – – 3.6 V
GPIO source impedance

[5]

IN

– Resistance – – 1 k

For audio application 10 – – KW
For static measurement 500 – –

For static measurement – 20 – s

––3V

8 kHz, A-weighted

Capacitance – – 10 pF

Note

5. Conditional requirement for the measurement time of 10 s. Relaxed with longer measurement time for each GPIO input channel.

Document Number: 002-26540 Rev. ** Page 27 of 45

PRELIMINARY

CYBT-213043-02

Chipset RF Specifications

Notes

6. The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off.

7. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

8. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

9. Desired signal is –64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth-modulated signal at
frequency f2, f0 = 2 * f1 – f2, and |f2 – f1| = n * 1 MHz, where n = 3, 4, or 5. For the typical case, n = 4.

Ta bl e 2 0, Table 21, Tabl e 2 2, and Tab l e 2 3 apply to single-ended industrial temperatures. Unused inputs are left open.

Table 20. BR/EDR - Receiver RF Specifications

Parameter Mode and Conditions Min Typ Max Unit

Receiver Section

Frequency range – 2402 – 2480 MHz

[]

RX sensitivity

GFSK, BDR GFSK 0.1% BER, 1 Mbps – –92
EDR 2M – –93.5 –
EDR 3M – –87 –

Maximum input – –20 – – dBm

Interference Performance

C/I cochannel GFSK, BDR GFSK 0.1% BER
C/I 1 MHz adjacent channel GFSK, BDR GFSK 0.1% BER
C/I 2 MHz adjacent channel GFSK, BDR GFSK 0.1% BER
C/I 3 MHz adjacent channel GFSK, BDR GFSK 0.1% BER
C/I image channel GFSK, BDR GFSK 0.1% BER
C/I 1 MHz adjacent to image channel GFSK, BDR GFSK 0.1% BER

Out-of-Band Blocking Performance (CW)

[]

[]

[]

[]

[]

[]

[]

––11.0
––0.0
– – –30.0
– – –40.0
–––9.0
– – –20.0

30 MHz to 2000 MHz BDR GFSK 0.1% BER – –10.0 –
2000 MHz to 2399 MHz BDR GFSK 0.1% BER – –27 –
2498 MHz to 3000 MHz BDR GFSK 0.1% BER – –27 –
3000 MHz to 12.75 GHz BDR GFSK 0.1% BER – –10.0 –

Intermodulation Performance

[]

BT, interferer signal level BDR GFSK 0.1% BER – – –39.0 dBm
Spurious Emissions
30 MHz to 1 GHz – – – –57.0
1 GHz to 12.75 GHz – – – –55.0

–dBm

dB

dB

dBm

dBm

.

Document Number: 002-26540 Rev. ** Page 28 of 45

PRELIMINARY

CYBT-213043-02

Table 21. BR/EDR - Transmitter RF Specifications

Parameter Min Typ Max Unit

Transmitter Section

Frequency range 2402 – 2480 MHz
Class 2: BR TX power – 4.0 –
Class 2: EDR 2M and 3M TX power – 0 –

dBm

20 dB bandwidth – 930 1000 kHz

Adjacent Channel Power

|M – N| = 2 – – –20
|M – N| 3

[10]

– – –40

dBm

Out-of-Band Spurious Emission

30 MHz to 1 GHz – – –36.0
1 GHz to 12.75 GHz – – –30.0

1.8 GHz to 1.9 GHz – – –47.0

dBm

5.15 GHz to 5.3 GHz – – –47.0

LO Performance

Initial carrier frequency tolerance –75 – +75 kHz
Frequency Drift
DH1 packet –25 – +25

kHzDH3 packet –40 – +40
DH5 packet –40 – +40
Drift rate –20 – 20 kHz/50 µs

Frequency Deviation

Average deviation in payload (sequence used is 00001111) 140 – 175
Maximum deviation in payload (sequence used is 10101010) 115 – –

kHz

Channel spacing – 1 – MHz

Note

10. Meet SIG Specification.

Table 22. BLE RF Specifications

Parameter Conditions Minimum Typ ical Maximum Unit

Frequency range N/A 2402 – 2480 MHz

RX sensitivity

[11]

GFSK, BDR GFSK 0.1% BER 0.1% BER,
1 Mbps

––95–

dBm

TX power N/A – 4.0 –
Mod Char: Delta F1 average N/A 225 255 275 kHz
Mod Char: Delta F2 max

[12]

N/A 99.9 – – %

Mod Char: Ratio N/A 0.8 – – %

Notes

11. Dirty TX is Off.

12. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

Document Number: 002-26540 Rev. ** Page 29 of 45

PRELIMINARY

CYBT-213043-02

Table 23. BLE2 RF Specifications

Parameter Conditions Minimum Ty pic al Maximum Unit

RX sensitivity
TX power – – 4.0 –

Note

13. 255 packet.

[13]

–––89–

dBm

Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

UART Timing

Table 24. UART Timing Specifications

Reference Characteristics Min. Typ . Max. Unit

1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods
2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods
3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods

Figure 13. UART Timing

Document Number: 002-26540 Rev. ** Page 30 of 45

PRELIMINARY

CYBT-213043-02

SPI Timing

The SPI interface can be clocked up to 24 MHz.

Ta bl e 2 5 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2.

Table 25. SPI Mode 0 and 2

Reference Characteristics Min. Max. Unit

1 Time from master assert SPI_CSN to first clock edge 45 –

SCK

3 Idle time between subsequent SPI transactions 1 SCK –

Figure 14. SPI Timing, Mode 0 and 2

ns2 Setup time for MOSI data lines 6 ¾

Document Number: 002-26540 Rev. ** Page 31 of 45

PRELIMINARY

CYBT-213043-02

Ta bl e 2 6 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3.

Table 26. SPI Mode 1 and 3

Reference Characteristics Min. Max. Unit

1 Time from master assert SPI_CSN to first clock edge 45 –

SCK

3 Idle time between subsequent SPI transactions 1 SCK –

Figure 15. SPI Timing, Mode 1 and 3

ns2 Setup time for MOSI data lines 6 ¾

Document Number: 002-26540 Rev. ** Page 32 of 45

PRELIMINARY

CYBT-213043-02

I2C Compatible Interface Timing

The specifications in Table 26 references Figure .

Table 27. I2C Interface Timing Specifications (up to 1 MHz)

Reference Characteristics Minimum Maximum Unit

100

1 Clock frequency –

2 START condition setup time 650 –
3 START condition hold time 280 –
4 Clock low time 650 –
5 Clock high time 280 –

[15]

[14]

0 –

650 –

6 Data input hold time
7 Data input setup time 100 –
8 STOP condition setup time 280 –
9 Output valid from clock – 400
10 Bus free time

Notes

14. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

15. Time that the CBUS must be free before a new transaction can start.

400
800

1000

kHz

ns

Figure 16.

I2C Interface Timing Diagram

Document Number: 002-26540 Rev. ** Page 33 of 45

PRELIMINARY

CYBT-213043-02

I2S Interface Timing

I2S timing is shown below in Table 28, Figure 17, and Figure 18.

Table 28. Timing for I

Clock Period T T

HIGH t

HC

LOWt

LC

HIGH t

HC

LOW t

LC

Rise time t

Delay t
Hold time t

Setup time t

Hold time t

Notes

16. The system clock period T must be greater than T

17. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t
respect to T.

18. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum
periods are greater than 0.35T

19. Because the delay (t
t
tRC is not more than t

20. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient
setup time.

21. The data setup and hold time must not be less than the specified receiver setup and hold time.

RC

dtr

htr

hr

which means t

RC

sr

2

S Transmitters and Receivers

Transmitter Receiver

NotesLower LImit Upper Limit Lower Limit Upper Limit

Min Max Min Max Min Max Min Max

tr

–––Tr–––

Master Mode: Clock generated by transmitter or receiver

0.35T

0.35T

tr

tr

– – – 0.35T

– – – 0.35T

tr

tr

– – – [17]

– – – [17]

Slave Mode: Clock accepted by transmitter or receiver

–0.35Ttr–––0.35Ttr––

–0.35Ttr–––0.35Ttr––

– – 0.15T

tr

– – – – [17]

Transmi tter

– – – 0.8T – – – – [18]
0–––––––

Receiver

––––0.2Ttr– – – [19]

––––0.2Ttr– – – [19]

and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.

tr

, any clock that meets the requirements can be used.

r

) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding

dtr

becomes zero or negative. Therefore, the transmitter has to guarantee that t

htr

RCmax

, where t

is not less than 0.15Ttr.

RCmax

is greater than or equal to zero, so long as the clock rise-time

htr

and tLC are specified with

HC

[16]

[16]

[16]

[17]

Document Number: 002-26540 Rev. ** Page 34 of 45

PRELIMINARY

CYBT-213043-02

Figure 17. I2S Transmitter Timing

2

Figure 18. I

S Receiver Timing

Document Number: 002-26540 Rev. ** Page 35 of 45

PRELIMINARY

CYBT-213043-02

Environmental Specifications

Note

22. This does not apply to the RF pins (ANT).

Environmental Compliance

This Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBT-213043-02 module is certified under the following RF certification standards:

■ FCC: WAP3034

■ ISED: 7922A-3034

■ MIC: TBD

■ CE

Safety Certification

The CYBT-213043-02 module complies with the following safety regulations:

■ Underwriters Laboratories, Inc. (UL): Filing E331901

■ CSA

■ TUV

Environmental Conditions

Ta bl e 2 9 describes the operating and storage conditions for the Cypress Bluetooth module.

Table 29. Environmental Conditions for CYBT-213043-02

Description Minimum Specification Maximum Specification

Operating temperature 30 °C 85 °C
Operating humidity (relative, non-condensation) 5% 85%
Thermal ramp rate
Storage temperature
Storage temperature and humidity

ESD: Module integrated into system Components

[22]

– 10 °C/minute

–40 °C 85 °C

– 85 °C at 85%

–

15 kV Air

2.0 kV Contact

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Document Number: 002-26540 Rev. ** Page 36 of 45

PRELIMINARY

CYBT-213043-02

Regulatory Information

FCC

FCC NOTICE:
The device CYBT-213043-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter

approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■ Reorient or relocate the receiving antenna.

■ Increase the separation between the equipment and receiver.

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

■ Consult the dealer or an experienced radio/TV technician for help

LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP3034.

In any case the end product must be labeled exterior with “Contains FCC ID: WAP3034”.

ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 13. When integrated in the OEMs

product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna
not in Table 7 on page 13 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for
emissions.

RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna

in Ta b le 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal
instructions about the integrated radio module is not allowed.

The radiated output power of CYBT-213043-02 with the integrated PCB trace antenna (FCC ID: WAP3034) is far below the FCC radio
frequency exposure limits. Nevertheless, use CYBT-213043-02 in such a manner that minimizes the potential for human contact
during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-26540 Rev. ** Page 37 of 45

PRELIMINARY

CYBT-213043-02

ISED

Innovation, Science and Economic Development (ISED) Canada Certification

CYBT-213043-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada.
License: IC: 7922A-3034
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antenna listed in Ta bl e 7 on page 13, having a maximum gain of -0.5 dBi. Antennas
not included in Table 7 on page 13 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required
antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any
other antenna or transmitter.

ISED NOTICE:
The device CYBT-213043-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the

requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This
device may not cause harmful interference, and (2) This device must accept any interference received, including interference that
may cause undesired operation.

L'appareil CYBT-213043-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux
exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions
suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y
compris les interférences pouvant entraîner un fonctionnement indésirable.

ISED INTERFERENCE STATEMENT FOR CANADA
This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).

Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any
interference, including interference that may cause undesired operation of the device.

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de
licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur
de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le
fonctionnement.

ISED RADIATION EXPOSURE STATEMENT FOR CANADA
This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.

LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as
the ISED Notices above. The IC identifier is 7922A-3034. In any case, the end product must be labeled in its exterior with "Contains
IC: 7922A-3034".

Le fabricant d'équipement d'origine (OEM) doit s'assurer que le
étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit
ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3034. En tout cas, le produit final doit être étiqueté dans son extérieur
avec "Contient IC: 7922A-3034".

s exigences d'étiquetage ISED sont respectées. Cela comprend une

Document Number: 002-26540 Rev. ** Page 38 of 45

PRELIMINARY

CYBT-213043-02

European Declaration of Conformity

TBD

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-213043-02 complies with the essential requirements and
other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive
2014, the end-customer equipment should be labeled as follows:

All versions of the CYBT-213043-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus,
Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta,
Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

MIC Japan

CYBT-213043-02 is certified as a module with certification number TBD. End products that integrate CYBT-213043-02 do not need
additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

Document Number: 002-26540 Rev. ** Page 39 of 45

PRELIMINARY

CYBT-213043-02

Packaging

Table 30. Solder Reflow Peak Temperature

Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles

CYBT-213043-02 35-pad SMT 260 °C 30 seconds 2

Table 31. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number Package MSL

CYBT-213043-02 35-pad SMT MSL 3

The CYBT-213043-02 is offered in tape and reel packaging. Figure 19 details the tape dimensions used for the CYBT-213043-02.

Figure 19. CYBT-213043-02 Tape Dimensions

Figure 20 details the orientation of the CYBT-213043-02 in the tape as well as the direction for unreeling.

Figure 20. Component Orientation in Tape and Unreeling Direction

Document Number: 002-26540 Rev. ** Page 40 of 45

PRELIMINARY

CYBT-213043-02

Figure 21 details reel dimensions used for the CYBT-213043-02.

Top View (Seen from Top)

Figure 21. Reel Dimensions

The CYBT-213043-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBT-213043-02 is detailed in Figure 22.

Figure 22. CYBT-213043-02 Center of Mass

Document Number: 002-26540 Rev. ** Page 41 of 45

PRELIMINARY

CYBT-213043-02

Ordering Information

Ta bl e 3 2 lists the CYBT-213043-02 part number and features. Ta bl e 3 2 also lists the target program for the respective module ordering

codes. Ta bl e 3 3 lists the reel shipment quantities for the CYBT-213043-02.

Table 32. Ordering Information

Ordering Part

Number

CYBT-213043-02 96 256 176 Yes Yes Yes Yes Yes 6 15 22 35-SMT Tape and Reel

Table 33. Tape and Reel Package Quantity and Minimum Order Amount

Description Minimum Reel Quantity Maximum Reel Quantity Comments

Reel Quantity
Minimum Order Quantity (MOQ)
Order Increment (OI)

The CYBT-213043-02 is offered in tape and reel packaging. The CYBT-213043-02 ships in a reel size of 500 units.

For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134
U.S. Cypress Headquarter Contact Info [phone]
Cypress website address http://www.cypress.com

Max CPU

Speed

(MHz)

Flash

Size
(KB)

RAM

Size

UART I2C SPI I2S PCM PWM

(KB)

500 500 Ships in 500 unit reel quantities.
500 – –
500 – –

ADC

Inputs

GPIOs Package Packaging

Document Number: 002-26540 Rev. ** Page 42 of 45

PRELIMINARY

CYBT-213043-02

Acronyms Document Conventions

Table 34. Acronyms Used in this Document

Acronym Description

BLE Bluetooth Low Energy
Bluetooth SIG Bluetooth Special Interest Group
CE European Conformity
CSA Canadian Standards Association
EMI electromagnetic interference
ESD electrostatic discharge
FCC Federal Communications Commission
GPIO general-purpose input/output

ISED

IDE integrated design environment
KC Korea Certification

MIC

PCB printed circuit board
RX receive
QDID qualification design ID

SMT

TCPWM timer, counter, pulse width modulator (PWM)

TUV

TX transmit

Innovation, Science and Economic Devel­opment (Canada)

Ministry of Internal Affairs and Communications
(Japan)

surface-mount technology; a method for
producing electronic circuitry in which the
components are placed directly onto the surface
of PCBs

Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)

Units of Measure

Table 35. Units of Measure

Symbol Unit of Measure

°C degree Celsius
dB decibel
dBi decibels relative to isotropic
dBm decibel-milliwatts
kV kilovolt
mA milliamperes
mm millimeters
mV millivolt

A microamperes
m micrometers

MHz megahertz
GHz gigahertz
Vvolt

Document Number: 002-26540 Rev. ** Page 43 of 45

PRELIMINARY

CYBT-213043-02

Document History Page

Document Title: CYBT-213043-02 EZ-BT™ Module
Document Number: 002-26540

Revision ECN

** 6487647 DSO 02/21/2019 Preliminary datasheet for CYBT-213043-02 module.

Orig. of
Change

Submission

Date

Description of Change

Document Number: 002-26540 Rev. ** Page 44 of 45

PRELIMINARY

CYBT-213043-02

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

Products

Arm® Cortex® Microcontrollers cypress.com/arm
Automotive cypress.com/automotive
Clocks & Buffers cypress.com/clocks
Interface cypress.com/interface
Internet of Things cypress.com/iot
Memory cypress.com/memory
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless

PSoC® Solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Cypress Developer Community

Community | Projects | Video | Blogs | Training | Components

Technical Support

cypress.com/support

© Cypress Semiconductor Corporation, 2019. This document is the property of Cypress Semiconductor Corporation and its subsidiarie s, including Spansion LLC ("C ypress"). This doc ument, inclu ding
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-26540 Rev. ** Revised February 21, 2019 Page 45 of 45