PRELIMINARY
CYBT-483039-02
EZ-BT™ XR WICED® Module
General Description
Notes
1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with o
2. Specified as EZ-BT XT module to module range. Mobile phone connection will decrease based on the PA/LNA performance of the mobile phone used.
The CYBT-483039-02 is a dual-mode Bluetooth BR/EDR and
Low Energy (BLE) wireless module solution. The
CYBT-483039-02 includes onboard crystal oscillators, passive
components, PA/LNA, and the Cypress CYW20719 silicon
device.
The CYBT-483039-02 supports a number of peripheral functions
(ADC, PWM), as well as multiple serial communication protocols
(UART, SPI, I2C, I2S/PCM). The CYBT-483039-02 includes a
royalty-free stack compatible with Bluetooth 5.0 in a 12.75 ×
18.59 × 1.80 mm module form-factor.
The CYBT-483039-02 includes an integrated chip antenna,
on-board external power/low noise amplifier, qulaified by
Bluetooth SIG, and includes regulatory certification approval for
FCC, ISED, MIC, and CE.
Module Description
Module size: 12.75 mm × 18.59 mm × 1.80 mm
n
Complies with Bluetooth Core Specification version 5.0
n
supporting BR, EDR 2/3 Mbps, eSCO, BLE, and LE 2 Mbps .
QDID: TBD
p
p
Declaration ID: TBD
True Extended Range:
n
Up to 1 kilometer bidirectional communication
p
Certified to FCC, ISED, MIC, and CE standards
n
n
Up to 15 GPIOs
n
1024-KB flash memory, 512-KB SRAM memory
n
Industrial temperature range: –30 °C to +85 °C
n
Integrated ARM Cortex-M4 microprocessor core with
floating point unit (FPU)
RF Characteristics
Maximum TX output power(EIRP): +20.0 dBm
n
n
Conducted output power:
+17.6dBm for BT3.0, +16.8dBm for BT4.0
p
Antenna peak gain: 2.3 dBi
n
BLE RX Receive Sensitivity: –95.0 dbm
n
Received signal strength indicator (RSSI) with 1-dB resolution
n
Power Consumption
n
TX current consumption
BLE silicon: 5.6 mA (MCU + radio only, 0 dbm)
p
RFX2401C: 100 mA peak (PA/LNA only, +17.5 dBm Pout)
p
RFX2401C: 27 mA peak (PA/LNA only, +7.5 dBm Pout)
p
[1, 2]
RX current consumption
n
Bluetooth silicon: 5.9 mA (MCU + radio only)
p
RFX2401C: 8.0 mA (PA/LNA only)
p
n
Cypress CYW20719 silicon low power mode support
p
PDS: 61 μA with 512 KB SRAM retention
SDS: 1.6 uA
p
p
HIDOFF (External Interrupt): 400 nA
Functional Capabilities
n
1x ADC with (12-bit ENoB for DC measurement and 13-bit
ENoB for Audio measurement) with 10 channels.
n
1x HCI UART for programming and HCI
n
1x peripheral UART (PUART)
2x SPI (master or slave) blocks (SPI, Quad SPI, MIPI DBI-C)
n
1x I2C master/slave and 1x I2C master only
n
n
I2S/PCM audio interfaces
n
Up to 6 16-bit PWMs
Watchdog Timer
n
Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR)
n
Support
BLE protocol stack supporting generic access profile (GAP)
n
Central, Peripheral, or Broadcaster roles
Hardware Security Engine
n
Benefits
CYBT-483039-02 is fully integrated and certified solution that
provides all necessary components required to operate
Bluetooth communication standards.
n
Proven hardware design ready to use
n
Ultra-flexible supermux I/O designs allows maximum flexibility
for GPIO function assignment
Large non-volatile memory for complex application devel-
n
opment
n
Over-the-air update capable for development or field updates
Bluetooth SIG qualified with QDID and Declaration ID
n
WICED™ Studio provides an easy-to-use integrated design
n
environment (IDE) to configure, develop, program, and test
your Bluetooth application
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-23993 Rev. ** Revised May 22, 2018
utput power of +18 dBm POUT.
PRELIMINARY
CYBT-483039-02
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
References
n Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap
n Development Kits:
p CYBT-483039-EVAL, CYBT-483039-02 Evaluation Board
p CYW920719Q40EVB-01, Evaluation Kit for CYW20719
silicon device
n Test and Debug Tools:
p CYSmart, Bluetooth
p CYSmart Mobile, Bluetooth
®
LE Test and Debug Tool (Windows)
®
LE Test and Debug Tool
n Knowledge Base Article
p KBA97095 - EZ-BLE™ Module Placement
p KBA213976 - FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
p KBA210802 - Queries on BLE Qualification and Declaration
Processes
p KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
p KBA223428- Programming an EZ-BT WICED Module
(Android/iOS Mobile App)
Development Environments
Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)
Cypress' WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design.
WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated development
environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also
leverages many common industry standards.
Technical Support
n Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress
Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers
around the world.
n Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.
n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-23993 Rev. ** Page 2 of 49
PRELIMINARY
CYBT-483039-02
Contents
Overview............................................................................ 4
Functional Block Diagram ........................................... 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 8
Module Connections ...................................................... 10
Connections and Optional External Components ..... 12
Power Connections (VDD and VDDPA) .................... 12
External Reset (XRES).............................................. 13
HCI UART Connections ............................................ 13
External Component Recommendation .................... 13
Critical Components List ........................................... 15
Antenna Design......................................................... 15
Power Amplifier (PA) and Low Noise Amplifier (LNA) 15
Bluetooth Baseband Core ............................................. 16
BQB and Regulatory Testing Support....................... 16
Power Management Unit................................................ 17
Integrated Radio Transceiver........................................ 18
Transmitter Path........................................................ 18
Receiver Path............................................................ 18
Local Oscillator.......................................................... 18
Microcontroller Unit ....................................................... 19
External Reset........................................................... 19
Peripheral and Communication Interfaces .................. 20
I2C............................................................................. 20
HCI UART Interface .................................................. 20
Peripheral UART Interface ........................................ 20
Serial Peripheral Interface......................................... 20
32 kHz Crystal Oscillator........................................... 20
ADC Port ................................................................... 22
GPIO Ports................................................................ 22
PWM.......................................................................... 23
PDM Microphone....................................................... 24
I2S Interface.............................................................. 24
PCM Interface ........................................................... 24
Security Engine ......................................................... 25
Power Modes .................................................................. 26
Firmware.......................................................................... 26
Electrical Characteristics............................................... 27
Core Buck Regulator................................................. 27
Digital LDO................................................................ 29
Digital I/O Characteristics.......................................... 29
ADC Electrical Characteristics .................................. 29
Bluetooth Silicon Current Consumption .................... 30
Chipset RF Specifications ............................................. 31
Timing and AC Characteristics ..................................... 34
UART Timing............................................................. 34
SPI Timing................................................................. 35
I2C Compatible Interface Timing............................... 37
I2S Interface Timing .................................................. 38
Environmental Specifications ....................................... 40
Environmental Compliance ....................................... 40
RF Certification.......................................................... 40
Safety Certification .................................................... 40
Environmental Conditions ......................................... 40
ESD and EMI Protection ........................................... 40
Regulatory Information.................................................. 41
FCC........................................................................... 41
ISED.......................................................................... 42
European Declaration of Conformity ......................... 43
MIC Japan................................................................. 43
Packaging........................................................................ 44
Ordering Information...................................................... 46
Acronyms........................................................................ 47
Document Conventions ................................................. 47
Units of Measure ....................................................... 47
Document History Page................................................. 48
Sales, Solutions, and Legal Information...................... 49
Worldwide Sales and Design Support....................... 49
Products .................................................................... 49
PSoC® Solutions ...................................................... 49
Cypress Developer Community................................. 49
Technical Support ..................................................... 49
Document Number: 002-23993 Rev. ** Page 3 of 49
PRELIMINARY
CYBT-483039-02
Overview
Functional Block Diagram
Figure 1 illustrates the CYBT-483039-02 functional block diagram.
Figure 1. Functional Block Diagram
Note: General Purpose Input/Output pins shown in Figure 1 are configuratble to any specified input or output function in the SuperMux table detailed in Table 5 in the Module
Connections section.
Note: Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYBT-483039-02 is 15.
Module Description
The CYBT-483039-02 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for
the CYBT-483039-02 will not be made until approval is provided by the end customer for this product. The CYBT-483039-02 will be
held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item Specification
Module dimensions
Antenna location dimensions
PCB thickness Height (H) 0.50 ± 0.10 mm
Shield height Height (H) 1.20 mm
Maximum component height Height (H) 1.30 mm typical (Chip Antenna)
Total module thickness (bottom of module to top of shield) Height (H) 1.80 mm typical
See Figure 2 for the mechanical reference drawing for CYBT-483039-02.
Length (X) 12.75 ± 0.15 mm
Width (Y) 18.59 ± 0.15 mm
Length (X) 12.75 mm
Width (Y) 4.82 mm
Document Number: 002-23993 Rev. ** Page 4 of 49
PRELIMINARY
CYBT-483039-02
Figure 2. Module Mechanical Drawing
Bottom View (Seen from Bottom)
Side View
Top View (Seen from Top)
Notes
3. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 8.
Document Number: 002-23993 Rev. ** Page 5 of 49
PRELIMINARY
CYBT-483039-02
Pad Connection Interface
Solder Pad Connections
(Seen from Bottom)
As shown in the bottom view of Figure 2 on page 5, the CYBT-483039-02 has 34 connections to a host board via solder pads (SP).
Ta bl e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-483039-02 module.
Table 2. Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 34 Solder Pad 1.02 mm 0.71 mm 1.02 mm
Figure 3. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.
2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the chip antenna
located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Please refer
to AN96841 for module placement best practices.
3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna may
contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the
host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).
Document Number: 002-23993 Rev. ** Page 6 of 49
PRELIMINARY
CYBT-483039-02
Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-483039-02 Chip Antenna
Document Number: 002-23993 Rev. ** Page 7 of 49
PRELIMINARY
CYBT-483039-02
Recommended Host PCB Layout
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Figure 5, Figure 6, Figure 7, and Ta bl e 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBT-483039-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 5. CYBT-483039-02 Host Layout (Dimensioned) Figure 6. CYBT-483039-02 Host Layout (Relative to Origin)
Document Number: 002-23993 Rev. ** Page 8 of 49
PRELIMINARY
CYBT-483039-02
Ta bl e 3 provides the center location for each solder pad on the CYBT-483039-02. All dimensions are referenced to the center of the
Top View (Seen on Host PCB)
solder pad. Refer to Figure 7 for the location of each module solder pad.
Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location
Solder Pad
(Center of Pad)
1 (0.38, 5.92) (14.96, 233.07)
2 (0.38, 6.93) (14.96, 272.83)
3 (0.38, 7.95) (14.96, 312.99)
4 (0.38, 8.97) (14.96, 353.15)
5 (0.38, 9.98) (14.96, 392.91)
6 (0.38, 11.00) (14.96, 433.07)
7 (0.38, 12.01) (14.96, 472.83)
8 (0.38, 13.03) (14.96, 512.99)
9 (0.38, 14.05) (14.96, 553.15)
10 (0.38, 15.06) (14.96, 592.91)
11 (0.38, 16.08) (14.96, 633.07)
12 (0.38, 17.09) (14.96, 672.83)
13 (1.80, 18.21) (70.87, 716.93)
14 (2.82, 18.21) (111.02, 716.93)
15 (3.84, 18.21) (151.18, 716.93)
16 (4.85, 18.21) (190.94, 716.93)
17 (5.87, 18.21) (231.10, 716.93)
18 (6.88, 18.21) (270.87, 716.93)
19 (7.90, 18.21) (311.02, 716.93)
20 (8.92, 18.21) (351.18, 716.93)
21 (9.93, 18.21) (390.94, 716.93)
22 (10.95, 18.21) (431.10, 716.93)
23 (12.37, 17.09) (487.01, 672.83)
24 (12.37, 16.08) (487.01, 633.07)
25 (12.37, 15.06) (487.01, 592.91)
26 (12.37, 14.05) (487.01, 553.15)
27 (12.37, 13.03) (487.01, 512.99)
28 (12.37, 12.01) (487.01, 472.83)
29 (12.37, 11.00) (487.01, 433.07)
30 (12.37, 9.98) (487.01, 392.91)
31 (12.37, 8.97) (487.01, 353.15)
32 (12.37, 7.95) (487.01, 312.99)
33 (12.37, 6.93) (487.01, 272.83)
34 (12.37, 5.92) (487.01, 233.07)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
Document Number: 002-23993 Rev. ** Page 9 of 49
PRELIMINARY
CYBT-483039-02
Module Connections
Note
4. The CYBT-483039-02 can configure GPIO connections to any Input/Output function described in Tab l e 5 .
5. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15
until the device comes out of reset.
Ta bl e 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available
on the CYBT-483039-02 can be configured to any of the input or output funcitons listed in Ta bl e 5 . Table 4 specifies any function that
is required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux.
Table 4. CYBT-483039-02 Solder Pad Connection Definitions
Pad Pad Name Silicon Pin Name XTALI/O ADC GPIO
1 VDD VDDIO Silicon Power Supply Input (2.0V ~ 3.6V)
2 GND GND Ground
3 XRES RST_N External Reset (Active Low)
4P33 P33 - IN6 33 see Table 5
5P25 P25 - - 33 see Table 5
6P26 P26 - - 33 see Table 5
7P38 P38 - IN1 33 see Table 5
8 P34/P35/P36
9P1 P1 - IN28 33 see Table 5
10 P0 P0 - IN29 33 see Table 5
11 P2 9 P29 - I N10 33 see Table 5
12 P13/P23/P28
13 GND GND Ground
14 P10/P11
15 P17 P17 - IN18 33 see Table 5
16 P7 P7 - - 3 -
17 P6 P6 - - 33 see Table 5
18 P4 P4 - - 3 -
19 XTALO_32K XTALO_32K
XTALI_32K/
20
21 UART_CTS_N BT_UART_CTS_N UART (HCI UART) Clear To Send Input Only
22 UART_RTS_N BT_UART_RTS_N UART (HCI UART) Request To Send Output Only
23 UART_TXD BT_UART_TXD UART (HCI UART) Transmit Data Only
24 UART_RXD BT_UART_RXD UART (HCI UART) Receive Data Only
25 HOST_WAKE BT_HOST_WAKE
26 GND GND Ground
27 GND GND Ground
28 GND GND Ground
29 GND GND Ground
30 GND GND Ground
31 GND GND Ground
32 VDDPA N/A PA/LNA Power Supply Voltage (2.0 ~ 3.6V)
33 GND GND Ground
34 GND GND Ground
P15
[5]
P34
P35
P36
P13
P23
P28
P10
P11
XTALI_32K
P15
-
-
-
External Oscillator
Output (32KHz)
External Oscillator Input
(32KHz)
A signal from the CYBT-483039-02 module to the host indicating that the Bluetooth device requires
IN5 (P34)
IN4 (P35)
IN3 (P36)
IN22 (P13)
IN12 (P23)
IN11 (P28)
IN25 (P10)
IN24 (P11)
-- -
IN20 (P15) 3(P15) 3(P15), see Ta b le 5
3 (P34/P35/P36) 3 see Table 5
3(P13/P23/P28) 3 see Table 5
3 (P10/P11) 3 see Table 5
attention.
SuperMux Capable
[4]
Document Number: 002-23993 Rev. ** Page 10 of 49
PRELIMINARY
CYBT-483039-02
Table 5 details the available Input and Ouput functions that are configurable to any sodler pad in Ta bl e 4 that are marked as SuperMux
capable.
Table 5. GPIO SuperMux Input and Output Functions
Function Input or Output Function Type GPIOs Required Function Connection Description
SWD
SPI 1
SPI 2
PUART
2
C Input/Output
I
2
C 2 Input/Output
I
PCM In Input Audio Input Communication 3
PCM Out Output Audio Output Communication 3
2
S In Input Audio Input Communication 3
I
2
S Out Ouput Audio Output Communication 3
I
PDM Input Microphone 1 ~ 2
Input
Input/Output SWDIO, Serial Wire Debugger I/O
Input/Output
Output SPI 1 DCX (DBI-C DCX 8-bit mode)
Input/Output
Output SPI 2 DCX (DBI-C DCX 8-bit mode)
Input Serial Communication Input
Output Serial Communication Output
Serial Communication and
Debug
Serial Communication
(Master or Slave)
Serial Communication
(Master or Slave)
Serial Communication
(Master or Slave)
Serial Communication
(Master or Slave)
4 ~ 8
4 ~ 8
2
4
2
2
SWDCK, Serial Wire Debugger Clock
SPI 1 Clock
SPI 1 Chip Select
SPI 1 MOSI
SPI 1 MISO
SPI 1 I/O 2 (Quad SPI)
SPI 1 I/O 3 (Quad SPI)
SPI 1 Interrupt
SPI 2 Clock
SPI 2 Chip Select
SPI 2 MOSI
SPI 2 MISO
SPI 2 I/O 2 (Quad SPI)
SPI 2 I/O 3 (Quad SPI)
SPI 2 Interrupt
Periperal UART RX
Peripheral UART CTS
Peripheral UART TX
Peripheral UART RTS
I2C Clock
I2C Data
I2C 2 Clock
I2C 2 Data
PCM Input
PCM Clock
PCM Sync
PCM Output
PCM Clock
PCM Sync
I2S DI, Data Input
I2S WS, Word Select
I2S Clock
I2S DO, Data Output
I2S WS, Word Select
I2S Clock
PDM Input Channel 1
PDM Input Channel 2
Document Number: 002-23993 Rev. ** Page 11 of 49
PRELIMINARY
CYBT-483039-02
Function Input or Output Function Type GPIOs Required Function Connection Description
PWM Channel 0
PWM Channel 1
PWM Channel 2
PWM Output Pulse Width Modulator 1 ~ 6
PWM Channel 3
PWM Channel 4
PWM Channel 5
ACLK Output Auxiliary Clock 1 ~ 2
HIDOFF Output HID-OFF Indicator 1 HID-OFF Indicator to host
Auxiliary Clock 0 (ACLK0)
Auxiliary Clock 1 (ACLK1)
Connections and Optional External Components
Power Connections (VDD and VDDPA)
The CYBT-483039-02 contains two power supply connections, VDD and VDDPA.
VDD is the power supply connection for the Cypress CYW20719 silicon device. VDD accepts a supply input of 1.76 V to 3.63 V.
Ta bl e 1 4 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Ta bl e 1 4.
VDDPA is the power supply connection for the on-module power amplifier/low-noise amplifier. VDDPA accepts a supply input of 2.00 V
to 3.60 V. Table 14 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in
Ta bl e 1 4.
Considerations and Optional Components for Brown Out (BO) Conditions
Power supply design must be completed to ensure that the CYBT-483039-02 module does not encounter a Brown Out condition,
which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to the
module during power up or reset is in the range shown below:
V
≤ VDD ≤ V
IL
Refer to Table 18 for the VIL and V
specifications.
IH
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that
this cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that an
external voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please refer
to Figure 8 for the recommended circuit design when using an external voltage detection IC.
Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC
IH
In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the
module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues
that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition.
Document Number: 002-23993 Rev. ** Page 12 of 49
PRELIMINARY
CYBT-483039-02
External Reset (XRES)
The CYBT-483039-02 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This
action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,
which is an input to the CYBT-483039-02 module (solder pad 3). The CYBT-483039-02 module
resistor on the XRES input
During power on operation, the XRES connection to the CYBT-483039-02 is required to be held low 50 ms after the VDD power supply
input to the module is stable. This can be accomplished in the following ways:
n The host device can connect a GPIO to the XRES of Cypress CYBT-483039-02 module and pull XRES low until VDD is stable.
XRES is recommended to be released 50 ms after VDD is stable.
n If the XRES connection of the CYBT-483039-02 module is not used in the application, a 0.33 uF capacitor may be connected to the
XRES solder pad of the CYBT-483039-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitor
value should result in an XRES release timing of at least 50 ms after VDD stability.
n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.
Refer to Figure 11 on page 19 for XRES operating and timing requirements during power on events.
does not require an external pull-up
HCI UART Connections
The recommendations in this section apply to the HCI UART (Solder Pads 21, 22, 23, and 24). For full UART functionality, all UART
signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired
or capable, then the following connection considerations should be followed for UART RTS and CTS:
n UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.
n UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the
module.
External Component Recommendation
Power Supply Input Options and Circuitry
Two connection options are available for the VDD and VDDPA power supplies:
1. Single supply: Connect VDD and VDDPAto the same supply.
2. Independent supply: Power VDD and VDDPA separately.
In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection.
The ferrite bead should be positioned as close as possible to the module pad connection.
The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).
Document Number: 002-23993 Rev. ** Page 13 of 49
PRELIMINARY
CYBT-483039-02
Figure 9 illustrates the CYBT-483039-02 schematic.
Figure 9. CYBT-483039-02 Schematic Diagram
Document Number: 002-23993 Rev. ** Page 14 of 49
PRELIMINARY
CYBT-483039-02
Critical Components List
Ta bl e 6 details the critical components used in the CYBT-483039-02 module.
Table 6. Critical Component List
Component Reference Designator Description
40-pin QFU2Silicon N Bluetooth Silicon Device - CYW20719
Antenna, 2.4 GHz, ALA321C3-CA1Chip Antenna
PA/LNA, RFX2401CU2PA/LNA
24.000 MHz, 12PFY1Crystal
Antenna Design
Ta bl e 7 details the chip antenna used in the CYBT-483039-02 module.
Table 7. Chip Antenna Specifications
Item Description
2400 – 2500 MHzFrequency Range
2.3 dBi typicalPeak Gain
10.0 dB typicalReturn Loss
Power Amplifier (PA) and Low Noise Amplifier (LNA)
Ta bl e 8 details the PA/LNA that is used on the CYBT-483039-02 module. For more information, see Ta ble 8 .
Table 8. Power Amplifier/Low Noise Amplifier Details
Item Description
Skyworks Inc.PA/LNA Manufacturer
RFX2401CPA/LNA Part Number
Power Supply R 2.0V to 3.6Vange
Ta bl e 9 details the power consumption of the integrated PA/LNA used on the More Part Numbers module. Ta b le 9 only details the
current consumption of the RFX2401C PA/LNA. VDD= 3.3 V, TA = +25°C, measured on the RFX2401C evaluation board, unless
otherwise noted.
Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications
Parameter Test Condition Min Typical Max Unit
mA100Pout = +18dBmTx High Power Current
mA17No RF appliedTx Quiescent Current
mA8No RF appliedRx Quiescent Current
Document Number: 002-23993 Rev. ** Page 15 of 49
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