Cypress Semiconductor 3033 User Manual

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PRELIMINARY

CYBT-013033-01

EZ-BT™ Module

MNKEZ-BLE™ PRoC™ Module

General Description

Benefits

The Cypress CYBT-013033-01 is a certified module supporting dual-mode Bluetooth® Classic (BR/EDR) and Bluetooth® Low Energy (BLE) wireless communication standards. The CYBT-013033-01 is a turnkey solution and includes an onboard crystal oscillator, PCB trace antenna, passive components, and Cypress CYW20707 silicon device.

The CYBT-013033-01 is a custom RF module design intended to provide Bluetooth Classic and BLE communication, and allow up to two GPIO connections for system or module wake events. The CYBT-013033-01 supports UART and BSC (I2C compatible) serial communication, and allows for interface to the Apple MFi Coprocessor chip (via the BSC connection).

The Cypress CYBT-013033-01 complies with Bluetooth Core Specification version 4.2+HS and is designed for use in UART HCI applications. The combination of the Bluetooth Baseband Core (BBC), a Peripheral Transport Unit (PTU), and a Cortex-M3 based microprocessor with on-chip ROM provides a lower and upper layer Bluetooth stack, including Link Controller (LC), Link Manager (LM), and HCI.

Module Features

■

Module size: 10.0 mm × 15.0 mm × 2.25 mm (with shield) Bluetooth dual-mode module, complying with Bluetooth Core

■

Specification 4.2 including BR/EDR/BLE Supports maximum Bluetooth data rates over HCI UART

■

Temperature range: –30 °C to +85 °C

■

ARM® Cortex®-M3 processor

■

Multiple serial interface options:

UART: HCI interface supporting up to 4 Mbps

❐

BSC (I2C compatible): Supporting 400 kHz clock support

■

Apple MFi Coprocessor interface

■

2 GPIOs

■

Certified to FCC, CE, MIC, and IC regulations

FCC ID: WAP3033

❐

IC ID: 7922A-3033

❐

MIC ID: TBD

❐

■

Bluetooth SIG 4.2 qualified

QDID: TBD

❐

Declaration ID: TBD

❐

The CYBT-013033-01 module is provided as a turnkey solution, including all necessary hardware required to use BR, EDR, and BLE communication standards.

■

Proven, qualified, and certified hardware design ready to use

■

Small footprint (10 × 15 mm × 2.25 mm), perfect for space constrained applications

Fully certified module eliminates the time needed for desig n,

■

development and certification processes

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Bluetooth SIG qualified with QDID and Declaration ID Multiple serial communication protocol support

■

Interface option for Apple MFi Authentication Coprocessor

■

WICED Studio provides an easy-to-use integrated design

■

environment (IDE) to configure, develop, program, and test your application.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600 Document Number: 002-18414 Rev. ** Revised January 27, 2017

PRELIMINARY

CYBT-013033-01

Overview............................................................................ 3

Functional Block Diagram ........................................... 3

Module Description...................................................... 3

Pad Connection Interface................................................ 6

Recommended Host PCB Layout ................................... 7

Module Connections............................... ... ... ................... 8

Connections and Optional External Components ....... 8

Power Connections (VDDIN)....................................... 8

External Reset (XRES)................................................ 8

UART Connections...................................................... 8

External Component Recommendation ...................... 8

Critical Components List ........................................... 10

Antenna Design......................................................... 10

Bluetooth Baseband Core ............................................. 11

Bluetooth Low Energy............................................... 11

Link Control Layer.......................................................... 11

Power Management Unit................................................ 12

RF Power Management ............................................ 12

SoC Power Management .......................................... 12

Bluetooth Baseband Core Power Management........ 12

Adaptive Frequency Hopping.................................... 13

Microprocessor Unit....................................................... 14

Overview ...................... ... .......................................... 14

One-Time Programmable Memory................................ 14

Peripheral Transport Unit.............................................. 14

HCI Transport Detection Configuration..................... 14

UART Interface.......................................................... 15

Electrical Characteristics.................................. ... .......... 16

RF Specifications........................................................... 19

Timing and AC Characteristics.................................. 22

Environmental Specifications....................................... 24

Environmental Compliance ....................................... 24

RF Certification.......................................................... 24

Safety Certification.................................................... 24

Environmental Conditions ......................................... 24

ESD and EMI Protection........................................... 24

Regulatory Information........................................... ... .... 25

FCC........................................................................... 25

Industry Canada (IC) Certific ation............................. 26

European R&TTE Declaration of Conformity ............ 26

MIC Japan................................................................. 27

Packaging........................................................................ 28

Ordering Information...................................................... 30

Part Numbering Convention...................................... 30

Acronyms........................................................................ 31

Document Conventions................................. ................ 31

Units of Measure....................................................... 31

Document History Page................................................. 32

Sales, Solutions, and Legal Information...................... 33

Worldwide Sales and Design Support....................... 33

Products.................................................................... 33

PSoC® Solutions ...................................................... 33

Cypress Developer Community................................. 33

Technical Support ..................................................... 33

Document Number: 002-18414 Rev. ** Page 2 of 33

PRELIMINARY

CYBT-013033-01

Overview

Functional Block Diagram

Figure 1 illustrates the CYBT-013033-01 functional block diagram.

Figure 1. Functional Block Diagram

Module Description

The CYBT-013033-01 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical speci fications and module certifications are maintained. Designs should b e held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions PCB thickness Height (H) 0.80 ± 0.10 mm

Shield height Height (H) 1.45 ± 0.10 mm Maximum component height Height (H) 1.05 mm typical (Bluetooth silicon device) T ot al module thickness (bottom of module to highest component) Height (H) 2.25 mm typical

See Figure 2 for the mechanical reference drawing for CYBT-013033-01.

Length (X) 10.00 ± 0.15 mm

Width (Y) 15.00 ± 0.15 mm

Length (X) 5.13 mm

Width (Y) 10.00 mm

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CYBT-013033-01

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (See from Top)

Notes

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page7.

2. The CYBT-013033-01 includes castellated p ad co nnections, den oted as the circul ar openings at the p ad locat ion above. Ref er to the 3 D rendering in Figure 3 on page 5 for a depiction of the pad construction.

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PRELIMINARY

CYBT-013033-01

Figure 3. Module 3D Drawing

Top View With Shield

Top View Without Shield

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PRELIMINARY

CYBT-013033-01

Pad Connection Interface

Bottom View (Seen from Bottom)

Optional Host PCB Keep Out Area Around Chip Antenna

As shown in the bottom view of Figure 2 on page 4, the CYBT-013033-01 connects to the host board via solder pads on the bottom side of the module. Table 2 and Figure 4 detail the solder pad length, width, and pitch dimensions of the CYBT-013033-01 module.

Table 2. Solder Pad Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 13 Castellated Solder Pads 1.02 mm 0.71 mm 1.27 mm

Figure 4. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the ante nna area of the Cypress module (see Figure 2 on page 4) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host boa rd with the PCB trace antenna located at the far corner. This placement minimizes the additional re commended keep o ut area stated in item 2 . Please refer to AN96841 for module placement best practices.

3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB trace antenna may contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 5 (dimensions are in mm).

Figure 5. Optional Additional Host PCB Keep Out Area Around the CYBT-013033-01 PCB Trace Antenna

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CYBT-013033-01

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Figure 6 (Dimensioned) and Figure 7 (Relative to Origin) provide the recommended host PCB layout pattern for the CYBT-013033-01.

Pad length of 1.27 mm (0.655 mm from center of the pad on either side) shown in Figure 7 is the minimum recomme nded host pad length. All dimensions are in millimeters.

Figure 6. CYBT-013033-01 Host Layout (Dimensioned) Figure 7. CYBT-013033-01 Host Layout (Relative to Origin)

Figure 8. Solder Pad Reference Dimensions

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CYBT-013033-01

Module Connections

Notes

3. BT_GPIO_0/BT_DEV_WAKE is a signal from the host to the CYBT-013033-01 that the host requires attention.

4. BT_GPIO_1/BT_HOST_WAKE is a signal from the CYBT-013033-01 module to the host indicating that the Bluetooth device requires attention.

Table 3 details the solder pad connection definitions and available functions for each connection pad. Table 3 lists the solder pads on

the CYBT-013033-01, the silicon device pin, and denotes what functions are available for each solder pad. Table3 also lists the primary/intended function for each solder pad for the application this module was specifically designed for.

Table 3. Solder Pad Connection Definitions

Pad

Number

1 A6 External Reset Hardware Connection Input External Reset (Active Low) 2A8 ✓(SCL) ✓(PWM3) ✓(P3, P29, or P35) Apple SCL Interface 3C7 ✓(SDA) ✓(PWM3) ✓(P12) Apple SDA Interface 4F8 ✓(BT_GPIO_0)

5F7✓(PUART: RXD or TXD) ✓(BT_GPIO_1)

6F5✓(UART_RXD) UART RXD 7G4 ✓(UART_CTS) UART CTS 8F4 ✓(UART_TXD) UART TXD

9F3 ✓(UART_RTS) UART RTS 10 VDDIN Power Supply Input (3.00 to 3.60V) Power Supply Input 11 GND GND Ground Connection 12 GND GND Ground Connection 13 GND GND Ground Connection

Connections and Optional External Components

Silicon

Device Pin

UART BSC (I2C) PWM GPIO_WAKE GPIO Primary Function

[3]

✓(P36 or P38) Device Wake Event Input

[4]

✓(P25 or P32)

UART_TX Debug Host Wake Event Output NC/GPIO

Power Connections (VDDIN)

The CYBT-013033-01 contains one power supply connection, VDDIN.

VDDIN accepts a supply range of 3.00 V to 3.60 V. Table 10 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 10.

External Reset (XRES)

The CYBT-013033-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-013033-01 module.

UART Connections

For full UART functionality, all UAR T signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:

■ UART RTS: Can be left floating, pulled low, or pulled high. RTS

is not critical for initial firmware uploading at power on.

■ UART CTS: Must by pulled low to bypass flow control and to

ensure that continuous data transfers are made from the host to the module.

External Component Recommendation

Power Supply Circuitry

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection.

If used, the recommended ferrite bead value is 330, 100 MHz. (Murata BLM21PG331SN1D).

Apple MFi Authentication Coprocessor Interface

If solder pads 2 and 3 are used as the interface to the Apple MFi authentication coprocessor, 10 Kpull-up resistors should be placed between the MFi coprocessor and the Cypress module.

Document Number: 002-18414 Rev. ** Page 8 of 33

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CYBT-013033-01

Figure 9 illustrates the CYBT-013033-01 schematic.

Figure 9. CYBT-013033-01 Schematic Diagram

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CYBT-013033-01

Critical Components List

Table 4 details the critical components used in the CYBT-013033-01 module.

Table 4. Critical Component List

Component Reference Designator Description

Silicon U1 49-pin BGA Dual-Mode BT/BLE Silicon Device - BCM20707UA2KFFB4G Crystal Y1 24.000 MHz, 12PF

Antenna Design

Table 5 details the PCB trace antenna used in the CYBT-013033-01 module.

Table 5. Trace Antenna Specifications

Item Description

Frequency Range 2400 – 2500 MHz Peak Gain 0.5 dBi typical Return Loss 10 dB minimum

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CYBT-013033-01

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:

Symbol timing recovery, dat a deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver.

Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter.

Bluetooth Low Energy

The CYBT-013033-01 supports dual-mode Bluetooth (BR/EDR/BLE) operation. The CYBT-013033-01 supports all Bluetooth 4.2 and legacy features, with the following benefits:

■ Dual-mode Bluetooth (BR/EDR/BLE)

■ Extended inquiry response (EIR): Shortens the time to retrieve the device name , specific profile, and operating mode.

■ Encryption pause resume (EPR): Enables the use of Bluetooth

■ Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life.

■ Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required.

■ Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link

timeout supervision.

■ Quality of Service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human

interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements.

■ Secure connections (BR/EDR)

■ Fast advertising interval

■ Piconet clock adjust

■ Connectionless broadcast

■ LE privacy v1.1

■ Low duty cycle directed advertising

■ LE dual mode topology

technology in a much more secure environment.

slot usage, optimally segments and

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth Controller.

■ Major states: ❐ Standby ❐ Connection

■ Substates: ❐ Page

❐ Page Scan ❐ Inquiry ❐ Inquiry Scan ❐ Sniff

Document Number: 002-18414 Rev. ** Page 11 of 33

Link

PRELIMINARY

CYBT-013033-01

Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked through power management registers or packet handling in the baseband core. This section contains descriptions of the PMU features.

RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions, accordingly.

SoC Power Management

The host can place the device in a sleep state, in which all nonessential blocks are powered off and all nonessential clocks are disabled. Power to the digital core is maintained so that the state of the registers and RAM is not lost. In addition, the CYBT-013033-01 internal LPO clock is applied to the internal sleep controller so that the chip ca n wake automatically at a spe cified time or b ased on signaling from the host. The goal is to limit the current consumption to a minimum, while maintaining the ability to wake up and resume a connection with minimal latency.

If a scan or sniff session is enabled while the device is in Sleep mode, the device automatically will wake up for the scan/sniff event, then go back to sleep when the event is done. In this case, the device uses its internal LPO-based timers to trigger the periodic wake up. While in Sleep mode, the transports are idle. However, the device can wake up at any time. If signaled to wake up while a scan or sniff session is in progress, the session continues but the device will not sleep between scan/sniff events. Once Sleep mo de is enabled, the wake signaling mechanism can also be thought of as a sleep signaling mechanism, since removing the wake status will often cause the device to sleep.

In addition to a Bluetooth device wake signaling mechanism, there is a host wake signaling mechanism. This feature provides a way for the Bluetooth device to wake up a host that is in a reduced power state.

Table 6 and Table 7 describe the mechanism available for the device and the host to signal a wake status to each other.

Table 6. Mechanism for Device and Host to Signal Wake Status

Bluetooth device WAKE (BT_DEV_WAKE - Pad 4) and Host WAKE (and BT_HOST_WAKE - Pad 5) signaling

The BT_DEV_WAKE signal allows the host to wake the BT device, and BT_HOST_WAKE is an output that allows the BT device to wake the host.

Table 7. Power Control Pad Summary

Pin Name

(Pad Number)

BT_DEV_WAKE

(Pad 4)

BT_HOST_WAKE

(Pad 5)

XRES (Pad 1) BT input Used to place the chip in reset. XRES is active-low.

Direction Description

Bluetooth device wake-up: Signal from the host to the Bluetooth device that the host requires attention.

Host output

BT input

BT output

Host input

■ Asserted = Bluetooth device must wake up or remain awake.

■ Deasserted = Bluetooth device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low. By default, BT_DEV_WAKE is active-low (if BT-WAKE is low it requires the device to wake up or remain awake).

Host wake-up. Signal from the Bluetooth device to the host indicating that Bluetooth device requires attention.

■ Asserted = Host device must wake up or remain awake.

■ Deasserted = Host device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

Bluetooth Baseband Core Power Management

The following are low-power operations for the Bluetooth Baseband Core (BBC):

■ Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

■ Blu etooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the CYBT-013033-01 runs on the

low-power oscillator and wakes up after a predefined time period.

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CYBT-013033-01

Adaptive Frequency Hopping

The CYBT-013033-01 supports host channel classification and dynamic channel classification Adaptive Frequency Hopping (AFH) schemes, as defined in the Bluetooth specification.

Host channel classification enables the host to set a predefined hopping map for the device to follow. If dynamic channel classification is enabled, the device gathers link quality statistics on a channel-by-channel basis to facilitate channel

assessment and channel map selection. To provide a more accurate frequency hop map, link quality is determined using both RF and baseband signal processing.

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CYBT-013033-01

Microprocessor Unit

Overview

The CYBT-013033-01 microprocessor unit runs software from the Link Control (LC) layer up to the stack and Application layer. In the HCI mode of operation the stack will be run on the external host. The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code.

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations, including automatic host transport selection from UART transport without external NVRAM. At power-up, the lower layer protocol stack is executed from the internal ROM.

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded from the host to the device through the UART transport.

One-Time Programmable Memory

The CYBT-013033-01 includes a One-Time Programmable (OTP) memory, allowing manufacturi ng customization and avoiding the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is programmed or not, it is disabled after the boot process completes to save power.

The OTP size is 2048 bytes. The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be

downloaded into RAM after the CYBT-013033-01 boots up and is ready for host transport communication. The OTP contents are limited to:

■ Parameters required prior to downloading user configuration to RAM.

■ Parameters unique to each part and each customer (i.e., the BD_ADDR, and software license key).

The following are typical parameters programmed into the OTP memory:

■ BD_ADDR

■ Software license key

■ Output power calibration

■ Frequency trimming

■ Initial status LED drive configuration

The OTP contents also include a static error correction table to improve yield during the programming process as well as forward error correction codes to eliminate any long-term reliability problems. The OTP contents associated with error correction are not visible by customers.

Peripheral Transport Unit

This section discusses the UART peripheral interface. The CYBT-013033-01 has a 1040-byte transmit and receive FIFO, which is large enough to hold the entire payload of the largest EDR Bluetooth packet (3-DH5).

HCI Transport Detection Configuration

Note: HCI transport detection is only valid for the HCI operating mode.

The CYBT-013033-01 supports the following interface types for the HCI transport from the host:

■ UART (H4)

Only one host interface can be active at a time. The firmware performs a transport detect function at boot-time to determine which host is the active transport. It can auto-detect UART interfaces, but the SPI interface must be selected by strapping the SCL pin to 0.

■ The complete algorithm is summarized as follows:

■ Determine if any local NVRAM contains a valid configuration file. If it does and a transport configuration entry is present, select the

active transport according to entry, and then exit the transport detection routine.

■ Look for CTS_N = 0 on the UART interface. If it is present, select UART.

■ Repeat Step 2 and Step 3 until transport is determined.

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CYBT-013033-01

UART Interface

The CYBT-013033-01 shares a single UART for Bluetooth. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.

UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.2 UART HCI specification: H4, and a custom Extended H4. The default baud rate is 115.2 Kbaud.

The CYBT-013033-01 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP). It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYBT-013033-01 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%.

Table 8. Example of Common Baud Rates

Desired Rate Actual Rate Error (%)

4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70

921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16

57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16

9600 9600 0.00

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CYBT-013033-01

Electrical Characteristics

Note: All voltages listed in Table 9 are referenced to V Table 9. Absolute Maximum Voltage

Requirement Parameter

Ambient Temperatu re of Operatio n –30 25 85 °C Storage temperature –40 – 150 °C VDD Core 1.14 1.2 1.26 V VDD IO 3 3.3 3.6 V VDD RF (excluding class 1 PA) 1.14 1.2 1.26 V VDD PA (class 1 mode) 2.25 2.5 2.75 V

Table 10. Power Supply Specifications

Parameter Min. Typ. Max. Units Comments

VDDIN input 3.0 3.3 3.6 V – VDDIN_Ripple – – 100 mV VBAT input 3.0 3.3 3.6 V Internally routed on CYBT-013033-01 module

2.5V LDO input 3.0 3.3 3.6 V Internally routed on CYBT-013033-01 module

Table 11. VDDC LDO Electrical Specifications

Parameter Conditions Min. Typ. Max. Units

Input Voltage – 1.62 3.3 3.6 V Nominal Output

Voltage DC Accuracy Accuracy at any step, including bandgap reference. –5 – 5 %

Output Voltage Programmability

Load Current – – – 40 mA Dropout Voltage I Line Regulation Vin from 1.62V to 3.6V, I

Load Regulation

Quiescent Current

Power Down Current Vin = 3.3V @25C – 0.2 – A

PSRR

Over Current Limit – 100 – – mA Turn-on Time

Range 0.89 – 1.34 V Step Size –30–mV

= 40 mA – – 200 mV

load

= 1 mA to 40 mA, Vout = 1.2V , Package + PCB

load

R = 0.3W No load @Vin = 3.3V – 18 23 A Max load @Vin = 3.3V – – 0.56 0.65 mA

Vin = 3.3, Vout = 1.2V,

= 40 mA

load

VBAT = 3.3V, BG already on, LDO OFF to ON,

F, 90% of Vout

Co = 1

––1.2–V

= 40 mA – – 0.2 %Vo/V

load

DDIN

Specification

Minimum Nominal Maximum

3.0V supply Ripple frequency of 100 kHz to 750 kHz

– 0.02 0.05 %Vo/mA

1 kHz 65 – – dB 10 kHz 60 – – dB 100 kHz 55 – – dB

– – 100 s

Units

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CYBT-013033-01

Table 11. VDDC LDO Electrical Specifications (continued)

Parameter Conditions Min. Typ. Max. Units

External Output Capacitor

External Input Capacitor

Turn-on Time

Ceramic cap with ESR 

0.5 0.814.7F

Ceramic, X5R, 0402, ±20%, 10V. – 1 – F VBAT= 3.3V, BG already on, LDO OFF to ON,

F, 90% of Vout

Co = 1

– – 100 s

Table 12. BTLDO_2P5 Electrical Specifications

Parameters Conditions Min Typ Max Units

Min = Vo + 0.2V = 2.7V

Input supply voltage, Vin

(for Vo= 2.5V) Dropout voltage requirement must be met under maximum load for performance

3.0 3.3 3.6 V

specs.

Nominal output voltage, Vo

Output voltage programmability

Default = 2.5V – 2.5 – V Range

Accuracy at any step (including line/load regulation), load >0.1 mA

2.2 –5

–

2.8 5

Dropout voltage At max load – – 200 mV Output current – 0.1 – 70 mA

Quiescent current

Leakage current

No load; Vin = Vo + 0.2V Max load @ 70 mA; Vin = Vo + 0.2V

Power-down mode. At junction temperature 85°C.

–

–1.55A

660

700

A

Line regulation Vin from (Vo + 0.2V) to 3.6V, max load – – 3.5 mV/V Load regulation Load from 1 mA to 70 mA, Vin = 3.6V – – 0.3 m V/mA

PSRR

Vin  Vo + 0.2V, Vo = 2.5V, Co = 2.2 F, max load, 100 Hz to 100 kHz

20 – – dB

LDO turn-on time LDO turn-on time when rest of chip is up – – 150 s

Table 13. Digital I/O Characteristics

Characteristics Symbol Minimum Typical Maximum Unit

Input low voltage (VDDIN = 3.3V) V Input high voltage (VDDIN = 3.3V) V Output low voltage V Output high voltage V Input low current I Input high current I Output low current (VDDIN = 3.3V, V Output high current (VDDIN = 3.3V, V

= 0.4V) I

= 2.9V) I

Input capacitance C

IH OL OH IL IH

––0.8V

2.0 – – V ––0.4V

VDDIN – 0.4V – – V

––1.0A ––1.0A ––2.0mA ––4.0mA ––0.4pF

Document Number: 002-18414 Rev. ** Page 17 of 33

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Table 14. Current Consumption — Common Use Cases

Condition Current (mA)

Receive (1 Mbps) current level when receiving a basic rate packet. 12.5 Transmit (1 Mbps) current level when transmitting a basic rate packet. 26.5 Receive (EDR) current level when receiving a 2 or 3 Mbps rate packet. 12.5 Transmit (EDR) current level when transmitting a 2 or 3 Mbps rate packet. 20.0 DM1/DH1 average current during a basic rate maximum throughput connection that includes only this packet type. 14.5 DM3/DH3 average current during a basic rate maximum throughput connection that includes only this packet type. 17.0 DM5/DH5 average current during a maximum basic rate throughput connection that includes only this packet type. 17.5 Sleep UART transport active. External LPO clock available. 0.120 Inquiry Scan (1.28 sec.). Periodic scan rate is 1.28 sec. 0.188 Page Scan (R1) Periodic scan rate is R1 (1.28 sec). 0.188 Inquiry Scan + Page Scan (R1)

Both inquiry and page scans are interlaced together at a 1.28 seconds periodic scan rate. Sniff master (500 ms) attempt and timeout parameters set to 4. Quality connection that rarely requires more than

a minimum packet exchange. Sniff slave (500 ms) attempt and timeout parameters set to 4. Quality connection that rarely requires more than a

minimum packet exchange. Sniff (500 ms) + Inquiry or Page Scan (R1) 0.700 Sniff (500ms) + Inquiry Scan + Page Scan (R1) 0.800

0.286

0.415

0.408

Document Number: 002-18414 Rev. ** Page 18 of 33

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RF Specifications

Table 15. Receiver RF Specifications

Parameter Conditions Minimum Typical

General

Frequency range – 2402 – 2480 MHz RX sensitivity

[8]

Maximum input GFSK, 1 Mbps – – –20 dBm Maximum input p/4-DQPSK, 8-DPSK, 2/3 Mbps – – –20 dBm

Interference Performance

■ GFSK Modulation

[9]

C/I cochannel GFSK, 0.1% BER – 9.5 11 dB C/I 1 MHz adjacent channel GFSK, 0.1% BER – –5 0 dB C/I 2 MHz adjacent channel GFSK, 0.1% BER – –40 –30.0 dB

3 MHz adjacent channel GFSK, 0.1% BER – –49 –40.0 dB

C/I > C/I image channel GFSK, 0.1% BER – –27 –9.0 dB C/I 1 MHz adjacent to image channel GFSK, 0.1% BER – –37 –20.0 dB

■ QPSK Modulation

[10]

C/I cochannel p/4-DQPSK, 0.1% BER – 11 13 dB C/I 1 MHz adjacent channel p/4-DQPSK, 0.1% BER – –8 0 dB C/I 2 MHz adjacent channel p/4-DQPSK, 0.1% BER – –40 –30.0 dB

3 MHz adjacent channel 8-DPSK, 0.1% BER – –50 –40.0 dB

C/I > C/I image channel p/4-DQPSK, 0.1% BER – –27 –7.0 dB C/I 1 MHz adjacent to image channel p/4-DQPSK, 0.1% BER – –40 –20.0 dB

■ 8PSK Modulation

[11]

C/I cochannel 8-DPSK, 0.1% BER – 17 21 dB C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER – –5 5 dB C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER – –40 –25.0 dB

3 MHz adjacent channel 8-DPSK, 0.1% BER – –47 –33.0 dB

C/I > C/I Image channel 8-DPSK, 0.1% BER – –20 0 dB C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER – –35 –13.0 dB

Notes

5. All specifications are single ended. Unused inputs are left open.

6. All specifications, except typical, are for industrial temperatures.

7. Typical operating conditions are 3.3V VBAT and 25°C ambient temperature.

8. The receiver sensitivity is measured at BER of 0.1% on the device interface.

9. Typical GFSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –45 dB, –42 dB, and –41 dB, respectively.

10.Typical QPSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –46 dB, –43 dB, and –42 dB, respectively.

11.Typical 8PSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –50 dB, –45 dB, and –45 dB, respectively.

12.Meets this specification using front-end band pass filter.

13.Numbers are referred to the pin output with an external BPF filter.

14.f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n * 1 MHz, where “n” is 3, 4, or 5. For the typical case, n = 4.

15.Includes baseband radiated emissions.

[5, 6]

[7]

Maximum Unit

GFSK, 0.1% BER, 1 Mbps – –93.5 – dBm p/4-DQPSK, 0.01% BER, 2 Mbps – –95.5 – dBm 8-DPSK, 0.01% BER, 3 Mbps – –89.5 – dBm

Document Number: 002-18414 Rev. ** Page 19 of 33

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CYBT-013033-01

[5, 6]

Table 15. Receiver RF Specifications

Parameter Conditions Minimum Typical

Out-of-Band Blocking Performance (CW)

(continued)

[12]

[7]

Maximum Unit

30 MHz–2000 MHz 0.1% BER – –10.0 – dBm 2000–2399 MHz 0.1% BER – –27 – dBm 2498–3000 MHz 0.1% BER – –27 – dBm 3000 MHz–12.75 GHz 0.1% BER – –10.0 – dBm

Out-of-Band Blocking Performance, Modulated Interferer

776–764 MHz CDMA – –10 824–849 MHz CDMA – –10 1850–1910 MHz CDMA – –23 824–849 MHz EDGE/GSM – –10 880–915 MHz EDGE/GSM – –10 1710–1785 MHz EDGE/GSM – –23 1850–1910 MHz EDGE/GSM – –23 1850–1910 MHz WCDMA – –23 1920–1980 MHz WCDMA – –23

Intermodulation Performance

[14]

[13] [13] [13] [13] [13] [13] [13] [13] [13]

–dBm –dBm –dBm –dBm –dBm –dBm –dBm –dBm –dBm

BT, Df = 4 MHz – –39.0 – – dBm

Spurious Emissions

[15]

30 MHz to 1 GHz – – – –62 dBm 1–12.75 GHz – – – –47 dBm 65–108 MHz FM RX – –147 – dBm/Hz 746–764 MHz CDMA – –147 – dBm/Hz 851–894 MHz CDMA – –147 – dBm/Hz 925–960 MHz EDGE/GSM – –147 – dBm/Hz 1805–1880 MHz EDGE/GSM – –147 – dBm/Hz 1930–1990 MHz PCS – –147 – dBm/Hz 2110–2170 MHz WCDMA – –147 – dBm/Hz