Cypress Semiconductor 3027 User Manual
PRELIMINARY
CYBT-353027-02
EZ-BT™ WICED Module
General Description
Note
1. The values in this section were calculated for a 90% efficient DC-DC at 3V in HCI mode, and based on a Class I configuration bench-marked at Class II. Lower values
are expected for a class II configuration using an external LPO and corresponding PA configuration.
The CYBT-353027-02 is a fully integrated Bluetooth Smart
Ready wireless module. The CYBT-353027-02 includes an
onboard crystal oscillator, passive components, flash memory,
and the Cypress CYW2070x silicon device.
The CYBT-353027-02 supports peripheral functions (ADC,
timers), UART, I2C, and SPI communication, and a Bluetooth
audio interface. The CYBT-353027-02 includes a royalty-free
BLE stack compatible with Bluetooth 5.0 in a 9.0 × 9.0 × 1.75 mm
SMT package.
The CYBT-353027-02 includes 512 KB of onboard serial flash
memory and is designed for standalone operation. The
CYBT-353027-02 uses an integrated power amplifier to achieve
Class I or Class II output power capability.
The CYBT-353027-02 is fully qualified by Bluetooth SIG and is
targeted at space constrained applications.
Module Description
n Module size: 9.00 mm × 9.00 mm × 1.75 mm
n Bluetooth 5.0 Qualified Smart Ready module
p QDID: TBD
p Declaration ID: TBD
n Certified to FCC, ISED, MIC, and CE regulations
n Castelated solder pad connections for ease-of-use
n 512-KB on-module serial flash memory
n Up to 8 GPIOs
n Temperature range: -30 °C to +85 °C
n Cortex-M3 32-bit processor
n Maximum TX output power:
p +12 dbm for Bluetooth Classic
p +9 dBm for Bluetooth Low Energy
n RX Receive Sensitivity:
p –93.5 dBm for Bluetooth Classic
p –96.5 dBm for Bluetooth Low Energy
Power Consumption
n TX average current consumption: 52.5 mA (EDR) at 8 dBm
n RX average current consumption: 26.4 mA (EDR)
n Low power mode support
p Deep Sleep: 2.69 uA
[1]
Functional Capabilities
n Σ-Δ ADC for audio (12 bits) and DC measurement (10 bits)
n Serial Communications interface compatible with I
n Master Serial Peripheral Interface (SPI) support
n HCI interface through UART
n PCM/I2S Audio interface
n Two-wire Global Coexistence Interface (GCI)
n Programmable output power control
n Supports extended synchronous connections (eSCO), for
2
C slaves
enhanced voice quality by allowing for retransmission of
dropped packets
n Bluetooth wideband speech support
Benefits
CYBT-353027-02 provides all necessary components required
to operate BLE and/or BR/EDR communication standards.
n Proven hardware design ready to use
n Dual-mode operation eliminates the need for multiple modules
n Cost optimized for applications without space constraints
n Nonvolatile memory for self-sufficient operation and
Over-the-air updates
n Bluetooth SIG Listed with QDID and Declaration ID
n Fully certified module eliminates the time needed for design,
development and certification processes
n WICED™ STUDIO provides an easy-to-use integrated design
environment (IDE) to configure, develop, and program a
Bluetooth application
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-23132 Rev. ** Revised March 14, 2018
PRELIMINARY
CYBT-353027-02
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
References
n Overview: EZ-BLE/BT Module Portfolio, Module Roadmap
n Development Kits:
p CYBT-353027-EVAL, CYBT-353027-02 Evaluation Board
n Test and Debug Tools:
p CYSmart, Bluetooth
p CYSmart Mobile, Bluetooth
®
LE Test and Debug Tool (Windows)
®
LE Test and Debug Tool
n Knowledge Base Article
p KBA97095 - EZ-BLE™ Module Placement
p KBA213976 - FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
p KBA210802 - Queries on BLE Qualification and Declaration
Processes
p KBA218122 - 3D Model Fils for EZ-BLE/EZ-BT Modules
(Android/iOS Mobile App)
Development Environments
Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)
Cypress' WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design.
WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated development
environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also
leverages many common industry standards.
Technical Support
n Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress
Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers
around the world.
n Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.
n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-23132 Rev. ** Page 2 of 50
PRELIMINARY
CYBT-353027-02
Contents
Overview............................................................................ 4
Functional Block Diagram ........................................... 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 7
Module Connections ........................................................ 9
Connections and Optional External Components....... 10
Power Connections (VDDIN)..................................... 10
External Reset (XRES).............................................. 10
Multiple-Bonded GPIO Connections ......................... 11
Critical Components List ........................................... 13
Antenna Design......................................................... 13
Bluetooth Baseband Core ............................................. 14
Link Control Layer ..................................................... 14
Frequency Hopping Generator.................................. 15
Power Management Unit................................................ 15
RF Power Management ............................................ 15
Host Controller Power Management ......................... 15
BBC Power Management.......................................... 15
Microcontroller Unit ....................................................... 16
NVRAM Configuration Data and Storage.................. 16
External Reset (XRES).............................................. 16
Integrated Radio Transceiver........................................ 18
Transmitter Path........................................................ 18
Receiver Path............................................................ 18
Local Oscillator Generation....................................... 18
Calibration ................................................................. 18
Internal LDO .............................................................. 18
Collaborative Coexistence............................................. 19
Global Coexistence Interface ........................................ 19
SECI I/O .................................................................... 19
Peripheral and Communication Interfaces .................. 20
Cypress Serial Communications Interface ................ 20
HCI UART Interface .................................................. 20
Peripheral UART Interface ........................................ 21
Serial Peripheral Interface......................................... 21
.PCM Interface .......................................................... 22
Clock Frequencies..................................................... 22
ADC Port ................................................................... 22
GPIO Port.................................................................. 23
Electrical Characteristics............................................... 24
Chipset RF Specifications ............................................. 26
Timing and AC Characteristics ..................................... 29
UART Timing............................................................. 29
SPI Timing................................................................. 30
BSC Interface Timing ................................................ 32
PCM Interface Timing...........................................
I2S Interface Timing .................................................. 37
Environmental Specifications ....................................... 39
Environmental Compliance ....................................... 39
RF Certification.......................................................... 39
Safety Certification .................................................... 39
Environmental Conditions ......................................... 39
ESD and EMI Protection ........................................... 39
Regulatory Information.................................................. 40
FCC........................................................................... 40
ISED.......................................................................... 41
European Declaration of Conformity ......................... 42
MIC Japan................................................................. 42
Packaging........................................................................ 43
Ordering Information...................................................... 45
Acronyms........................................................................ 46
Document Conventions ................................................. 48
Units of Measure ....................................................... 48
Document History Page................................................. 49
Sales, Solutions, and Legal Information...................... 50
Worldwide Sales and Design Support....................... 50
Products .................................................................... 50
PSoC® Solutions ...................................................... 50
Cypress Developer Community................................. 50
Technical Support ..................................................... 50
..... 33
Document Number: 002-23132 Rev. ** Page 3 of 50
PRELIMINARY
CYBT-353027-02
Overview
Functional Block Diagram
Figure 1 illustrates the CYBT-353027-02 functional block diagram.
Figure 1. Functional Block Diagram
Module Description
The CYBT-353027-02 module is a complete module designed to be soldered to the application’s main board.
Module Dimensions and Drawing
Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the
physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item Specification
Module dimensions
Antenna area dimensions
PCB thickness Height (H) 0.50 ± 0.10 mm
Shield height Height (H) 1.25 mm typical
Maximum component height Height (H) 1.25 mm typical
Total module thickness (bottom of module to highest component) Height (H) 1.75 mm typical
See Figure 2 for the mechanical reference drawing for CYBT-353027-02.
Length (X) 9.00 ± 0.15 mm
Width (Y) 9.00 ± 0.15 mm
Length (X) 6.00 mm
Width (Y) 2.50 mm
Document Number: 002-23132 Rev. ** Page 4 of 50
PRELIMINARY
CYBT-353027-02
Figure 2. Module Mechanical Drawing
Bottom View (Seen from Bottom)
Top View (Seen from Top)
Side View
Notes
2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.
Document Number: 002-23132 Rev. ** Page 5 of 50
PRELIMINARY
CYBT-353027-02
Pad Connection Interface
As shown in the bottom view of Figure 2 on page 5, the CYBT-353027-02 connects to the host board via solder pads on the backside
of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-353027-02 module.
Table 2. Connection Description
Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch
SP 24 Solder Pads 0.71 mm 0.51 mm 1.05 mm
Figure 3. Solder Pad Dimensions (Seen from Bottom
To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.
2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace
antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to
AN96841 for module placement best practices.
Figure 4. Recommended Host PCB Keep Out Area Around the CYBT-353027-02 Antenna
Document Number: 002-23132 Rev. ** Page 6 of 50
PRELIMINARY
CYBT-353027-02
Recommended Host PCB Layout
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Figure 5, Figure 6, Figure 7, and Ta b le 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBT-353027-02. Dimensions are in millimeters unless otherwise noted. Pad length of 0.96 mm (0.48 mm from center of the pad on
either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 5. CYBT-353027-02 Host Layout (Dimensioned) Figure 6. CYBT-353027-02 Host Layout (Relative to Origin)
Document Number: 002-23132 Rev. ** Page 7 of 50
PRELIMINARY
CYBT-353027-02
Ta bl e 3 provides the center location for each solder pad on the CYBT-353027-02. All dimensions are referenced to the center of the
Top View (Seen on Host PCB)
solder pad. Refer to Figure 7 for the location of each module solder pad.
Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location
Solder Pad
(Center of Pad)
1 (0.23, 2.31) (9.06, 119.29)
2 (0.23, 3.36) (9.06, 132.28)
3 (0.23, 4.41) (9.06, 201.97)
4 (0.23, 5.46) (9.06, 243.31)
5 (0.23, 6.51) (9.06, 284.65)
6 (0.23, 7.56) (9.06, 297.64)
7 (0.82,8.77) (32.28, 345.27)
8 (1.88,8.77) (74.02, 345.27)
9 (2.93,8.77) (115.35, 345.27)
10 (3.98,8.77) (156.69, 345.27)
11 (5.03,8.77) (198.03, 345.27)
12 (6.08,8.77) (239.37, 345.27)
13 (7.13,8.77) (280.71, 345.27)
14 (8.18,8.77) (322.05, 345.27)
15 (8.77,7.56) (345.27, 297.64)
16 (8.77,6.51) (345.27,256.30)
17 (8.77,5.46) (345.27, 214.96)
18 (8.77,4.41) (345.27, 173.62)
19 (8.77,3.36) (345.27, 132.28)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
Document Number: 002-23132 Rev. ** Page 8 of 50
PRELIMINARY
CYBT-353027-02
Module Connections
Note
3. The CYBT-353027-02 contains a single SPI (SPI1) peripheral supporting master configuration. SPI2 is used for on-module serial memory interface.
4. SPI2_CS_N is internally routed on the module to on-board serical flash memory. SPI2_CS_N is made available on module pad 7 to be used for Recover Mode
operation only.
Ta bl e 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-353027-02 module.
Ta bl e 4 lists the solder pads on the CYBT-353027-02 module, the silicon device pin, and denotes what functions are available for each
solder pad.
Table 4. CYBT-353027-02 Solder Pad Connection Definitions
Pad Name
Pad
1 GND GND Ground
2GPIO_4
3P11
4P3
5 XRES RST_N External Reset (Active Low)
6GPIO_5
7 SPI2_CS_N SPI2_CSN
8GPIO_0 BT_GPIO_0
9GPIO_1 BT_GPIO_1
10 UART_TXD BT_UART_TXD HCI UART Transmit Data
11 CLK_REQ BT_CLK_REQ
12 UART_RXD BT_UART_RXD HCI UART Receive Data
13 VDDIN VDDO VDDIN (2.3V ~ 3.6V)
14 GND GND Ground
15 UART_RTS BT_UART_RTS_N HCI UART Request To Send Output
16 GPIO_3 BT_GPIO_3/P0 PUART_TX/P0
17 UART_CTS BT_UART_CTS_N HCI UART Clear To Send Input
18 GPIO_6
19 GND GND Ground
Silicon Port Pin
Name(s)
GPIO_4/P1/I2S_C
LK/PCM_CLK
P11/I2S_WS/PCM
_SYNC
P3/I2S_DI/PCM_I
N
BT_GPIO_5/P8/P3
BT_GPIO_6/P9/I2
3
[4]
S_DO/PCM_OUT
UART SPI
PUART_RX/P33
[3]
SPI1_MISO/P1
(master)
SPI1_CLK
(master)
SPI2_CS_N
SPI1_MOSI/P0
(master)
I2C ADC COEX CLK/XTAL GPIO
IN28/P1 3
IN24 3
SDA 3
IN27/P8
IN6/P33
3
(GCI_SEC
I_OUT)
Used for shared-clock applications
IN29/P0 3
SCL IN26/P93(GCI_SEC
I_IN)
ACK1/P33 3
(Dev
Wake)
(Host
Wake)
3
3
3
Other
PCM_CLK
I2S_CLK
PCM_Sync
I2S_WS
PCM_DI
I2S_DI
I2S_DO
PCM_Out
Document Number: 002-23132 Rev. ** Page 9 of 50
PRELIMINARY
CYBT-353027-02
Connections and Optional External Components
Power Connections (VDDIN)
The CYBT-353027-02 contains one power supply connection, VDDIN. VDDIN accepts a supply input range of 2.3 V to 3.6 V for
CYBT-353027-02. Ta b le 1 1 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as
shown in Table 11.
It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned
as close as possible to the module pin connection and the recommended ferrite bead value is 330 Ω, 100 MHz.
Considerations and Optional Components for Brown Out (BO) Conditions
Power supply design must be completed to ensure that the CYBT-353027-02 module does not encounter a Brown Out condition,
which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the
module during power up or reset is in the following range:
V
≤ VDDIN ≤ V
IL
Refer to Table 12 for the VIL and V
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that
this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an
external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to
Figure 8 for the recommended circuit design when using an external voltage detection IC.
Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC
specifications.
IH
IH
In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the
module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues
that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition.
External Reset (XRES)
The CYBT-353027-02 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This
action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,
which is an input to the CYBT-353027-02 module (solder pad 5). The CYBT-353027-02 module
resistor on the XRES input
During power-on operation, the XRES connection to the CYBT-353027-02 is required to be held low 50 ms after the VDD power supply
input to the module is stable. This can be accomplished in the following ways:
n The host device should connect a GPIO to the XRES of the Cypress CYBT-353027-02 module and pull XRES low until VDD is
stable. XRES is recommended to be released 50 ms after VDDIN is stable.
n If the XRES connection of the CYBT-353027-02 module is not used in the application, a 10-µF capacitor may be connected to the
XRES solder pad of the CYBT-353027-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The
capacitor value should result in an XRES release timing of 50 ms after VDDIN stability.
n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.
Refer to Figure 11 on page 17 for XRES operating and timing requirements during power-on events.
Document Number: 002-23132 Rev. ** Page 10 of 50
does not require an external pull-up
PRELIMINARY
CYBT-353027-02
Multiple-Bonded GPIO Connections
The CYBT-353027-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used,
only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED
Studio SDK. For details on the port pins that are multiple-bonded, refer to the GPIO Port section of this document.
Document Number: 002-23132 Rev. ** Page 11 of 50
PRELIMINARY
CYBT-353027-02
Figure 9 illustrates the CYBT-353027-02 schematic.
Figure 9. CYBT-353027-02 Schematic Diagram
Document Number: 002-23132 Rev. ** Page 12 of 50
PRELIMINARY
CYBT-353027-02
Critical Components List
Ta bl e 5 details the critical components used in the CYBT-353027-02 module.
Table 5. Critical Component List
Component Reference Designator Description
Silicon U1 36-pin FBGA BT/BLE Silicon Device - CYW2070X
Silicon U2 8-pin TDF8N, 512K Serial Flash
Crystal Y1 24.000 MHz, 12PF
Antenna Design
Ta bl e 6 details trace antenna used in the CYBT-353027-02 module. For more information, see Ta bl e 6.
Table 6. Chip Antenna Specifications
Item Description
Frequency Range 2400–2500 MHz
Peak Gain -1.0 dBi typical
Return Loss 10 dB minimum
Document Number: 002-23132 Rev. ** Page 13 of 50
PRELIMINARY
CYBT-353027-02
Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and
packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition
to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions
are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:
n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
Bluetooth Features
CYBT-353027-02 is qualified to the Bluetooth 5.0 specification. CYBT-353027-02 supports all Bluetooth 4.2 and legacy features, with
the following benefits.
n Dual-mode Bluetooth (BT Classic and BLE) operation
n Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode.
n Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment.
n Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life.
n Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required.
n Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link
timeout supervision.
n Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human
interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary
flag (PBF) enhancements.
n Secure connections (BR/EDR)
n Fast advertising interval
n Piconet clock adjust
n Connectionless broadcast
n LE privacy v1.1
n Low duty cycle directed advertising
n LE dual mode topology
Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the LCU.
n States:
p Standby
p Connection
p Page
p Page Scan
p Inquiry
p Inquiry Scan
p Sniff
p Advertising
p Scanning
Document Number: 002-23132 Rev. ** Page 14 of 50
PRELIMINARY
CYBT-353027-02
Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth
clock, and device address.
Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked by software through power
management registers or packet-handling in the baseband core.
RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4-GHz transceiver, which then processes the power-down functions accordingly.
Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the
disabling of the on-chip regulator when in deep sleep (HIDOFF) mode.
BBC Power Management
There are several low-power operations for the BBC:
n Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
n Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBT-353027-02 runs on the
Low Power Oscillator and wakes up after a predefined time period.
The CYBT-353027-02 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
n Active mode
n Idle mode
n Sleep mode
n HIDOFF (Deep Sleep) mode
The CYBT-353027-02 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately
entered when user activity resumes.
In HIDOFF (Deep Sleep) mode, the CYBT-353027-02 baseband and core are powered off by disabling power to LDOOUT. The VDDO
domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power
consumption and is intended for long periods of inactivity.
Document Number: 002-23132 Rev. ** Page 15 of 50
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