Cypress Semiconductor 3026 User Manual

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

EZ-BT™ WICED Module

General Description

Notes

1. The values in this section were calculated for a 90% efficient DC-DC at 3V in HCI mode, and based on a Class I configurationbench-marked at Class II. Lower values
are expected for a class II configuration using an external LPO and corresponding PAconfiguration

The CYBT-X430XX-01 is a fully integrated Bluetooth Smart
Ready wireless module. The CYBT-X430XX-01 includes an
onboard crystal oscillator, passive components, flash memory,
and the Cypress CYW20706 silicon device. Refer to the

CYW20706 datasheet for additional details on the capabilities of

the silicon device used in this module.
The CYBT-X430XX-01 supports peripheral functions (ADC and

PWM), UART and USB communication, and a Bluetooth audio
interface. The CYBT-X430XX-01 includes a royalty-free BLE
stack compatible with Bluetooth 4.2 in a 12.0 × 15.5 × 1.95 mm
package.

The CYBT-343026-01 includes 512KB of onboard serial flash
memory and is designed for stand-alone opperation. The
CYBT-343029-01 has the same characterisitcs as the
CYBT-343026-01, but also include an on-board Apple
Authentication co-processor for use with Apple products such as
Homekit. The CYBT-143038-01 does not contain onboard flash,
requiring hosted control or application RAM upload operating
modes. The CYBT-143038-01 can also interface to external
flash on the host board. The CYBT-X430XX-01 utilizes an
integrated power amplifer to achieve Class I or Class II output
power capability.

The CYBT-X430XX-01 is fully qualified by Bluetooth SIG and is
targeted at applications requiring cost optimized BLE wireless
connectivity.

Module Description

n Module size: 12.00 mm × 15.50 mm × 1.95 mm

n Bluetooth LE 4.2 Smart Ready module

p QDID: WAP3026

p Declaration ID: 7922A-3026
n Certified to FCC, IC, MIC, and CE regulations

n Castelated solder pad connections for ease-of-use

n 512-KB on-module serial flash memory ( CYBT-34302X-01)

n Up to 10 GPIOs

n Temperature range: –30 °C to +85 °C

n Cortex-M3 32-bit processor

n Maximum TX output power:

p +12 dbm for Bluetooth EDR

p +9 dBm for Bluetooth Low Energy
n RX Receive Sensitivity:

p –93.5 dBm for Bluetooth Classic

p –96.5 dBm for Bluetooth Low Energy

Power Consumption

n TX average current consumption: 12.5 mA (EDR) Class-II

n RX average current consumption: 20.0 mA (EDR)

n Low power mode support

p Sleep: 120 uA

[1]

Functional Capabilities

n 10-bit auxiliary ADC with nine analog channels

n Serial Communications interface compatible with I2C slaves

n Serial Peripheral Interface (SPI) support for both master and

slave modes

n HCI interface through USB or UART

n PCM/I2S Auido interface

n 2-wire Global Coexistence Interface (GCI)

n Bluetooth wideband speech support

n Integrated peripherals such as PWM, ADC, Triac control

n Programmable output power control

n Maximum of 100 LE Connections

n Supports extended synchronous connections (eSCO), for

enhanced voice quality by allowing for retransmission of
dropped packets

Benefits

CYBT-X430XX-01 provides all necessary components required
to operate BLE and/or EDR/BR communication standards.

n Proven hardware design ready to use

n Dual-mode operatoin eliminates the need for multiple modules

n Cost optimized for applications without space constraints

n Non-volatile memory for self-sufficient operation and

Over-the-air updates ( CYBT-34302X-01 only)

n Bluetooth SIG Listed with QDID and Declaration ID

n Fully certified module eliminates the time needed for design,

development and certification processes

n WICED™ STUDIO 4.0 provides an easy-to-use integrated

design environment (IDE) to configure, develop, and program
a Bluetooth application

n Pre-programmed EZ-Serial firmware platform to allow for

easy-to-use out of the box Bluetooth connectivity

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-19525 Rev. ** Revised May 31, 2017

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.

References

n Overview: EZ-BLE/BT Module Portfolio, Module Roadmap
n EZ-BT WICED Product Overview
n CYW20706 BT Silicon Datasheet

n Knowledge Base Article

p KBA97095 - EZ-BLE™ Module Placement

p KBA213260 - RF Regulatory Certifications for

n Development Kits:

p CYBT-343026-EVAL, CYBT-343026-01 Evaluation Board

n Test and Debug Tools:

p CYSmart, Bluetooth
p CYSmart Mobile, Bluetooth

®

LE Test and Debug Tool (Windows)

®

LE Test and Debug Tool

(Android/iOS Mobile App)

CYBT-343026-01 and CYBT-143038-01 EZ-BT™ WICED
Modules

p KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

p KBA210802 - Queries on BLE Qualification and Declaration

Processes

Development Environments
Two Easy-To-Use Design Environments to Get You Started Quickly

Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)

Cypress's WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design.

WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated development
environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also
leverages many common industry standards.

EZ-Serial™ BT Firmware Platform

Cypress’s EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features
needed in Bluetooth applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status
and control signals through the module’s GPIOs, making it easy to add BLE and/or EDR/BR functionality quickly to existing designs.

Use a simple serial terminal and evaluation kit to begin development without requiring an IDE.
EZ-BT modules with non-volatile memory are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial

pre-loaded on your module, you can download each EZ-BT module’s firmware images on the EZ-Serial webpage.

Technical Support

n Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers

around the world.

n Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.

n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: [phone]. Select option 2 at the prompt.

Document Number: 002-19525 Rev. ** Page 2 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Contents

Overview............................................................................ 4

Functional Block Diagram ........................................... 4

Module Description...................................................... 4

Pad Connection Interface ................................................ 6

Recommended Host PCB Layout ................................... 7

Module Connections ........................................................ 9

Connections and Optional External Components....... 11

Power Connections (VDDIN)..................................... 11

External Reset (XRES).............................................. 11

Multiple-Bonded GPIO Connections ......................... 11

Using CYBT-143038-01 with External Flash............. 11

Critical Components List ........................................... 13

Antenna Design......................................................... 13

Bluetooth Baseband Core ............................................. 14

Link Control Layer ..................................................... 14

Test Mode Support.................................................... 15

Frequency Hopping Generator.................................. 15

Microprocessor Unit....................................................... 16

NVRAM Configuration Data and Storage.................. 16

One-Time Programmable Memory............................ 16

External Reset (XRES).............................................. 17

Integrated Radio Transceiver........................................ 18

Transmitter Path........................................................ 18

Digital Modulator ....................................................... 18

Digital Demodulator and Bit Synchronizer................. 18

Power Amplifier ......................................................... 18

Receiver Path............................................................ 18

Digital Demodulator and Bit Synchronizer................. 18

Receiver Signal Strength Indicator............................ 18

Local Oscillator Generation....................................... 18

Calibration ................................................................. 18

Internal LDO .............................................................. 19

Collaborative Coexistence............................................. 19

Global Coexistence Interface ........................................ 19

SECI I/O .................................................................... 19

Peripheral Transport Unit .............................................. 19

Cypress Serial Communications Interface ................ 19

UART Interface.......................................................... 20

Peripheral UART Interface ........................................ 21

PCM Interface.................................................................. 21

Slot Mapping ............................................................. 21

Frame Synchronization ............................................. 21

Data Formatting......................................................... 21

Burst PCM Mode....................................................... 21

Clock Frequencies.......................................................... 21

GPIO Port ........................................................................ 22

PWM................................................................................. 22

Triac Control/PWM ......................................................... 23

Serial Peripheral Interface ............................................. 23

Power Management Unit................................................ 23

RF Power Management ............................................ 23

Host Controller Power Management ......................... 24

BBC Power Management.......................................... 24

Electrical Characteristics............................................... 25

RF Specifications ........................................................... 27

Timing and AC Characteristics ..................................... 30

UART Timing............................................................. 30

SPI Timing................................................................. 31

BSC Interface Timing ................................................ 33

PCM Interface Timing................................................ 34

I2S Interface Timing .................................................. 38

Environmental Specifications ....................................... 39

Environmental Compliance ....................................... 39

RF Certification.......................................................... 39

Safety Certification .................................................... 39

Environmental Conditions ......................................... 39

ESD and EMI Protection ........................................... 39

Regulatory Information.................................................. 40

FCC........................................................................... 40

ISED.......................................................................... 41

European Declaration of Conformity ......................... 42

MIC Japan................................................................. 42

Packaging........................................................................ 43

Ordering Information...................................................... 45

Acronyms........................................................................ 46

Document Conventions ................................................. 47

Units of Measure ....................................................... 47

Document History Page................................................. 48

Sales, Solutions, and Legal Information...................... 49

Worldwide Sales and Design Support....................... 49

Products .................................................................... 49

PSoC® Solutions ...................................................... 49

Cypress Developer Community................................. 49

Technical Support ..................................................... 49

Document Number: 002-19525 Rev. ** Page 3 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Overview

Functional Block Diagram

Figure 1 illustrates the CYBT-343026-01 functional block diagram.

Figure 1. Functional Block Diagram

Module Description

The CYBT-X430XX-01 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections
will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the
physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna connection location dimensions

PCB thickness Height (H) 0.50 ± 0.05 mm
Shield height Height (H) 1.45 mm typical
Maximum component height Height (H) 1.45 mm typical
Total module thickness (bottom of module to highest component) Height (H) 1.95 mm typical

See Figure 2 for the mechanical reference drawing for CYBT-X430XX-01.

Length (X) 12.00 ± 0.15 mm

Width (Y) 15.50 ± 0.15 mm

Length (X) 12.0 mm

Width (Y) 4.62 mm

Document Number: 002-19525 Rev. ** Page 4 of 49

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CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (See

Notes

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

3. The CYBT-343026-01 includes castellated pad connections, denoted as the circular openings at the pad location above.

Document Number: 002-19525 Rev. ** Page 5 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Pad Connection Interface

As shown in the bottom view of Figure 2 on page 5, the CYBT-X430XX-01 connects to the host board via solder pads on the backside
of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-X430XX-01 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 24 Solder Pads 1.02 mm 0.71 mm 1.27 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must
contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace
antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please
refer to AN96841 for module placement best practices.

Figure 4. Recommended Host PCB Keep Out Area Around the CYBT-X430XX-01 Antenna

Document Number: 002-19525 Rev. ** Page 6 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure 7, and Ta ble 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBT-X430XX-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-X430XX-01 Host Layout (Dimensioned) Figure 6. CYBT-X430XX-01 Host Layout (Relative to Origin)

Document Number: 002-19525 Rev. ** Page 7 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Ta bl e 3 provides the center location for each solder pad on the CYBT-X430XX-01. All dimensions reference the to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure 6 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location

Solder Pad

(Center of Pad)

1 (0.38, 5.04) (14.96, 198.42)
2 (0.38, 6.26) (14.96, 246.46)
3 (0.38, 7.48) (14.96, 294.49)
4 (0.38, 8.70) (14.96, 342.52)
5 (0.38, 9.92) (14.96, 390.55)
6 (0.38, 11.14) (14.96, 438.58)
7 (0.38, 12.35) (14.96, 486.22)
8 (0.38, 13.57) (14.96, 534.25)

9 (1.73, 15.11) (68.11, 594.88)
10 (2.95, 15.11) (116.14, 594.88)
11 (4.17, 15.11) (164.17, 594.88)
12 (5.39, 15.11) (212.20, 594.88)
13 (6.61, 15.11) (260.24, 594.88)
14 (7.83, 15.11) (308.27, 594.88)
15 (9.05, 15.11) (356.30, 594.88)
16 (10.27, 15.11) (404.33, 594.88)
17 (11.62, 13.57) (457.48, 534.25)
18 (11.62, 12.35) (457.48, 486.22)
19 (11.62, 11.14) (457.48, 438.58)
20 (11.62, 9.92) (457.48, 390.55)
21 (11.62, 8.70) (457.48, 342.52)
22 (11.62, 7.48) (457.48, 294.49)
23 (11.62, 6.26) (457.48, 246.46)
24 (11.62, 5.04) (457.48, 198.42)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

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CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Module Connections

Ta bl e 4 and Table 5 detail the solder pad connection definitions and available functions for the pad connections for the

CYBT-34302X-01 and CYBT-143038-01 respectively. Ta b le 4 and Table 5 lists the solder pads on the CYBT-X430XX-01 modules,
the silicon device pin, and denotes what functions are available for each solder pad. The CYBT-343026-01 and CYBT-343029-01
share a common footprint.

Table 4. CYBT-343026-01 and CYBT-343029-01 Solder Pad Connection Definitions

Pad Pad Name UART SPI

1P0/P34

2 I2C_SCL SCL

3 XRES External Reset (Active Low)
4 I2C_SDA SDA

5 P2/P37/P28 PUART_RX/P2

6 SPI2_CS_N No Connect (Used for on-module memory SPI interface for CYBT-343026-01)
7 GND Ground
8 SPI2_MISO No Connect (Used for on-module memory SPI interface for CYBT-343026-01)
9 SPI2_MOSI No Connect (Used for on-module memory SPI interface for CYBT-343026-01)

10 SPI2_CLK No Connect (Used for on-module memory SPI interface for CYBT-343026-01)

11 G PIO_ 0

12 GPIO_1

13 GND Ground

14 GPIO_4

15 P4/P24

16 UART_TXD UART Transmit Data
17 UART_CTS UART Clear To Send Input
18 UART_RTS UART Request To Send Output

19 GPIO_7 PUART_RTS/P30 IN9/P30

20 UART_RXD UART Receive Data
21 VDDIN VDDIN (3.0V ~ 3.6V)

22 GPIO_3 UART_RX/P33

23 GPIO_6

24 GND Ground

1. The CYBT-343026-01 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface.

2. Quadrature Decoder

PUART_TX/P0

PUART_RX/P34

PUART_RX/P25
PUART_TX/P32

PUART_RTS/P6
PUART_TX/P31

PUART_RX/P4

PUART_TX/P24

SPI1_MOSI/P0

SPI1_CS(slave)/P2
SPI1_MOSI(master)/P2
SPI1_MISO(slave)/P37

SPI1_CLK/P36

SPI1_MOSI/P38

SPI1_MISO/P25

SPI1_MOSI/P6

SPI1_CLK/P24

SPI1_MOSI/P27

SPI1_MOSI/P33

1

(master/slave)

(master/slave)

(master/slave)
SPI1_CS/P32

(slave)

SPI1_CS/P6

(slave)

(master/slave)

(master/slave)

(master/slave)

(slave)

SPI1_CS/P26

(slave)

I2C ADC QD

IN29/P0
IN5/P34

SCL/P37

IN11/P28

IN2/P37

IN3/P36
IN1/P38

IN7/P32 DX0/P32 ACLK0/P323(HostWak

IN8/P31 DZ0/P6

IN6/P33

IN24/P11 OC0/P26

2

CLK/XTAL GPIO

DY0/P34

DX0/P2
OC2/P28
DZ1/P37

DZ0/P36 ACLK0/P363(DevWake

DY0/P4

OC1/P27
DX1/P33

ACK1/P37 3

ACLK1/P33 3

3 PCM_Sync

)

e)

3

(GCI)

3

(CLK_RE

Q)

3

(GCI)

3

(GCI)

Other

I2S_WS

~TX_PD/P36

Ext LPO In

PWM2/P27

PWM1/P26

Document Number: 002-19525 Rev. ** Page 9 of 49

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CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Table 5. CYBT-143038-01 Solder Pad

Pad Pad Name UART SPI

1P0/P34

2 I2C_SCL SCL

3XRES External reset
4 I2C_SDA SDA

5 P2/P37/P28 PUART_RX/P2

6 SPI2_CS_N

7 GND Ground

8 SPI2_MISO

9 SPI2_MOSI

10 SPI2_CLK

11 G PIO_ 0

12 GPIO_1

13 GND Ground

14 GPIO_4

15 P4/P24

16 UART_TXD UART transmit data
17 UART_CTS UART clear to send input
18 UART_RTS UART request to send output

19 GPIO_7 PUART_RTS/P30 IN9/P30

20 UART_RXD UART receive data
21 VDDIN VDDIN (3.0V ~ 3.6V)

22 GPIO_3 UART_RX/P33

23 GPIO_6

24 GND Ground

1. The CYBT-143038-01 contains two SPI peripherals, SPI1 and SPI2. SPI1 supports only master or slave modes, whereas SPI2 supports master only mode. The con­nections shown in Table 5 above detail the SPI function for the given mode shown in parenthesis. If external memory is used with the CYBT-143038-01, then SPI2
should be used as the interface.

2. Quadrature Decoder

PUART_TX/P0

PUART_RX/P34

PUART_RX/P25
PUART_TX/P32

PUART_RTS/P6
PUART_TX/P31

PUART_RX/P4

PUART_TX/P24

SPI1_MOSI/P0

SPI1_CS(slave)/P2

SPI1_MOSI(master)/

SPI1_MISO(slave)/P3

SPI2 active-low chip

SPI1_CLK/P36

SPI1_MOSI/P38

SPI1_MISO/P25

SPI1_MOSI/P6

SPI1_CLK/P24

SPI1_MOSI/P27

SPI1_MOSI/P33

1

(master/slave)

P2

7

select

SPI2_MISO

(master)

SPI2_MOSI

(master)

SPI2_CLK

(master)

(master/slave)

(master/slave)
SPI1_CS/P32

(slave)

SPI1_CS/P6

(slave)

(master/slave)

(master/slave)

(master/slave)

(slave)

SPI1_CS/P26

(slave)

I2C ADC QD

IN29/P0
IN5/P34

SCL/P37

SCL

SDA

IN11/P28

IN2/P37

IN3/P36
IN1/P38

IN7/P32 DX0/P32 ACLK0/P32

IN8/P31 DZ0/P6

IN6/P33

IN24/P11 OC0/P26

2

CLK/XTAL GPIO

DY0/P34

DX0/P2
OC2/P28
DZ1/P37

DZ0/P36 ACLK0/P36

DY0/P4 3

OC1/P27
DX1/P33

ACK1/P37 3

(DevWake)

(Host Wake)

(GCI)

(CLK_REQ)

(GCI)

ACLK1/P33 3

(GCI)

Other

3 PCM_Sync

3

3

3

3

3

I2S_WS

~TX_PD/P36

Ext LPO In

PWM2/P27

PWM1/P26

Document Number: 002-19525 Rev. ** Page 10 of 49

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CYBT-343029-01
CYBT-143038-01

Connections and Optional External Components

Power Connections (VDDIN)

The CYBT-X430XX-01 contains one power supply connection, VDDIN. VDDIN accepts a supply input range of 2.3 V to 3.6 V for
CYBT-34302X-01 and 1.62 V to 3.6 V for the CYBT-143038-01. Ta ble 1 2 provides this specification. The maximum power supply
ripple for this power connection is 100 mV, as shown in Table 1 2.

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead
between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned
as close as possible to the module pin connection and the recommended ferrite bead value is 330Ω, 100 MHz.

External Reset (XRES)

The CYBT-X430XX-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This
action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,
which is an input to the CYBT-X430XX-01 module (solder pad 3). The CYBT-X430XX-01 module
resistor on the XRES input

During power on operation, the XRES connection to the CYBT-X430XX-01 is required to be held low 50 ms after the VDD power
supply input to the module is stable. This can be accomplished in the following ways:

n The host device should connect a GPIO to the XRES of Cypress CYBT-X430XX-01 module and pull XRES low until VDD is stable.

XRES is recommended to be released 50 ms after VDDIN is stable.

n The XRES release timing may be controlled by a external voltage detection circuit. XRES should be released 50 ms after VDD is

stable.

Refer to Figure 10 on page 17 for XRES operating and timing requirements during power on events.

Multiple-Bonded GPIO Connections

The CYBT-X430XX-01 contains GPIO which are multiple-bonded at the silicon level. If any of these dual-bonded GPIO are used, only
the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio
SDK. For details on the features and functions that each of these multiple-bonded GPIO provide, please refer to Table 4 and Table 5.

does not require an external pull-up

Using CYBT-143038-01 with External Flash

The CYBT-143038-01 does not contain any on-module non-volatile memory. If desired, the CYBT-143038-01 can be used with an
external memory device (SFLASH).

If EEPROM is used as an external memory device with I2C interface, module solder pads 4 (SDA) and 2 (SCL) must be used as the
I2C interface.

If using external SFLASH as the memory interface, SPI2 (master) must be used as the interface to the SFLASH device. The specific
GPIO required and the applicable SPI signal is shown below. These are the same signals used for SFLASH interface on the
CYBT-343026-01.

1. SPI signal MOSI: Module Solder Pad 9, silicon connection SPI2_MOSI_I2C_SDA

2. SPI signal MISO: Module Solder Pad 8, silicon connection SPI2_MISO_I2C_SCL

3. SPI Signal CLK: Module Solder Pad 10 silicon connection SPI2_CLK

4. SPI Signal CS: Module Solder Pad 6, silicon connection SPI2_CSN

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CYBT-343029-01
CYBT-143038-01

Figure 8 illustrates the CYBT-343026-01 schematic.

Figure 8. CYBT-343026-01 Schematic Diagram

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CYBT-343029-01
CYBT-143038-01

Critical Components List

Ta bl e 6 details the critical components used in the CYBT-X430XX-01 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 49-pin FBGA BT/BLE Silicon Device - CYW20706
Silicon U2 8-pin TDF8N, 512KSerial Flash ( CYBT-34302X-01)
Crystal Y1 24.000 MHz, 12PF

Antenna Design

Ta bl e 7 details trace antenna used in the CYBT-X430XX-01 module. For more information, see Tab le 7 .

Table 7. Trace Antenna Specifications

Item Description

Frequency Range 2400 – 2500 MHz
Peak Gain –0.5 dBi typical
Return Loss 10 dB minimum

Document Number: 002-19525 Rev. ** Page 13 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and
packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition
to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions
are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:

n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),

data decryption, and data dewhitening in the receiver.

n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the

transmitter.

Bluetooth 4.2 Features

CYBT-X430XX-01 supports all Bluetooth 4.2 and legacy features, with the following benefits

n Dual-mode Bluetooth (BT and BLE operation)

n Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode.

n Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment.

n Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life.

n Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required.

n Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link

timeout supervision.

n Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human

interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary
flag (PBF) enhancements.

n Secure connections (BR/EDR)

n Fast advertising interval

n Piconet clock adjust

n Connectionless broadcast

n LE privacy v1.1

n Low duty cycle directed advertising

n LE dual mode topology

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth
Link Controller.

n States:

p Standby
p Connection
p Page
p Page Scan
p Inquiry
p Inquiry Scan
p Sniff
p Advertising
p Scanning

Document Number: 002-19525 Rev. ** Page 14 of 49

PRELIMINARY

CYBT-343026-01
CYBT-343029-01
CYBT-143038-01

Test Mode Support

The CYBT-X430XX-01 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version

3.0.
This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYBT-X430XX-01also supports enhanced testing features to simplify RF

debugging and qualification and type-approval testing. These features include:

n Fixed frequency carrier wave (unmodulated) transmission

p Simplifies some type-approval measurements (Japan)
p Aids in transmitter performance analysis

n Fixed frequency constant receiver mode

p Receiver output directed to I/O pin
p Allows for direct BER measurements using standard RF test equipment
p Facilitates spurious emissions testing for receive mode

n Fixed frequency constant transmission

p 8-bit fixed pattern or PRBS-9
p Enables modulated signal measurements with standard RF test equipment.

Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth
clock, and device address.

Document Number: 002-19525 Rev. ** Page 15 of 49