Cypress Semiconductor 3025 User Manual

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

EZ-BLE™ WICED Module

General Description

Notes

1. CYBLE-0130XX-00 global connections (Power, Ground, XRES, etc) are pad compatible with the CYBLE-x120xx-00 family of modules. Available GPIO and functions may not be 100% compatible with your design. A review of the pad location and function within your design should be complete to determine if the CYBLE-0130XX-00 is completely pad-compatible to the CYBLE-x120xx-00 modules.

The CYBLE-0130XX-00 is a fully integrated Bluetooth Low Energy (BLE) wireless module solution. The CYBLE-0130XX-00 includes onboard crystal oscillator, passive components, flash memory, and the Cypress CYW20737 silicon device. Refer to the CYW20737 datasheet for additional details on the capabilities of the silicon device used in this module.

The CYBLE-0130XX-00 supports a number of peripheral functions (ADC and PWM), as well as UART serial communication. The CYBLE-0130XX-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 in a 14.5 × 19.2 ×

2.25mm package. The CYBLE-013025-00 includes 128KB of onboard flash

memory and is designed to allow for self-sufficient opperation. The CYBLE-013030-00 does not contain onboard flash, providing maximum cost optimization and allowing for hosted control or application RAM upload, or interface to external flash on the host board.

The CYBLE-0130XX-00 is fully certified by Bluetooth SIG is targeted at applications requiring cost optimized BLE wireless connectivity. The CYBLE-0130XX-00 is footprint compatible with the CYBLE-x120xx-00 module family.

Module Description

n Module size: 14.52 mm × 19.20 mm × 2.25 mm

n Bluetooth LE 4.1 single-mode module

p QDID: TBD p Declaration ID: TBD

n Certified to FCC, IC, MIC, and CE regulations

n Castelated solder pad connections for ease-of-use

n 128-KB flash memory, 60-KB SRAM memory

n Up to 14 GPIOs configurable as open drain high/low,

pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output

n Industrial temperature range: –30 °C to +85 °C

n Cortex-M3 32-bit processor

n Watchdog timer with dedicated internal low-speed oscillator

n Supports A4WP wireless charging

n Supports fRSA encryption/decryption and key exchange

mechanisms (up to 4 kbit)

n Supports NFC tag-based “tap-to-pair”

n Supports IR learning with built-in IR modulator

Power Consumption

n Maximum TX output power: +4.0 dbm

n RX Receive Sensitivity: –94 dbm

n Received signal strength indicator (RSSI) with 1-dB resolution

n TX current consumption: 9.1 mA

n RX current consumption: 9.8 mA

n Cypress CYW20737 silicon low power mode support

p Sleep: 12 uA typical p Deep Sleep: TBD

Functional Capabilities

n 10-bit auxiliary ADC with nine analog channels

n Serial Communications interface (compatible with Philips

slaves)

n Four dedicated PWM blocks

n BLE protocol stack supporting generic access profile (GAP)

[1]

Central, Peripheral, Observer, or Broadcaster roles

n Programmable output power control

Benefits

CYBLE-0130XX-00 provides all necessary components required to operate BLE communication standards.

n Proven hardware design ready to use

n Cost optimized for applications without space constraints

n Non-volatile memory for complex application development

n Over-the-air update capable for in-field updates

n Bluetooth SIG qualified with QDID and Declaration ID

n Fully certified module eliminates the time needed for design,

development and certification processes

n WICED™ SMART provides an easy-to-use integrated design

environment (IDE) to configure, develop, and program a BLE application

I2C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-xxxxx Rev. ** Revised April 10, 2017

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Contents

Overview............................................................................ 3

Functional Block Diagram ........................................... 3

Module Description...................................................... 3

Pad Connection Interface ................................................ 5

Recommended Host PCB Layout ................................... 6

Module Connections ........................................................ 8

Connections and Optional External Components ..... 10

Power Connections (VDD) ........................................ 10

External Reset (XRES).............................................. 10

External Component Recommendation .................... 10

Critical Components List ........................................... 12

Antenna Design......................................................... 12

Bluetooth Baseband Core ............................................. 13

Infrared Modulator.......................................................... 14

Infrared Learning ............................................................ 15

Wireless Charging .......................................................... 16

Security ........................................................................... 16

Support for NFC Tag Based Pairing ............................. 16

Bluetooth Smart Audio .................................................. 16

ADC Port.......................................................................... 17

Serial Peripheral Interface ............................................. 18

Microprocessor Unit....................................................... 18

Internal Reset ............................................................ 19

External Reset (XRES).............................................. 19

Integrated Radio Transceiver........................................ 20

Transmitter Path........................................................ 20

Digital Modulator ....................................................... 20

Power Amplifier ......................................................... 20

Receiver Path............................................................ 20

Digital Demodulator and Bit Synchronizer................. 20

Receiver Signal Strength Indicator............................ 20

Local Oscillator.......................................................... 20

Calibration ................................................................. 20

Internal LDO Regulator ............................................. 20

Peripheral Transport Unit .............................................. 21

Broadcom Serial Communications Interface............. 21

Peripheral Block ........................................................ 21

GPIO Port ........................................................................ 22

PWM................................................................................. 23

Power Management Unit................................................ 24

RF Power Management ............................................ 24

Host Controller Power Management ......................... 24

BBC Power Management.......................................... 24

Electrical Characteristics.....................................

RF Specifications ........................................................... 28

Timing and AC Characteristics ..................................... 30

UART Timing............................................................. 30

SPI Timing................................................................. 30

BSC Interface Timing ................................................ 31

Environmental Specifications ....................................... 33

Environmental Compliance ....................................... 33

RF Certification.......................................................... 33

Safety Certification .................................................... 33

Environmental Conditions ......................................... 33

ESD and EMI Protection ........................................... 33

Regulatory Information.................................................. 34

FCC........................................................................... 34

Industry Canada (IC) Certification............................. 35

European R&TTE Declaration of Conformity ............ 35

MIC Japan................................................................. 36

Packaging........................................................................ 37

Ordering Information...................................................... 39

Acronyms........................................................................ 40

Document Conventions ................................................. 40

Units of Measure ....................................................... 40

Document History Page................................................. 41

Sales, Solutions, and Legal Information...................... 42

Worldwide Sales and Design Support....................... 42

Products .................................................................... 42

PSoC® Solutions ...................................................... 42

Cypress Developer Community................................. 42

Technical Support ..................................................... 42

.......... 25

Document Number: 002-xxxxx Rev. ** Page 2 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Overview

Functional Block Diagram

Figure 1 illustrates the CYBLE-0130XX-00 functional block diagram.

Figure 1. Functional Block Diagram

Module Description

The CYBLE-0130XX-00 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna connection location dimensions

PCB thickness Height (H) 0.80 ± 0.10 mm Shield height Height (H) 1.45 mm typical Maximum component height Height (H) 1.45 mm typical Total module thickness (bottom of module to highest component) Height (H) 2.25 mm typical

See Figure 2 for the mechanical reference drawing for CYBLE-0130XX-00.

Length (X) 14.52 ± 0.10 mm

Width (Y) 19.50 ± 0.10 mm

Length (X) 14.52 mm

Width (Y) 4.80 mm

Document Number: 002-xxxxx Rev. ** Page 3 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Figure 2. Module Mechanical Drawing

Bottom View (Seen from Bottom)

Side View

Top View (See from Top)

Notes

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 6.

3. The CYBLE-0130XX-00 includes castellated pad connections, denoted as the circular openings at the pad location above.

Document Number: 002-xxxxx Rev. ** Page 4 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Pad Connection Interface

As shown in the bottom view of Figure 2 on page 4, the CYBLE-0130XX-00 connects to the host board via solder pads on the backside of the module. Tab l e 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBLE-0130XX-00 module.

Table 2. Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 31 Solder Pads 1.02 mm 0.71 mm 1.27 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module placement best practices.

2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).

Figure 4. Recommended Host PCB Keep Out Area Around the CYBLE-0130XX-00 Antenna

Document Number: 002-xxxxx Rev. ** Page 5 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Recommended Host PCB Layout

Top View (Seen on Host PCB)

Figure 5, Figure 6, Figure 7, and Ta b le 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBLE-0130XX-00. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBLE-0130XX-00 Host Layout (Dimensioned) Figure 6. CYBLE-0130XX-00 Host Layout (Relative to Origin)

Document Number: 002-xxxxx Rev. ** Page 6 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Ta bl e 3 provides the center location for each solder pad on the CYBLE-0130XX-00. All dimensions reference the to the center of the

Top View (Seen on Host PCB)

solder pad. Refer to Figure 6 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location

Solder Pad

(Center of Pad)

1 (0.39, 4.88) (15.35, 192.13) 2 (0.39, 6.15) (15.35, 242.13) 3 (0.39, 7.42) (15.35, 292.13) 4 (0.39, 8.69) (15.35, 342.13) 5 (0.39, 9.96) (15.35, 392.13) 6 (0.39, 11.23) (15.35, 442.13) 7 (0.39, 12.50) (15.35, 492.13) 8 (0.39, 13.77) (15.35, 542.13)

9 (0.39, 15.04) (15.35, 592.13) 10 (0.39, 16.31) (15.35, 642.13) 11 (0.39, 17.58) (15.35, 692.13) 12 (2.04, 18.82) (80.31, 740.94) 13 (3.31, 18.82) (130.31, 740.94) 14 (4.58, 18.82) (180.31, 740.94) 15 (5.85, 18.82) (230.31, 740.94) 16 (7.12, 18.82) (280.31, 740.94) 17 (8.39, 18.82) (330.31, 740.94) 18 (9.66, 18.82) (380.31, 740.94) 19 (10.93, 18.82) (430.31, 740.94) 20 (12.20, 18.82) (480.31, 740.94) 21 (13.47, 18.82) (530.31, 740.94) 22 (14.14, 16.31) (556.69, 642.12) 23 (14.14, 15.04) (556.69, 592.12) 24 (14.14, 13.77) (556.69, 542.12) 25 (14.14, 12.50) (556.69, 492.12) 26 (14.14, 11.23) (556.69, 442.12) 27 (14.14, 9.96) (556.69, 392.12) 28 (14.14, 8.69) (556.69, 342.12) 29 (14.14, 7.42) (556.69, 292.12) 30 (14.14, 6.15) (556.69, 242.12) 31 (14.14, 4.88) (556.69, 192.12)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

Document Number: 002-xxxxx Rev. ** Page 7 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Module Connections

Ta bl e 4 and Table 5 detail the solder pad connection definitions and available functions for the pad connections for the

CYBLE-013025-00 and CYBLE-013030-00 respectively. Tab le 4 an d Ta bl e 5 lists the solder pads on the CYBLE-0130XX-00 modules, the silicon device pin, and denotes what functions are available for each solder pad.

Table 4. CYBLE-013025-00 Solder Pad Connection Definitions

Pad Num-

ber

1 XRES Power Supply Input (3.30V) 2 GND/NC Ground Can be NC 3 GND/NC Ground Can be NC 4 P11/27 SPI2_MOSI(master/slave) 33ADC input, QOC, XTALI32K 5 P12/26 SPI2_CS(slave) 33ADC input, QOC, XTALO32K 6P15 3 ADC input, SWDIO, IR_RX 7 P14/38 SPI2_MOSI(master/slave) 33ADC Input, IR_TX 8P13/28 33ADC input, QOC, IR_TX

9P24

10 NC Not Connect 11 NC Not Connect

12 P25

13 P4

14 P2

15 VDD VDD

16 P3

17 P8/33 3 ADC input, TX_PD, QDX1,ACLK1 18 P32 3 ADC input, ACLK0 19 P1 PUART_RTS,SPI2_MISO 3 ADC input, IR_TX

20 P0

21 SDA I2C_SDA 3 22 SCL I2C_SCL 3 23 UP_TX 3(UART_TXD) 3 24 UP_RX 3(UART_RXD) 3 25 GND Ground 26 GND Ground 27 GND Ground 28 GND Ground 29 NC Not Connect 30 NC Not Connect 31 NC Not Connect

Pad Name UART/SPI/I2C PWM GPIO Other Function

PUART_RX,SPI2_CLK(master/

PUART_RX,SPI2_MISO(maste

PUART_RX,SPI2_MOSI(maste

PUART_CTS,SPI2_CLK(maste

PUART_TX,SPI2_MOSI(master

slave))

r/slave)

r)/SPI2_CS(slave)

r/slave)

/slave)

3 IR_TX, Q_Y0

3 QDX0

3 QDX1

3 ADC input, IR_RX

Document Number: 002-xxxxx Rev. ** Page 8 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Table 5. CYBLE-013030-00 Solder Pad Connection Definitions

Pad Num-

ber

9P24

10 NC Not Connect 11 NC Not Connect

12 P25

13 P4

14 P2

15 VDD VDD

16 P3

17 P8/33 PUART_RX,SPI1_MOSI 3 ADC input, TX_PD, QDX1,ACLK1 18 P32 PUART_TX,SPI1_MISO/CS 3 ADC input, ACLK0 19 P1 PUART_RTS,SPI2_MISO 3 ADC input, IR_TX

20 P0

21 SDA I2C_SDA 3 22 SCL I2C_SCL 3 23 UP_TX 3(UART_TXD) 3 24 UP_RX 3(UART_RXD) 3 25 GND Ground 26 GND Ground 27 GND Ground 28 GND Ground 29 NC Not Connect 30 NC Not Connect 31 NC Not Connect

Pad Name UART/SPI/I2C PWM GPIO Other Function

PUART_RX,SPI2_CLK(master/

PUART_RX,SPI2_MISO(maste

PUART_RX,SPI2_MOSI(maste

PUART_CTS,SPI2_CLK(maste

PUART_TX,SPI2_MOSI(master

slave))

r/slave)

r)/SPI2_CS(slave)

r/slave)

/slave)

3 IR_TX, Q_Y0

3 QDX0

3 QDX1

3 ADC input, IR_RX

Document Number: 002-xxxxx Rev. ** Page 9 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Connections and Optional External Components

Power Connections (VDD)

The CYBLE-0130XX-00 contains one power supply connection, VDD. VDD accepts a supply input range of 2.3V to 3.6 V. Table 14 provides this specification. The maximum power supply ripple for this

power connection is 100 mV, as shown in Table 14.

External Reset (XRES)

The CYBLE-0130XX-00 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBLE-0130XX-00 module.

External Component Recommendation

Power Supply Circuitry

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection.

If used, the recommended ferrite bead value is 330Ω, 100 MHz. (Murata BLM21PG331SN1D).

Document Number: 002-xxxxx Rev. ** Page 10 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Figure 8 illustrates the CYBLE-0130XX-00 schematic.

Figure 8. CYBLE-0130XX-00 Schematic Diagram

Document Number: 002-xxxxx Rev. ** Page 11 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Critical Components List

Ta bl e 6 details the critical components used in the CYBLE-0130XX-00 module.

Table 6. Critical Component List

Component Reference Designator Description

Silicon U1 32-pin QFN BLE Silicon Device - CYW20737r Silicon U2 8-pin TDF8N, 128KSerial Flash Crystal Y1 24.000 MHz, 12PF

Antenna Design

Ta bl e 7 details trace antenna used in the CYBLE-0130XX-00 module. For more information, see Ta bl e 7 .

Table 7. Trace Antenna Specifications

Item Description

Frequency Range 2400 – 2500 MHz Peak Gain 0.5 dBi typical Return Loss 10 dB minimum

Document Number: 002-xxxxx Rev. ** Page 12 of 42

PRELIMINARY

CYBLE-013025-00 CYBLE-013030-00

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation. The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security before sending over the air:

n Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening.

n Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and data

whitening.

Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state, Bluetooth clock, and device address.

E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal processor intervention.

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit (LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state. STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, and inquiry scan.

Adaptive Frequency Hopping

The CYBLE-0130XX-00 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop map.

Document Number: 002-xxxxx Rev. ** Page 13 of 42

+ 29 hidden pages

Cypress Semiconductor 3025 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Module Description

Power Consumption

Functional Capabilities

Benefits

Overview

Functional Block Diagram

Module Description

Module Dimensions and Drawing

Pad Connection Interface

Recommended Host PCB Layout

Module Connections

Connections and Optional External Components

Power Connections (VDD)

External Reset (XRES)

External Component Recommendation

Power Supply Circuitry

Critical Components List

Antenna Design

Bluetooth Baseband Core