Cypress Semiconductor 2005 User Manual

PRELIMINARY

CYBLE-222014-01

EZ-BLE™ PRoC™ Bluetooth 4.2 Module

General Description

The Cypress CYBLE-222014-01 is a fully certified and qualified module supporting Bluetooth communication. The CYBLE-222014-01 is a turnkey solution and includes onboard crystal oscillators, chip antenna, passive components, and Cypress PRoC™ BLE. Refer to the CYBL10X7X datasheet for additional details on the capabilities of the PRoC BLE device used on this module.

The CYBLE-222014-01 supports a number of peripheral functions (ADC, timers, counters, PWM) and serial communication protocols (I programmable architecture. The CYBLE-222014-01 includes a royalty-free BLE stack compatible with Bluetooth 4.2 and provides up to 16 GPIOs in a small 10 × 10 × 1.80 mm package.

The CYBLE-222014-01 is drop-in compatible with the CYBLE-022001-00 (128KB BT 4.1) and CYBLE-222005-00 (256KB BT 4.1).

Module Description

■ Module size: 10.0 mm ×10.0 mm × 1.80 mm (with shield)

■ 256-KB flash memory, 32-KB SRAM memory

■ Up to 16 GPIOs configurable as open drain high/low,

pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output

■ Bluetooth 4.2 qualified single-mode module

■ Certified to FCC, CE MIC, KC, and IC regulations

■ Eight-channel direct memory access (DMA) controller

■ 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit

multiply, operating at up to 48 MHz

■ Industrial temperature range: –40 °C to +85 °C

■ Watchdog timer with dedicated internal low-speed oscillator

(ILO)

■ Two-pin SWD for programming

Power Consumption

■ TX output power: –18 dbm to +3 dbm

■ Received signal strength indicator (RSSI) with 1-dB resolution

■ TX current consumption of 15.6 mA (radio only, 0 dbm)

■ RX current consumption of 16.4 mA (radio only)

■ Low power mode support ❐ Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on

❐ Hibernate: 150 nA with SRAM retention ❐ Stop: 60 nA with XRES wakeup



Low Energy (BLE) 4.2 wireless

C, UART, SPI) through its

Functional Capabilities

■ Up to 15 capacitive sensors for buttons or sliders with

best-in-class signal-to-noise ration (SNR) and liquid tolerance

■ 12-bit, 1-Msps SAR ADC with internal reference,

sample-and-hold (S/H), and channel sequencer

■ Two serial communication blocks (SCBs) supporting I

(master/slave), SPI (master/slave), or UART

■ Four dedicated 16-bit timer, counter, or PWM blocks

(TCPWMs)

■ Programmable low voltage detect (LVD) from 1.8 V to 4.5 V

■ I

S master interface

■ Bluetooth Low Energy protocol stack supporting generic

access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles

■ Switches between Central and Peripheral roles on-the-go

■ Standard Bluetooth Low Energy profiles and services for

interoperability

■ Custom profile and service for specific use cases

Benefits

The CYBLE-222014-01 module is provided as a turnkey solution, including all necessary hardware required to use BLE communication standards.

■ Proven, qualified, and certified hardware design ready to use

■ Small footprint (10 × 10 mm × 1.80 mm), perfect for space

constrained applications

■ Reprogrammable architecture

■ Fully certified module eliminates the time needed for design,

development and certification processes

■ Bluetooth SIG qualified with QDID and Declaration ID

■ Flexible communication protocol support

■ PSoC Creator™ provides an easy-to-use integrated design

environment (IDE) to configure, develop, program, and test a BLE application

Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-11186 Rev. **

Revised February 18, 2016

PRELIMINARY

CYBLE-222014-01

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.

■ Overview: EZ-BLE Module Portfolio, Module Roadmap

■ EZ-BLE PRoC Product Overview

■ PRoC BLE Silicon Datasheet

■ Application notes: Cypress offers a number of BLE application

notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are:

❐ AN96841 - Getting Started with EZ-BLE Module ❐ AN94020 - Getting Started with PRoC BLE ❐ AN97060 - PSoC

4 BLE and PRoC™ BLE - Over-The-Air

(OTA) Device Firmware Upgrade (DFU) Guide

❐ AN91162 - Creating a BLE Custom Profile ❐ AN91184 - PSoC 4 BLE - Designing BLE Applications ❐ AN92584 - Designing for Low Power and Estimating Battery

Life for BLE Applications

❐ AN85951 - PSoC ❐ AN95089 - PSoC

4 CapSense® Design Guide

4/PRoC™ BLE Crystal Oscillator Selec-

■ Knowledge Base Articles ❐ KBA97095 - EZ-BLE™ Module Placement

■ Technical Reference Manual (TRM): ❐ PRoC

■ Development Kits: ❐ CY8CKIT-042-BLE, Bluetooth

❐ CY8CKIT-002, PSoC

■ Test and Debug Tools: ❐ CYSmart, Bluetooth

❐ CYSmart Mobile, Bluetooth

BLE Technical Reference Manual

Kit

MiniProg3 Program and Debug Kit

LE Test and Debug Tool (Windows)

Low Energy (BLE) Pioneer

LE Test and Debug Tool

(Android/iOS Mobile App)

tion and Tuning Techniques

❐ AN91445 - Antenna Design and RF Layout Guidelines

PSoC® Creator™ Integrated Design Environment (IDE)

PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and

debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC Components™.

PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements.

Blutooth Low Energy Component

The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack.

Technical Support

■ Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.

■ Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-11186 Rev. ** Page 2 of 37

PRELIMINARY

CYBLE-222014-01

Overview ............................................................................4

Module Description ...................................................... 4

Pad Connection Interface ................................................ 6

Recommended Host PCB Layout ................................... 7

Power Supply Connections

and Recommended External Components .................. 10

Connection Options ...................................................10

External Component Recommendation .................... 10

Critical Components List ...........................................12

Antenna Design ......................................................... 12

Electrical Specification .................................................. 13

GPIO .........................................................................15

XRES .........................................................................16

Digital Peripherals ..................................................... 19

Serial Communication ...............................................21

Memory .....................................................................22

System Resources ....................................................22

Environmental Specifications .......................................28

Environmental Compliance ....................................... 28

RF Certification .......................................................... 28

Environmental Conditions ......................................... 28

ESD and EMI Protection ...........................................28

Regulatory Information .................................................. 29

FCC ...........................................................................29

Industry Canada (IC) Certification .............................30

European R&TTE Declaration of Conformity ............ 30

MIC Japan ................................................................. 31

KC Korea ................................................................... 31

Packaging ........................................................................32

Ordering Information ...................................................... 34

Part Numbering Convention ......................................34

Acronyms ........................................................................35

Document Conventions ................................................. 35

Units of Measure ....................................................... 35

Document History Page ................................................. 36

Sales, Solutions, and Legal Information ...................... 37

Worldwide Sales and Design Support ....................... 37

Products ....................................................................37

PSoC® Solutions ......................................................37

Cypress Developer Community .................................37

Technical Support .....................................................37

Document Number: 002-11186 Rev. ** Page 3 of 37

PRELIMINARY

CYBLE-222014-01

Overview

Module Description

The CYBLE-222014-01 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item Specification

Module dimensions

Antenna location dimensions

PCB thickness Height (H) 0.50 ± 0.10 mm Shield height Height (H) 1.10 ± 0.10 mm Maximum component height Height (H) 1.30 mm typical (chip antenna) Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical

See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-222014-01.

Length (X) 10.00 ± 0.15 mm

Width (Y) 10.00 ± 0.15 mm

Length (X) 7.00 ± 0.15 mm

Width (Y) 5.00 ± 0.15 mm

Document Number: 002-11186 Rev. ** Page 4 of 37

PRELIMINARY

CYBLE-222014-01

Figure 1. Module Mechanical Drawing

Top View (View from Top)

Bottom View (Seen from Bottom)

Side View

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

Document Number: 002-11186 Rev. ** Page 5 of 37

PRELIMINARY

CYBLE-222014-01

Pad Connection Interface

Host PCB Keep Out Area Around Chip Antenna

As shown in the bottom view of Figure 1 on page 5, the CYBLE-222014-01 connects to the host board via solder pads on the back of the module. Ta bl e 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-222014-01 module.

Table 2. Solder Pad Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 22 Solder Pads 0.71 mm 0.41 mm 0.76 mm

Figure 2. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module placement best practices.

2. To maximize RF performance, the area immediately around the Cypress BLE module chip antenna should contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).

Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-222014-01 Chip Antenna

Document Number: 002-11186 Rev. ** Page 6 of 37

PRELIMINARY

CYBLE-222014-01

Recommended Host PCB Layout

Top View (On Host PCB)

Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBLE-222014-01. Dimensions are in millimeters unless otherwise noted. Pad length of 0.91 mm (0.455 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 4. Host Layout Pattern for CYBLE-222014-01 Figure 5. Module Pad Location from Origin

Document Number: 002-11186 Rev. ** Page 7 of 37

PRELIMINARY

CYBLE-222014-01

Ta bl e 3 provides the center location for each solder pad on the CYBLE-222014-01. All dimensions reference the to the center of the

solder pad. Refer to Figure 6 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location

Solder Pad

(Center of Pad)

1 (0.26, 1.64) (10.24, 64.57) 2 (0.26, 2.41) (10.24, 94.88) 3 (0.26, 3.17) (10.24, 124.80) 4 (0.26, 3.93) (10.24, 154.72) 5 (0.26, 4.69) (10.24, 184.65) 6 (0.81, 9.74) (31.89, 383.46) 7 (1.57, 9.74) (61.81, 383.46) 8 (2.34, 9.74) (92.13, 383.46)

9 (3.10, 9.74) (122.05, 383.46) 10 (3.86, 9.74) (151.97, 383.46) 11 (4.62, 9.74) (181.89, 383.46) 12 (5.38, 9.74) (211.81, 383.46) 13 (6.15, 9.74) (242.13, 383.46) 14 (6.91, 9.74) (272.05, 383.46) 15 (7.67, 9.74) (301.97, 383.46) 16 (8.43, 9.74) (331.89, 383.46) 17 (9.19, 9.74) (361.81, 383.46) 18 (9.75, 8.50) (383.86, 334.65) 19 (9.75, 7.74) (383.86, 304.72) 20 (9.75, 6.98) (383.86, 274.80) 21 (9.75, 6.22) (383.86, 244.88)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

Document Number: 002-11186 Rev. ** Page 8 of 37

PRELIMINARY

CYBLE-222014-01

Ta bl e 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on

Notes

2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.

3. The main board needs to connect both GND connections (Pad 1 and Pad 10) on the module to the common ground of the system.

4. When using the capacitive sensing functionality, Pad 2 (P4.1) can be connected to a C

TAN K

capacitor (located off of Cypress BLE Module). C

Tank

should be used

if implementing a shield layer on the capacitive sensor. If used, this capacitor should be placed as close to the module as possible.

5. When using the capacitive sensing functionality, Pad 21 (P4.0) must be connected to a C

MOD

capacitor (located off of Cypress BLE Module). The value of this

capacitor is 2.2 nF and should be placed as close to the module as possible.

6. If the I

S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator

CYBLE-222014-01, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a ✓.

Table 4. Solder Pad Connection Definitions

Solder Pad

Number

1GND 2P4.1

3P5.1✓(TX) ✓(SCLK) ✓(SCL) ✓✓(Sensor) ✓✓ ✓ 4P5.0✓(RX) ✓(SS) ✓(SDA) ✓✓(Sensor) ✓✓ 5V 6P1.6 7P0.7✓(CTS) ✓(SCLK) ✓✓(Sensor) ✓✓(SWDCLK) ✓ 8P0.4✓(RX) ✓(MOSI) ✓(SDA) ✓✓(Sensor) ✓✓ ✓ 9P0.5✓(TX) ✓(MISO) ✓(SCL) ✓✓(Sensor) ✓✓

10 GND Ground Connection 11 P0 .6 12 P1.7 ✓(CTS) ✓(SCLK) ✓✓(Sensor) ✓✓ 13 V 14 XRES External Reset Hardware Connection Input 15 P3.5 16 P3.4 ✓(RX) ✓(SDA) ✓✓(Sensor) ✓✓ 17 P3.7 ✓(CTS) ✓(MISO) ✓(Sensor) ✓✓ ✓ 18 P1.4 ✓(RX) ✓(MOSI) ✓(SDA) ✓✓(Sensor) ✓✓ 19 P1.5 ✓(TX) ✓(MISO) ✓(SCL) ✓✓(Sensor) ✓✓ 20 P3.6 ✓(RTS) ✓✓(Sensor) ✓✓ 21 P4.0

Device

Port Pin

[3]

[4]

DDR

[5]

UART SPI I2C TCPWM

[2]

CapSense

Ground Connection

✓(CTS) ✓(MISO) ✓✓(Sensor /

TAN K

Radio Power Supply (1.9V to 5.5V)

WCO

ECO_OUT LCD SWD GPIO

Out

✓✓

)

✓(RTS) ✓(SS) ✓✓(Sensor) ✓✓

✓(RTS) ✓(SS) ✓✓(Sensor) ✓✓(SWDIO) ✓

Digital Power Supply Input (1.71 to 5.5V)

✓(TX) ✓(SCL) ✓✓(Sensor) ✓✓

✓(RTS) ✓(MOSI) ✓✓(C

) ✓✓

MOD

Document Number: 002-11186 Rev. ** Page 9 of 37

PRELIMINARY

CYBLE-222014-01

Power Supply Connections and Recommended External Components

Two Ferrite Bead Option

Single Ferrite Bead Option

Power Connections

The CYBLE-222014-01 contains two power supply connections, VDD and VDDR. The VDD connection supplies power for both digital and analog device operation. The VDDR connection supplies power for the device radio.

VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 9. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in

Ta bl e 7 .

The power supply ramp rate of VDD must be equal to or greater than that of VDDR.

Connection Options

Two connection options are available for any application:

1. Single supply: Connect VDD and VDDR to the same supply.

2. Independent supply: Power VDD and VDDR separately.

Figure 7. Recommended Host Schematic Options for a Single Supply Option

External Component Recommendation

In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection.

Figure 7 details the recommended host schematic options for a

single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-222014-01.

Figure 8 details the recommended host schematic for an

independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz. (Murata

BLM21PG331SN1D).

Figure 8. Recommended Host Schematic for an Independent Supply Option

Document Number: 002-11186 Rev. ** Page 10 of 37

PRELIMINARY

CYBLE-222014-01

The CYBLE-222014-01 schematic is shown in Figure 9.

Figure 9. CYBLE-222014-01 Schematic Diagram

Document Number: 002-11186 Rev. ** Page 11 of 37

PRELIMINARY

CYBLE-222014-01

Critical Components List

Ta bl e 5 details the critical components used in the CYBLE-222014-01 module.

Table 5. Critical Component List

Component Reference Designator Description

Silicon U1 76-pin WLCSP Programmable Radio-on-Chip (PRoC) with BLE Crystal Y1 24.000 MHz, 10PF Crystal Y2 32.768 kHz, 12.5PF Antenna E1 2.4 – 2.5 GHz chip antenna

Antenna Design

Ta bl e 6 details the chip antenna used in the CYBLE-222014-01 module. The specifications listed are according to the vendor’s

datasheet. The Cypress module performance improves many of these characteristics. For more information, see Ta b le 8 .

Table 6. Chip Antenna Specifications

Item Description

Chip Antenna Manufacturer Johanson Technology Inc. Chip Antenna Part Number 2450AT18B100 Frequency Range 2400 – 2500 MHz Peak Gain 0.5 dBi typical Average Gain -0.5 dBi typical Return Loss 9.5 dB minimum

Document Number: 002-11186 Rev. ** Page 12 of 37

PRELIMINARY

CYBLE-222014-01

Electrical Specification

Ta bl e 7 details the absolute maximum electrical characteristics for the Cypress BLE module.

Table 7. CYBLE-222014-01 Absolute Maximum Ratings

Parameter Description Min Typ Max Units Details/Conditions

DDD_ABS

CCD_ABS

DDD_RIPPLE

GPIO_ABS

GPIO_injection

LU Pin current for latch up –200 200 mA –

Ta bl e 8 details the RF characteristics for the Cypress BLE module.

Table 8. CYBLE-222014-01 RF Performance Characteristics

Parameter Description Min Ty p Max Units Details/Conditions

RFO RF output power on ANT –18 0 3 dBm

Avg

RL Return loss – –10.5 – dB –

Analog, digital, or radio supply relative to VSS (V

= V

SSD

Direct digital core voltage input relative to V

SSA

)

SSD

Maximum power supply ripple for VDD and V input voltage

–0.5 – 6 V Absolute maximum

–0.5 – 1.95 V Absolute maximum

DDR

– – 100 mV

3.0V supply Ripple frequency of 100 kHz

to 750 kHz GPIO voltage –0.5 – VDD +0.5 V Absolute maximum Maximum current per GPIO –25 – 25 mA Absolute maximum GPIO injection current: Maximum for VIH > VDD

and minimum for V

< V

–0.5 – 0.5 mA

Absolute maximum current

injected per pin

Configurable via register

settings

RF receive sensitivity on ANT – –87 – dBm

Guaranteed by design

simulation Module frequency range 2400 – 2480 MHz – Peak gain – 0.5 – dBi – Average gain – –0.5 – dBi –

Ta bl e 9 through Table 48 list the module level electrical characteristics for the CYBLE-222014-01. All specifications are valid for –40

°C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

Table 9. CYBLE-222014-01 DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

DD1

DD2

DDR1

DDR2

Active Mode, V

DD3

DD4

DD5

DD6

DD7

Power supply input voltage 1.8 – 5.5 V With regulator enabled

Power supply input voltage unregulated 1.71 1.8 1.89 V

Internally unregulated

supply Radio supply voltage (radio on) 1.9 – 5.5 V – Radio supply voltage (radio off) 1.71 – 5.5 V –

= 1.71 V to 5.5 V

Execute from flash; CPU at 3 MHz – 1.7 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 6 MHz – 2.5 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 12 MHz – 4 – mA

T = 25 °C,

= 3.3 V

Document Number: 002-11186 Rev. ** Page 13 of 37

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CYBLE-222014-01

Table 9. CYBLE-222014-01 DC Specifications (continued)

Parameter Description Min Typ Max Units Details/Conditions

DD8

DD9

DD10

DD11

DD12

Sleep Mode, V

DD13

Sleep Mode, V

DD14

Deep-Sleep Mode, V

DD15

DD16

DD17

DD18

Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 24 MHz – 7.1 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °C

Execute from flash; CPU at 48 MHz – 13.4 – mA

T = 25 °C,

= 3.3 V

Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °C

= 1.8 to 5.5 V

IMO on – – – mA

and V

= 1.9 to 5.5 V

DDR

ECO on – – – mA

= 1.8 to 3.6 V

WDT with WCO on – 1.5 – µA

T = 25 °C, VDD = 3.3 V,

SYSCLK = 3 MHz

T = 25 °C, V

SYSCLK = 3 MHz

= 3.3 V,

T = 25 °C,

VDD = 3.3 V WDT with WCO on – – – µA T = –40 °C to 85 °C

WDT with WCO on – – – µA

T = 25 °C,

= 5 V

WDT with WCO on – – – µA T = –40 °C to 85 °C

Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)

DD19

DD20

WDT with WCO on – – – µA T = 25 °C WDT with WCO on – – – µA T = –40 °C to 85 °C

Hibernate Mode, VDD = 1.8 to 3.6 V

DD27

DD28

GPIO and reset active – 150 – nA

GPIO and reset active – – – nA T = –40 °C to 85 °C

Hibernate Mode, V

DD29

DD30

Stop Mode, V

DD33

DD34

DD35

DD36

Stop Mode, V

DD37

DD38

DD39

DD40

GPIO and reset active – – – nA

GPIO and reset active – – – nA T = –40 °C to 85 °C

= 1.8 to 3.6 V

Stop-mode current (VDD)–20–nA

Stop-mode current (V

Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C

Stop-mode current (V

= 3.6 to 5.5 V

Stop-mode current (VDD)–––nA

Stop-mode current (V

Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C Stop-mode current (V

= 3.6 to 5.5 V

) – 40 –- nA

DDR

)–––nA

DDR

)–––nA

DDR

) – – – nA T = –40 °C to 85 °C

DDR

T = 25 °C,

VDD = 3.3 V

T = 25 °C,

= 5 V

T = 25 °C,

= 3.3 V

T = 25 °C,

= 3.3 V

DDR

T = –40 °C to 85 °C,

= 1.9 V to 3.6 V

DDR

T = 25 °C,

= 5 V

T = 25 °C,

= 5 V

DDR

Document Number: 002-11186 Rev. ** Page 14 of 37

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CYBLE-222014-01

Table 10. AC Specifications

Note

7. V

must not exceed VDD + 0.2 V.

Parameter Description Min Typ Max Units Details/Conditions

CPU

SLEEP

DEEPSLEEP

HIBERNATE

STOP

CPU frequency 3 – 48 MHz 1.71 V VDD 5.5 V Wakeup from Sleep mode – 0 – µs Guaranteed by characterization

Wakeup from Deep-Sleep mode – – 25 µs

24-MHz IMO. Guaranteed by

characterization Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization Wakeup from Stop mode – – 2.2 ms XRES wakeup

GPIO

Table 11. GPIO DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

[7]

PULLUP

PULLDOWN

IL_CTBM

HYSTTL

HYSCMOS

DIODE

TOT_GPIO

Input voltage HIGH threshold 0.7 × V LVTTL input, V LVTTL input, V

< 2.7 V 0.7 × V

>= 2.7 V 2.0 – – V –

Input voltage LOW threshold – – 0.3 × V LVTTL input, V LVTTL input, V Output voltage HIGH level V Output voltage HIGH level V

< 2.7 V – – 0.3× V

>= 2.7 V – – 0.8 V –

–0.6 – – V IOH = 4 mA at 3.3-V VDD

–0.5 – – V IOH = 1 mA at 1.8-V V

Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V V Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V V Output voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V V Pull-up resistor 3.5 5.6 8.5 k – Pull-down resistor 3.5 5.6 8.5 k – Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V Input leakage on CTBm input pins – – 4 nA – Input capacitance – – 7 pF – Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V Input hysteresis CMOS 0.05 × V Current through protection diode to

DD/VSS

Maximum total source or sink chip current

– – 100 µA –

– – 200 mA –

– – V CMOS input

– – V –

VCMOS input

V–

– – 1 –

Document Number: 002-11186 Rev. ** Page 15 of 37

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Table 12. GPIO AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

RISEF

FALLF

RISES

FALLS

GPIOUT1

GPIOUT2

GPIOUT3

GPIOUT4

GPIOIN

Rise time in Fast-Strong mode 2 – 12 ns 3.3-V V Fall time in Fast-Strong mode 2 – 12 ns 3.3-V V Rise time in Slow-Strong mode 10 – 60 ns 3.3-V V Fall time in Slow-Strong mode 10 – 60 ns 3.3-V V GPIO Fout; 3.3 V  V

Fast-Strong mode GPIO Fout; 1.7 VV

Fast-Strong mode GPIO Fout; 3.3 V V

Slow-Strong mode GPIO Fout; 1.7 V V

Slow-Strong mode GPIO input operating frequency

1.71 V V

5.5 V

3.3 V

5.5 V

3.3 V

––33MHz

– – 16.7 MHz

–– 7MHz

––3.5MHz

90/10%, 25 pF load, 60/40 duty cycle

– – 48 MHz 90/10% V

DDD

, C , C , C , C

LOAD

= 25 pF = 25 pF = 25 pF = 25 pF

Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)

Parameter Description Min Ty p Max Units Details/Conditions

Input leakage (absolute value).

> V

– – 10 µA 25°C, VDD = 0 V, VIH = 3.0 V

Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V

Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)

Parameter Description Min Typ Max Units Details/Conditions

RISE_OVFS

FALL_OVFS

RISESS

FALLSS

GPIOUT1

GPIOUT2

Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V

Output rise time in Slow-Strong mode 10 – 60 ns

Output fall time in Slow-Strong mode 10 – 60 ns

GPIO F Fast-Strong mode

; 3.3 V V

OUT

; 1.71 V V

OUT

5.5 V

3.3 V

––24MHz

––16MHz

25 pF load, 10%-90%,

= 3.3 V

25 pF load, 10%-90%,

= 3.3 V

90/10%, 25 pF load, 60/40 duty cycle

XRES

Table 15. XRES DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

PULLUP

HYSXRES

DIODE

Input voltage HIGH threshold 0.7 × V Input voltage LOW threshold – – 0.3 × V

– – V CMOS input

DDD

V CMOS input

DDD

Pull-up resistor 3.5 5.6 8.5 k – Input capacitance – 3 – pF – Input voltage hysteresis – 100 – mV – Current through protection diode to

DD/VSS

– – 100 µA –

Document Number: 002-11186 Rev. ** Page 16 of 37

PRELIMINARY

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Table 16. XRES AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

RESETWIDTH

Reset pulse width 1 – – µs –

Temperature Sensor

Table 17. Temperature Sensor Specifications

Parameter Description Min Typ Max Units Details/Conditions

SENSACC

Temperature-sensor accuracy –5 ±1 5 °C –40 to +85 °C

SAR ADC

Table 18. SAR ADC DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

A_RES Resolution – – 12 bits A_CHNIS_S Number of channels - single-ended – – 8 8 full-speed A-CHNKS_D Number of channels - differential – – 4 Diff inputs use

neighboring I/O A-MONO Monotonicity – – – Yes A_GAINERR Gain error – – ±0.1 % With external

reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V

REF

A_ISAR Current consumption – – 1 mA A_VINS Input voltage range - single-ended V A_VIND Input voltage range - differential V

–VDDV – V

V A_INRES Input resistance – – 2.2 k A_INCAP Input capacitance – – 10 pF VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg

(1.024 V)

Table 19. SAR ADC AC Specifications

Parameter Description Min Typ Max Units

Details/

Conditions

A_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V

reference A_CMRR Common-mode rejection ratio 66 – – dB A_SAMP Sample rate – – 1 Msps 806 Ksps for More Part

Numbers devices Fsarintref SAR operating speed without external ref.

– – 100 Ksps 12-bit resolution

bypass

A_SNR Signal-to-noise ratio (SNR) 65 – – dB F

= 10 kHz

A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz A_INL Integral nonlinearity. V

1 Msps

A_INL Integral nonlinearity. V

1 Msps

A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,

500 Ksps

= 1.71 V to 5.5 V,

= 1.71 V to 3.6 V,

DDD

–1.7 – 2 LSB V

–1.5 – 1.7 LSB V

= 1 V to V

REF

= 1.71 V to V

REF

= 1 V to V

REF

Document Number: 002-11186 Rev. ** Page 17 of 37

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Table 19. SAR ADC AC Specifications (continued)

Parameter Description Min Typ Max Units

A_dnl Differential nonlinearity. V

5.5 V, 1 Msps

A_DNL Differential nonlinearity. VDD = 1.71 V to

= 1.71 V to

–1 – 2.2 LSB V

–1 – 2 LSB V

3.6 V, 1 Msps

A_DNL Differential nonlinearity. VDD = 1.71 V to

–1 – 2.2 LSB V

5.5 V, 500 Ksps

Details/

Conditions

= 1 V to V

REF

= 1.71 V to V

REF

= 1 V to V

REF

A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz

CSD

CSD Block Specifications

Parameter Description Min Ty p Max Units

CSD

Voltage range of operation 1.71 – 5.5 V

Details/

Conditions

IDAC1 DNL for 8-bit resolution –1 – 1 LSB IDAC1 INL for 8-bit resolution –3 – 3 LSB IDAC2 DNL for 7-bit resolution –1 – 1 LSB IDAC2 INL for 7-bit resolution –3 – 3 LSB SNR Ratio of counts of finger to noise 5 – – Ratio

Capacitance range of

9 pF to 35 pF, 0.1-pF

sensitivity. Radio is not

operating during the

scan

DAC1_CRT1

Output current of IDAC1 (8 bits) in High

–612 – µA

range

DAC1_CRT2

Output current of IDAC1 (8 bits) in Low

–306 – µA

range

DAC2_CRT1

Output current of IDAC2 (7 bits) in High

–305 – µA

range

DAC2_CRT2

Output current of IDAC2 (7 bits) in Low

–153 – µA

range

Document Number: 002-11186 Rev. ** Page 18 of 37

PRELIMINARY

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Digital Peripherals

Timer

Table 20. Timer DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TIM1

TIM2

TIM3

Table 21. Timer AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TIMFREQ

CAPWINT

CAPWEXT

TIMRES

TENWIDINT

TENWIDEXT

TIMRESWINT

TIMRESEXT

Counter

Table 22. Counter DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

CTR1

CTR2

CTR3

Block current consumption at 3 MHz – – 43 µA 16-bit timer Block current consumption at 12 MHz – – 152 µA 16-bit timer Block current consumption at 48 MHz – – 620 µA 16-bit timer

Operating frequency F Capture pulse width (internal) 2 × T Capture pulse width (external) 2 × T Timer resolution T Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

Block current consumption at 3 MHz – – 43

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns ––ns

16-bit counter

µA

Block current consumption at 12 MHz – – 152 µA 16-bit counter Block current consumption at 48 MHz – – 620 µA 16-bit counter

Table 23. Counter AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

CTRFREQ

CTRPWINT

CTRPWEXT

CTRES

CENWIDINT

CENWIDEXT

CTRRESWINT

CTRRESWEXT

Operating frequency F

CLK

Capture pulse width (internal) 2 × T Capture pulse width (external) 2 × T Counter Resolution T

CLK

Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns –– ns

Document Number: 002-11186 Rev. ** Page 19 of 37

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Pulse Width Modulation (PWM)

Table 24. PWM DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

PWM1

PWM2

PWM3

Block current consumption at 3 MHz – – 43 µA 16-bit PWM Block current consumption at 12 MHz – – 152 µA 16-bit PWM Block current consumption at 48 MHz – – 620 µA 16-bit PWM

Table 25. PWM AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

PWMFREQ

PWMPWINT

PWMEXT

PWMKILLINT

PWMKILLEXT

PWMEINT

PWMENEXT

PWMRESWINT

PWMRESWEXT

Operating frequency F

CLK

Pulse width (internal) 2 × T Pulse width (external) 2 × T Kill pulse width (internal) 2 × T Kill pulse width (external) 2 × T Enable pulse width (internal) 2 × T Enable pulse width (external) 2 × T Reset pulse width (internal) 2 × T Reset pulse width (external) 2 × T

CLK

–48MHz ––ns ––ns ––ns ––ns ––ns ––ns ––ns ––ns

LCD Direct Drive

Table 26. LCD Direct Drive DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

LCDLOW

LCDCAP

LCD I

LCDOP1

LCDOP2

OFFSET

Operating current in low-power mode – 17.5 – µA 16 × 4 small segment

display at 50 Hz

LCD capacitance per segment/common

– 500 5000 pF

driver Long-term segment offset – 20 – mV

LCD system operating current V

= 5 V

BIAS

LCD system operating current V

= 3.3 V

BIAS

– 2 – mA 32 × 4 segments. 50 Hz at

25 °C

– 2 – mA 32 × 4 segments

50 Hz at 25 °C

Table 27. LCD Direct Drive AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

LCD

LCD frame rate 10 50 150 Hz

Document Number: 002-11186 Rev. ** Page 20 of 37

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Serial Communication

Table 28. Fixed I2C DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

I2C1

I2C2

I2C3

I2C4

Table 29. Fixed I

Block current consumption at 100 kHz – – Block current consumption at 400 kHz – – Block current consumption at 1 Mbps – – I2C enabled in Deep-Sleep mode – –

C AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

I2C1

Bit rate – – 1 Mbps

Table 30. Fixed UART DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

UART1

UART2

Block current consumption at 100 kbps – – 55 µA – Block current consumption at 1000 kbps – – 360 µA –

Table 31. Fixed UART AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

UART

Bit rate – – 1 Mbps –

50 155 390

1.4

µA – µA – µA – µA –

Table 32. Fixed SPI DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

SPI1

SPI2

SPI3

Block current consumption at 1 Mbps – – 360 µA – Block current consumption at 4 Mbps – – 560 µA – Block current consumption at 8 Mbps – – 600 µA –

Table 33. Fixed SPI AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

SPI

SPI operating frequency (master; 6x over sampling) – – 8 MHz –

Table 34. Fixed SPI Master Mode AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

DMO

DSI

HMO

MOSI valid after SCLK driving edge – – 18 ns – MISO valid before SCLK capturing edge

Full clock, late MISO sampling used

20 – – ns Full clock, late MISO sampling

Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge

Table 35. Fixed SPI Slave Mode AC Specifications

Parameter Description Min Ty p Max Units

DMI

DSO

DSO_ext

HSO

SSELSCK

MOSI valid before SCLK capturing edge 40 – – ns MISO valid after SCLK driving edge – – 42 + 3 × T MISO Valid after SCLK driving edge in

external clock mode. V

< 3.0 V

– – 53 ns

CPU

Previous MISO data hold time 0 – – ns SSEL valid to first SCK valid edge 100 – – ns

Document Number: 002-11186 Rev. ** Page 21 of 37

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Memory

Note

8. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

Table 36. Flash DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

WS48

WS32

WS16

Erase and program voltage 1.71 – 5.5 V – Number of Wait states at 32–48 MHz 2 – – CPU execution from flash Number of Wait states at 16–32 MHz 1 – – CPU execution from flash Number of Wait states for 0–16 MHz 0 – – CPU execution from flash

Table 37. Flash AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ROWWRITE

ROWERASE

ROWPROGRAM

BULKERASE

DEVPROG

END

RET

RET2

[8]

Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes

[8]

Row erase time – – 13 ms –

[8]

Row program time after erase – – 7 ms –

[8]

Bulk erase time (128 KB) – – 35 ms –

[8]

Total device program time – – 25 seconds – Flash endurance 100 K – – cycles – Flash retention. TA  55 °C, 100 K P/E cycles 20 – – years – Flash retention. TA  85 °C, 10 K P/E cycles 10 – – years –

System Resources

Power-on-Reset (POR)

Table 38. POR DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

RISEIPOR

FALLIPOR

IPORHYST

Rising trip voltage 0.80 – 1.45 V – Falling trip voltage 0.75 – 1.40 V – Hysteresis 15 – 200 mV –

Table 39. POR AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

PPOR_TR

Precision power-on reset (PPOR) response time in Active and Sleep modes

––1µs –

Table 40. Brown-Out Detect

Parameter Description Min Typ Max Units Details/Conditions

FALLPPOR

FALLDPSLP

BOD trip voltage in Active and Sleep modes 1.64 – – V – BOD trip voltage in Deep Sleep 1.4 – – V –

Table 41. Hibernate Reset

Parameter Description Min Ty p Max Units Details/Conditions

HBRTRIP

BOD trip voltage in Hibernate 1.1 – – V –

Document Number: 002-11186 Rev. ** Page 22 of 37

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Voltage Monitors (LVD)

Table 42. Voltage Monitor DC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

V V V V V V V V V V V V V V V V

LVI 1

LVI 2

LVI 3

LVI 4

LVI 5

LVI 6

LVI 7

LVI 8

LVI 9

LVI 10

LVI 11

LVI 12

LVI 13

LVI 14

LVI 15

LVI 16

LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V – LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V – LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V – LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V – LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V – LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V – LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V – LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V – LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V – LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V – LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V – LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V – LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V – LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V – LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V – LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –

LVI_IDD Block current – – 100 µA –

Table 43. Voltage Monitor AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

MONTRIP

Voltage monitor trip time – – 1 µs –

SWD Interface

Table 44. SWD Interface Specifications

Parameter Description Min Typ Max Units Details/Conditions

F_SWDCLK1 3.3 V  V F_SWDCLK2 1.71 V  V

 5.5 V – – 14 MHz SWDCLK 1/3 CPU clock frequency

 3.3 V – – 7 MHz SWDCLK 1/3 CPU clock frequency

T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns – T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns – T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns – T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –

Document Number: 002-11186 Rev. ** Page 23 of 37

PRELIMINARY

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Internal Main Oscillator

Table 45. IMO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IMO1

IMO2

IMO3

IMO4

IMO5

IMO operating current at 48 MHz – – 1000 µA – IMO operating current at 24 MHz – – 325 µA – IMO operating current at 12 MHz – – 225 µA – IMO operating current at 6 MHz – – 180 µA – IMO operating current at 3 MHz – – 150 µA –

Table 46. IMO AC Specifications

Parameter Description Min Ty p Max Units Details/Conditions

IMOTOL3

Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration IMO startup time – 12 – µs –

Internal Low-Speed Oscillator

Table 47. ILO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ILO2

ILO operating current at 32 kHz – 0.3 1.05 µA –

Table 48. ILO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

STARTILO1

ILOTRIM1

ILO startup time – – 2 ms – 32-kHz trimmed frequency 15 32 50 kHz –

Table 49. ECO Trim Value Specification

Parameter Description Value Details/Conditions

ECO

TRIM

24-MHz trim value (firmware configuration)

0x00003FFA

Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG

BLE Subsystem

Table 50. BLE Subsystem

Parameter Description Min Ty p Max Units

Details/

Conditions

RF Receiver Specification

RXS, IDLE RX sensitivity with idle transmitter – –89 – dBm

RX sensitivity with idle transmitter excluding Balun loss

– –91 – dBm Guaranteed by design

simulation

RXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 dBm RF-PHY Specification

(RCV-LE/CA/01/C)

RXS, HIGHGAIN RX sensitivity in high-gain mode with idle

– –91 – dBm

transmitter

PRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification

(RCV-LE/CA/06/C)

CI1 Cochannel interference,

Wanted signal at –67 dBm and Interferer

– 9 21 dB RF-PHY Specification

(RCV-LE/CA/03/C)

at FRX

Document Number: 002-11186 Rev. ** Page 24 of 37

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Parameter Description Min Ty p Max Units

Details/

Conditions

CI2 Adjacent channel interference

Wanted signal at –67 dBm and Interferer at FRX ±1 MHz

CI3 Adjacent channel interference

Wanted signal at –67 dBm and Interferer at FRX ±2 MHz

CI4 Adjacent channel interference

Wanted signal at –67 dBm and Interferer at FRX ±3 MHz

CI5 Adjacent channel interference

Wanted Signal at –67 dBm and Interferer at Image frequency (F

CI3 Adjacent channel interference

Wanted signal at –67 dBm and Interferer at Image frequency (F

OBB1 Out-of-band blocking,

Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz

OBB2 Out-of-band blocking,

Wanted signal at –67 dBm and Interferer at F = 2003–2399 MHz

OBB3 Out-of-band blocking,

Wanted signal at –67 dBm and Interferer at F = 2484–2997 MHz

OBB4 Out-of-band blocking,

Wanted signal a –67 dBm and Interferer at F = 3000–12750 MHz

IMD Intermodulation performance

Wanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel

RXSE1 Receiver spurious emission

30 MHz to 1.0 GHz

RXSE2 Receiver spurious emission

1.0 GHz to 12.75 GHz

RF Transmitter Specifications

IMAGE

– 3 15 dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –29 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –39 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

– –20 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

)

– –30 – dB RF-PHY Specification

(RCV-LE/CA/03/C)

± 1 MHz)

–30 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–35 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–35 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–30 –27 – dBm RF-PHY Specification

(RCV-LE/CA/04/C)

–50 – – dBm RF-PHY Specification

(RCV-LE/CA/05/C)

– – –57 dBm 100-kHz measurement

bandwidth ETSI EN300 328 V1.8.1

– – –47 dBm 1-MHz measurement

bandwidth ETSI EN300 328 V1.8.1

TXP, ACC RF power accuracy – ±4 – dB

TXP, RANGE RF power control range – 20 – dB

TXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 – dBm

TXP, MAX Output power, maximum power setting

(PA10)

TXP, MIN Output power, minimum power setting

(PA1)

F2AVG Average frequency deviation for

10101010 pattern

F1AVG Average frequency deviation for

11110 00 0 pattern

Document Number: 002-11186 Rev. ** Page 25 of 37

–3 – dBm

– –18 – dBm

185 – – kHz RF-PHY Specification

(TRM-LE/CA/05/C)

225 250 275 kHz RF-PHY Specification

(TRM-LE/CA/05/C)

PRELIMINARY

CYBLE-222014-01

Parameter Description Min Ty p Max Units

EO Eye opening = F2AVG/F1AVG 0.8 – – RF-PHY Specification

(TRM-LE/CA/05/C)

FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification

(TRM-LE/CA/06/C)

FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification

FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification

FTX, DR Maximum drift rate –20 – 20 kHz/

50 µs

IBSE1 In-band spurious emission at 2-MHz

offset

IBSE2 In-band spurious emission at 3-MHz

offset

TXSE1 Transmitter spurious emissions

(average), <1.0 GHz

TXSE2 Transmitter spurious emissions

(average), >1.0 GHz

RF Current Specifications

IRX Receive current in normal mode – 18.7 – mA

– – –20 dBm RF-PHY Specification

– – -30 dBm RF-PHY Specification

– – -55.5 dBm FCC-15.247

– – -41.5 dBm FCC-15.247

(TRM-LE/CA/06/C)

(TRM-LE/CA/06/C) RF-PHY Specification

(TRM-LE/CA/06/C)

(TRM-LE/CA/03/C)

Details/

Conditions

IRX_RF Radio receive current in normal mode – 16.4 – mA Measured at V

IRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mA

ITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – mA

ITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – mA

ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – mA Measured at V

ITX_RF, 0dBm Radio TX current at 0 dBm excluding

Balun loss

ITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – mA

ITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – mA

ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – mA

ITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – mA

Iavg_1sec, 0dBm Average current at 1-second BLE

connection interval

Iavg_4sec, 0dBm Average current at 4-second BLE

connection interval

General RF Specifications

FREQ RF operating frequency 2400 – 2482 MHz

– 14.2 – mA Guaranteed by design

simulation

– 18.9 – µA TXP: 0 dBm; ±20-ppm

master and slave clock accuracy. For empty PDU exchange

– 6.25 – µA TXP: 0 dBm; ±20-ppm

master and slave clock accuracy. For empty PDU exchange

DDR

CHBW Channel spacing – 2 – MHz

DR On-air data rate – 1000 – kbps

IDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 µs

Document Number: 002-11186 Rev. ** Page 26 of 37

PRELIMINARY

CYBLE-222014-01

Parameter Description Min Ty p Max Units

IDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 µs

RSSI Specifications

RSSI, ACC RSSI accuracy – ±5 – dB

RSSI, RES RSSI resolution – 1 – dB

RSSI, PER RSSI sample period – 6 – µs

Details/

Conditions

Document Number: 002-11186 Rev. ** Page 27 of 37

PRELIMINARY

CYBLE-222014-01

Environmental Specifications

Note

9. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.

Environmental Compliance

This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBLE-222014-01 module is certified under the following RF certification standards:

■ FCC

■ CE

■ IC

■ MIC

■ KC

Environmental Conditions

Ta bl e 5 1 describes the operating and storage conditions for the Cypress BLE module.

Table 51. Environmental Conditions for CYBLE-222014-01

Description Minimum Specification Maximum Specification

Operating temperature -40 °C 85 °C Operating humidity (relative, non-condensation) 5% 85% Thermal ramp rate Storage temperature –40 °C 85 °C Storage temperature and humidity ESD: Module integrated into system

Components

[9]

– 3 °C/minute

– 85 ° C at 85%

–

15 kV Air

2.2 kV Contact

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Document Number: 002-11186 Rev. ** Page 28 of 37

PRELIMINARY

CYBLE-222014-01

Regulatory Information

FCC

FCC NOTICE: The device CYBLE-222014-01, including the antenna 2450AT18B100 from Johanson Technology, complies with Part 15 of the FCC

Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■ Reorient or relocate the receiving antenna.

■ Increase the separation between the equipment and receiver.

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

■ Consult the dealer or an experienced radio/TV technician for help

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: TBD.

In any case the end product must be labeled exterior with “Contains FCC ID: TBD”

ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these

fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas

in Table 6 on page 12, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.

The radiated output power of CYBLE-222014-01 with the chip antenna mounted (FCC ID: TBD) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-222014-01 in such a manner that minimizes the potential for human contact during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-11186 Rev. ** Page 29 of 37

PRELIMINARY

CYBLE-222014-01

Industry Canada (IC) Certification

CYBLE-222014-01 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: TBD Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antennas listed in Table 6 on page 12, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

IC NOTICE: The device CYBLE-222014-01 including the antenna 2450AT18B100 from Johanson technology, complies with Canada RSS-GEN

Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

IC RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)

this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label

on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is TBD. In any case, the end product must be labeled in its exterior with "Contains IC: TBD"

European R&TTE Declaration of Conformity

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-222014-01 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows:

All versions of the CYBLE-222014-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: 002-11186 Rev. ** Page 30 of 37

PRELIMINARY

CYBLE-222014-01

MIC Japan

CYBLE-222014-01 is certified as a module with type certification number TBD. End products that integrate CYBLE-222014-01 do not need additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

KC Korea

CYBLE-222014-01 is certified for use in Korea with certificate number TBD.

Document Number: 002-11186 Rev. ** Page 31 of 37

PRELIMINARY

CYBLE-222014-01

Packaging

Table 52. Solder Reflow Peak Temperature

Module Part Number Package Maximum Peak Temperature Maximum Time at PeakTemperature No. of Cycles

CYBLE-222014-01 22-pad SMT 260 °C 30 seconds 2

Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number Package MSL

CYBLE-222014-01 22-pad SMT MSL 3

The CYBLE-222014-01 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-222014-01.

Figure 10. CYBLE-222014-01 Tape Dimensions

Figure 11 details the orientation of the CYBLE-222014-01 in the tape as well as the direction for unreeling.

Figure 11. Component Orientation in Tape and Unreeling Direction

Document Number: 002-11186 Rev. ** Page 32 of 37

PRELIMINARY

CYBLE-222014-01

Figure 12 details reel dimensions used for the CYBLE-222014-01.

Figure 12. Reel Dimensions

The CYBLE-222014-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-222014-01 is detailed in Figure 13.

Figure 13. CYBLE-222014-01 Center of Mass

Document Number: 002-11186 Rev. ** Page 33 of 37

PRELIMINARY

CYBLE-222014-01

Ordering Information

The CYBLE-222014-01 part number and features are listed in the following table.

Part Number

CYBLE-222014-01 48 256 Yes Yes 2 4 1 Msps Yes Ye s 22-SMT Tape and

CPU

Speed

(MHz)

Flash

Size

(KB)

DMA CapSense SCB TCPWM

12-Bit

SAR ADC

I2S LCD Package Packing

Reel

Part Numbering Convention

The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.

For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134 U.S. Cypress Headquarter Contact Info (408) 943-2600 Cypress website address http://www.cypress.com

Document Number: 002-11186 Rev. ** Page 34 of 37

PRELIMINARY

CYBLE-222014-01

Acronyms

Acronym Description

BLE Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group CE European Conformity CSA Canadian Standards Association DMA direct memory access EMI electromagnetic interference ESD electrostatic discharge FCC Federal Communications Commission GPIO general-purpose input/output IC Industry Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications (Japan) PCB printed circuit board RX receive QDID qualification design ID SMT surface-mount technology; a method for producing electronic circuitry in which the components are placed

TCPWM timer, counter, pulse width modulator (PWM) TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association) TX transmit

directly onto the surface of PCBs

Document Conventions

Units of Measure

Symbol Unit of Measure

°C degree Celsius kV kilovolt mA milliamperes mm millimeters mV millivolt µA microamperes µm micrometers MHz megahertz GHz gigahertz Vvolt

Document Number: 002-11186 Rev. ** Page 35 of 37

PRELIMINARY

CYBLE-222014-01

Document History Page

Document Title: CYBLE-222014-01, EZ-BLE™ PRoC™ Bluetooth 4.2 Module Document Number: 002-11186

Revision ECN

** 5142440 DSO 02/18/2016 Preliminary datasheet for CYBLE-222014-01 module.

Orig. of Change

Submission

Date

Description of Change

Document Number: 002-11186 Rev. ** Page 36 of 37

PRELIMINARY

CYBLE-222014-01

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

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PSoC® Solutions

cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

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Community | Forums | Blogs | Video | Training

Technical Support

cypress.com/support

© Cypress Semiconductor Corporation, 2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circ uitry embodied in a Cypress product. Nor does it con vey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-11186 Rev. ** Revised February 18, 2016 Page 37 of 37

All products and company names mentioned in this document may be the trademarks of their respective holders.

Cypress Semiconductor 2005 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Module Description

Power Consumption

Functional Capabilities

Benefits

More Information

PSoC® Creator™ Integrated Design Environment (IDE)

Blutooth Low Energy Component

Technical Support

Contents

Overview

Module Description

Pad Connection Interface

Recommended Host PCB Layout

Power Supply Connections and Recommended External Components

Connection Options

External Component Recommendation

Critical Components List

Antenna Design

Electrical Specification

GPIO

XRES

Digital Peripherals

Serial Communication

Memory

System Resources

Environmental Specifications

Environmental Compliance

RF Certification

Environmental Conditions

ESD and EMI Protection

Regulatory Information

Industry Canada (IC) Certification

European R&TTE Declaration of Conformity

MIC Japan

KC Korea

Packaging

Ordering Information

Part Numbering Convention

Acronyms

Document Conventions

Units of Measure

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Products

PSoC® Solutions

Cypress Developer Community

Technical Support