Cypress Z9973 User Manual
Z9973
3.3V , 125-MHz, Multi-Output Zero Delay Buffer
Features
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
D
D
D
D
D
D
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
SELB(0,1)
SELC(0,1)
FB_SEL(0,1)
SCLK
SDATA
INV_CLK
0
1
Power-On
Reset
2
2
2
2
Phase
Detector
LPF
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
Output Disable
Circuitry
VCO
0
1
0
1
/2
12
T a ble 1. Frequency Table
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 F
[1]
VC0
00008x
000112x
001016x
001120x
010016x
010124x
011032x
011140x
10004x
10016x
10108x
101110x
11008x
110112x
111016x
111120x
Note:
1. x = the reference input frequency, 200 MHz < F
.
< 480 MHz.
VCO
Pin Configuration
Sync
Q
Frz
Sync
Q
Frz
Sync
Q
Frz
Sync
Q
Frz
Sync
Q
Frz
Sync
Q
Frz
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VCO_SEL
VDDC
QA1
QA0
VSS
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
VDD
14 15 16 17 18 19 20 21 22 23 24 25 26
INV_CLK
QC3
VSS
Z9973
QC2
VDDC
SELB1
SELB0
SELA1
SELA0
VDDC
QA3
QA2
VSS
VSS
39
QB0
38
VDDC
37
QB1
36
VSS
35
QB2
34
VDDC
33
QB3
32
FB_IN
31
VSS
30
FB_OUT
29
VDDC
28
27
FB_SEL0
FB_SEL1
SYNC
VSS
QC0
VDDC
QC1
SELC0
SELC1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07089 Rev. *D Revised December 21, 2002
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Z9973
Pin Description
Pin Number Pin Name PWR I/O Type Pin Description
11 PECL_CLK I PU PECL Clock Input.
12 PECL_CLK# I PD PECL Clock Input.
9TCLK0 IPUExternal Reference/Test Clock Input.
10 TCLK1 I PU External Reference/Test Clock Input.
44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.
29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The
25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchroni-
42, 43 SELA(1,0 ) I PU Frequency Se lect In put s. Th ese i nput s sele ct th e div ider ra tio at QA(0:3 )
40, 41 SELB(1,0 ) I PU Frequency Se lect In put s. Th ese i nput s sele ct th e div ider ra tio at QB(0:3 )
19, 20 SELC(1,0) I PU Frequency Select Input s . These in puts s elect the divi der ratio at Q C(0:3)
5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
52 VCO_SEL I PU VCO Divider Select Input. When set LOW, the VCO output is divided by
31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the
6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW,
7 REF_SEL I PU Reference Select Input. When HIG H, the crystal osc illator is selected. An d
8 TCLK_SEL I PU TCLK Select Input. When LOW , TCLK0 is selected and when HIGH TCLK1
2MR#/OE IPUMaster Reset/Output Enable Input. When ass erted LOW, res ets all of the
14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) out puts are inverted. Whe n
3SCLK IPUSerial Clock Input. Clocks data at SDATA into the internal register.
4SDATA IPUSerial Data Input. Input data is clocked to the internal register to
17, 22, 28,
33,37, 45, 49
13 VDD 3.3V Supply for PLL.
1, 15, 24, 30,
35, 39, 47, 51
Note:
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
[2]
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divi der ratios
selected.
outputs. See Table 2.
outputs. See Table 2.
outputs. See Table 2.
output. See Table 1.
2. When set HIGH, the divider is bypassed. See Table 1.
phase-locked loop (PLL).
PLL is bypassed.
when LOW, TCLK (0,1) is the referenc e clo ck .
is selected.
internal flip-flops and also disables all of the outputs. When pulled HIGH,
releases the internal flip-flops from reset and enables all of the outputs.
set LOW, the inverter is bypassed.
enable/disable individual outputs. This provides flexibility in power
management.
VDDC 3.3V Power Supply for Output Clock Buffers.
VSS Common Ground.
Document #: 38-07089 Rev. *D Page 2 of 9
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Z9973
Functional Description
The Z9973 has an integrat ed PL L that prov ides low -ske w and
low-jitter clock output s for high-performa nce microproc essors.
Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector co mp ares the inp ut referen ce cloc k to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is runnin g at mu ltiple s of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
Table 2. Frequency Select Inputs
VCO_SEL SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC
0 0 0VCO/80 0VCO/80 0VCO/4
0 0 1VCO/120 1VCO/120 1 VCO/8
0 1 0VCO/161 0VCO/161 0VCO/12
0 1 1VCO/241 1VCO/201 1VCO/16
1 0 0VCO/40 0VCO/40 0VCO/2
1 0 1VCO/60 1VCO/60 1VCO/4
1 1 0VCO/81 0VCO/81 0VCO/6
1 1 1VCO/121 1VCO/101 1 VCO/8
inputs (see Table 1). The VCO frequency is then divided to
provide the required output frequencies. These dividers are
set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see
Table 2). For situations in which the VCO needs to run at
relatively low frequencies and hence might not be stable,
assert VCO_SEL LOW to d ivide the VCO frequency by 2. This
will maintain the desired output relationships, but will provide
an enhanced PLL lock range.
The Z9973 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback
outputs to the Z9973 or a secon d PLL device to generate earl y
or late clocks for a specific design. This inversion does not
affect the output to output skew.
Zero Delay Buffer
When used as a ze ro de lay bu ff er, the Z9973 will likely be i n a
nested clock tree application. For these applications the
Z9973 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to us e LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The Z9973 can then lock onto the LVPECL
reference and translate with near-zero delay to low-skew
outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between inputs and outputs. Because the static phase
offset is a function o f the referenc e clock, the Tpd of t he Z9973
is a function of the configuration used.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
1. contain short or “runt” clock perio ds. These are clock cy cles
in which the cycle(s) are shorter in period than either the
old or new frequency to which it is being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency to which it is being transitioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The Z9973 monitors the
relationship between the QA and the QC output clocks. It
provides a low-going pulse, one p eriod in durat ion, one peri od
prior to the coincident ri sin g edges of th e QA and Q C out put s.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output (see Figure 1). Note. The SYNC output is defined for
all possible combinations of the QA and QC outputs even
though under some relationships the lower frequency clock
could be used as a synchronizing signal.
Document #: 38-07089 Rev. *D Page 3 of 9
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