Cypress XDR CY24272, XDR CY24271 User Manual

CY24272

Rambus® XDR™ Clock Generator with

Zero SDA Hold Time

Features

CLK0
CLK0B

CLK1
CLK1B

CLK2
CLK2B

CLK3
CLK3B

REFCLK,REFCLKB

SCL SDA ID0

ID1

EN

RegA

EN

RegB

EN

RegC

EN

RegD

PLL

Bypass
MUX

/BYPASS EN

Logic Block Diagram

■ Meets Rambus

requirements

■ 25 ps typical cycle-to-cycle jitter
❐ –135 dBc/Hz typical phase noise at 20 MHz offset

■ 100 or 133 MHz differential clock input

■ 300–667 MHz high speed clock support

■ Quad (open drain) differential output drivers

■ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4

■ Spread Aware™

■ 2.5V operation

■ 28-pin TSSOP package

®

Extended Data Rate (XDR™) clocking

Table 1. Device Comparison

CY24271 CY24272

SDA hold time = 300 ns
(SMBus compliant)

R

= 200Ω typical

RC

(Rambus standard drive)

SDA hold time = 0 ns

2

(I

C compliant)

RRC = 295Ω minimum
(Reduced output drive)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-42414 Rev. ** Revised November 9, 2007

[+] Feedback

CY24272

Figure 1. Pin Diagram - 28 Pin TSSOP

/BYPASS

REFCLKB

VDD

CLK0B

VSS

CLK2B

CLK3
CLK3B
VDD

VSS

CLK2

CLK0

VSS
CLK1
CLK1B
VDD

VDDP

ISET

VSSC

SDA

ID0
ID1

EN

SCL

VSSP

VSS

REFCLK

VDDC

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CY24272

Pinouts

Table 2. Pin Definition - 28 Pin TSSOP

Pin No. Name IO Description

1 VDDP PWR 2.5V power supply for phased lock loop (PLL)
2 VSSP GND Ground
3 ISET I Set clock driver current (external resistor)
4 VSS GND Ground
5 REFCLK I Reference clock input (connect to clock source)
6 REFCLKB I Complement of reference clock (connect to clock source)
7 VDDC PWR 2.5V power supply for core
8 VSSC GND Ground
9 SCL I SMBus clock (connect to SMBus)
10 SDA I SMBus data (connect to SMBus)
1 1 EN I Output Enable (CMOS signal)
12 ID0 I Device ID (CMOS signal)
13 ID1 I Device ID (CMOS signal)
14 /BYPASS I REFCLK bypassing PLL (CMOS signal)
15 VDD PWR Power supply for outputs
16 CLK3B O Complement clock output
17 CLK3 O Clock output
18 VSS GND Ground
19 CLK2B O Complement clock output
20 CLK2 O Clock output
21 VSS GND Ground
22 VDD PWR Power supply for outputs
23 CLK1B O Complement clock output
24 CLK1 O Clock output
25 VSS GND Ground
26 CLK0B O Complement clock output
27 CLK0 O Clock output
28 VDD PWR Power supply for outputs

Document Number: 001-42414 Rev. ** Page 2 of 13

[+] Feedback

CY24272

PLL Multiplier

Notes

1. Output frequencies shown in Table 3 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.

2. Default PLL multiplier at power up.

Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.

Default multiplier at power up is 4.

Table 3. PLL Multiplier Selection

Register

MULT2 MULT1 MULT0 REFCLK = 100 MHz

Frequency Multiplier

Output Frequency (MHz)

[1]

, REFSEL = 0 REFCLK = 133 MHz

0 0 0 3 300 400
001 4 400

[2]

0 1 0 5 500 667
0 1 1 6 600 –
1 0 0 Reserved – –
1 0 1 9/2 450 600
1 1 0 Reserved – –
1 1 1 15/4 375 500

Input Clock Signal

The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).

When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in

DC Operating Conditions on page 7 and AC Operating Condi­tions on page 8.

For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2 on page 6, provide a
reference voltage V
proper trip point of REFCLK. For the range of V

DC Operating Conditions on page 7, the outputs also meet the

at the REFCLKB pin. This determines the

TH

specified in

TH

Modes of Operation

The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.

Table 5 on page 4 shows selection from one to all four of the

outputs, the Outputs Disabled Mode (EN = low), and Bypass
Mode (EN = high, /BYPASS = low). There is an option reserved
for vendor test. Disabled outputs are set to High Z.

At power up, the SMBus registers default to the last entry in Table

6 on page 5. The value at RegTest is 0. The values at RegA,

RegB, RegC, and RegD are all ‘1’. Thus, all outputs are
controlled by the logic applied to EN and /BYPASS.

DC and AC Operating Conditions tables.

[1]

, REFSEL = 1

–

Table 4. SMBus Device Addresses for CY24272

XCG

Device Operation Five Most Significant Bits ID1 ID0 WR# / RD

0

1

2

3

Document Number: 001-42414 Rev. ** Page 3 of 13

Write D8
Read D9 1
Write DA
Read DB 1
Write DC
Read DD 1
Write DE
Read DF 1

Hex

Address

11011

8-bit SMBus Device Address Including Operation

00

01

10

11

0

0

0

0

[+] Feedback

CY24272

Notes

3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.

4. Default mode of operation is at power up.

Table 5. Modes of Operation for CY24272

EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B

L X X X X X X High Z High Z High Z High Z
H X 1 X X X X Reserved for Vendor Test
H L 0 X X X X REFCLK/

REFCLKB

[3]

REFCLK/

REFCLKB

REFCLK/

REFCLKB

REFCLK/

REFCLKB
H H 0 0 0 0 0 High Z High Z High Z High Z
H H 0 0 0 0 1 High Z High Z High Z CLK/CLKB
H H 0 0 0 1 0 High Z High Z CLK/CLKB High Z
H H 0 0 0 1 1 High Z High Z CLK/CLKB CLK/CLKB
H H 0 0 1 0 0 High Z CLK/CLKB High Z High Z
H H 0 0 1 0 1 High Z CLK/CLKB High Z CLK/CLKB
H H 0 0 1 1 0 High Z CLK/CLKB CLK/CLKB High Z
H H 0 0 1 1 1 High Z CLK/CLKB C LK/CLKB CLK/CLKB
H H 0 1 0 0 0 CLK/CLKB High Z High Z High Z
H H 0 1 0 0 1 CLK/CLKB High Z High Z CLK/CLKB
H H 0 1 0 1 0 CLK/CLKB High Z CLK/CLKB High Z
H H 0 1 0 1 1 CLK/CLKB High Z CLK/CLKB CLK/CLKB
H H 0 1 1 0 0 CLK/CLKB CLK/CLKB High Z High Z
H H 0 1 1 0 1 CLK/CLKB CLK/CLKB High Z CLK/CLKB
H H 0 1 1 1 0 CLK/CLKB CLK/CLKB CLK/CLKB High Z
HH 0

[4]

[4]

1

[4]

1

[4]

1

[4]

1

CLK/CLKB CLK/CLKB CLK/CLKB CLK/CLKB

Device ID and SMBus Device Address

The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address design ates a
write or read operation. Table 4 on page 3 shows the addresses
for four CY24272 devices on the same SMBus.

SMBus Protocol

The CY24272 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.

DC specifications are modified to Rambus standard to support

1.8, 2.5, and 3.3 volt devices. Time out detection and packet
error protocol SMBus features are not supported.

Hold time for SDA is reduced relative to the CY24271, so that it
is compatible with I

2

C.

SMBus Data Byte Definitions

Three data bytes are defined for the CY24272. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.

The definition of Byte 2 is sh own in Table 6, Table 7, and Table 8

on page 5. The upper five bits are the revision numbers of the

device and the lower three bits are the ID numbers assigned to
the vendor by Rambus.

Document Number: 001-42414 Rev. ** Page 4 of 13

[+] Feedback