W48S87-72
5
Serial Data Interface
The W48S87-72 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S87-72
initiali zes wit h defau lt regist er setti ngs, t heref ore the use of this
serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of de vice
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs
of the chipset. Clock device register changes are normally
made upon system init iali zati on, if any are r equire d. The int erface can also be us ed during system oper ation f or power management functions. Ta ble 2 summarizes the control functions
of the serial data interface.
Operation
Data is written to the W48S87-72 in ten bytes of eight bits
each. Bytes are written in the ord er shown in Table 3 .
Table 2. Serial Data Interface Control Functions Summary
Control Function Description Common Application
Clock Output Disa ble Any indivi dual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI
slot.
48-/24-MHz Cloc k Output
Frequency Selection
48-/24-MHz clock outputs can be set to 48 MHz or
24 MHz.
Provides flexibility in Super I/O and USB device selectio n.
CPU Clock Frequency
Selection
Provides CPU/PCI fr equency selections be yond the
60- and 66.6-MHz selections that are provided by
the SEL60/66 input pin. F req uency is changed i n a
smooth and controlled fashion.
For alternate CPU devices, and power management options. Smooth frequency transition allows CPU fr equency ch ange un der nor-
mal system operati on.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode All clock outputs toggle in relation with X1 input ,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved) Reserved fu nction for future device re vision or pro-
duction device testing.
No user application . Regist er bit must be wri t-
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence Byte Name Bit Sequence Byte Description
1 Slave Address 11010010 Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to hav e a specific slave
address for each potential receiver. The slave recei ver address for the
W48S87-72 is 11010010. Register setti ng will not be made if the Sl av e
Address is not correct ( or is for an alternate slave receiver).
2 Command
Code
Don’t Care Unused by the W48S87-72, the refore bit values are ignored (don’t c are).
This byte m ust be incl uded in the dat a write sequence to maintain pro per
byte allocati on. The Command Code Byt e is part of the standard serial
communication protocol and may be used when writing to another addressed slave receiver on the seri al data bus.
3 Byte Count Don’t Care Unused by the W48S87-72, the refore bit values are ignored (don’t c are).
This byte m ust be incl uded in the dat a write sequence to maintain pro per
byte allocation. The Byte Coun t Byte is part of the standard serial communication protocol and may be used when writing to anot her addressed slave receiver on the seri al data bus.
4 Data Byte 0 Refer to Table 4 The data bits in Data Bytes 0–7 set internal W48S87-72 registers that
control de vice operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted abov e. For descrip ti on
of bit control functions, ref er t o Ta ble 4 , Data Byte Serial Configuration
Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
11 Data Byte 7