Cypress W48S111-14G Datasheet

PRELIMINARY

Spread Spectrum Desktop /Notebook System

Frequenc y Ge ner ator

W48S111-14

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 28, 1999, rev. 0.7

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum Technology

• Reduces measured EMI by as much as 10 dB

•I

2

C programmable to 133 MHz

• T wo skew-controlled copi es of CPU output

• SEL100/66# selects CPU frequency (100 or 66.8 MHz)

• Seven copies of PCI output (synchronous w/CPU
output)

• One copy of 14.31818-MHz IOAPIC output

• One copy of 48-MHz USB output

• Selectable 24-/48-MHz clock is determined by resistor
straps on power-up

• One high-drive outpu t buffer that produces a copy of
the 14.318-MHz reference

• Isolated core VDD pin for noise reduction

Key Specifications

Supply Voltages:......... .. ............ ............ .... V

DDQ3

= 3.3V±5%

V

DDQ2

= 2.5V±5%

CPU Cy cl e to Cyc le Jitter: ............. .......... ... ......... ... ....200 ps

CPU, PCI Output Edge Rate:

.........................................≥

1 V/ns

CPU0: 1 O u tp u t Skew : .. ... .. .......... .. .......... ... ......... ... ....175 ps

PCI_ F, PCI1:6 Out p u t Skew: ...... .. .. .......... ... ......... ... .... 5 0 0 p s

CPU to PCI Skew: ........................1.5 to 4.0 ns (CPU Leads)

REF2X/SEL48#, SCLOCK, SDATA:. .. .. ..........250-kΩ pull-up

Note:

Internal pull-up resistors should not be relied upon for

setting I/O pins HIGH.

T able 1. Pin Selectable Frequency

SEL100/66# CPU(0:1) PCI

1 100 MHz 33.3 MHz
0 66.8 MHz 33.4 MHz

Pin ConfigurationBlock Diagram

VDDQ3
REF2X/SEL48#

VDDQ3
IOAPIC

CPU0
CPU1

PCI_F

XTAL

PLL Ref Freq

PLL 1

100/66#_SEL

X2

X1

VDDQ3

PCI1
PCI2

PCI3
PCI4

PCI5

48MHz
24/48MHz

PLL2

÷2/÷3

OSC

VDDQ2

PCI6
GND

GND

VDDQ3

GND

GND

I2C

SCLOCK

SDATA

LOGIC

X1
X2

GND

PCI_F

PCI1
PCI2
PCI3
PCI4

VDDQ3

PCI5
PCI6

VDDQ3

48MHz

24/48MHz

GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
SEL100/66#
GND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

W48S111-14

PRELIMINARYPRELIMI-

2

Pin Definitions

Pin Name

Pin
No.

Pin

Type Pin Description

CPU0:1 22, 21 O

CPU Clock Output s 0 thr ough 1:

These two CPU clo c ks run at a freque ncy s et by

SEL100/66#. Output voltage swin g is set by the voltage applied to VDDQ2.

PCI1:6
PCI_F

5, 6, 7, 8, 10,

11, 4

O

PCI Bus Clock Outputs 1 thro ugh 6 and PCI_F:

These sev en PCI cl ock outputs
run synchronousl y to t he CPU clock. Voltage sw ing is set by the power connection
to VDDQ3.

IOAPIC 24 O

I/O APIC Clock Output:

Provides 14. 318-MHz fi xed fr equ ency. The output voltage

swing is set by the power connection to VDDQ2.

48MHz 13 O

48-MHz O u tput:

Fixed 48-MHz USB clock. Output voltage swing is controlled by

voltage applied to VDDQ3.

24/48MHz 14 O

24-MHz or 48-MHz Output:

Frequency is set by the state of pin 27 on power-up.

REF2X/SEL48# 27 I/O

I/O Dual-Function REF2X and SEL48# pin:

Upon power-up, the state of SEL48#

is latched. The initial state is set by eit her a 10K resistor to GND or to V

DD

. A 10K

resistor to GND causes pin 14 to output 48 MHz. If the pin is str apped to V

DD

, pin
14 will output 24 MHz. Afte r 2 ms , the pin becomes a high -drive out put that produces
a copy of 14.318 MHz.

SEL100/66# 16 I

Frequency Selecti on Input:

Selects CPU clock frequency as shown in Table 1 on

page 1.

SDATA 18 I/O

I

2

C Data Pin:

Data should be presented to thi s input as described in the I

2

C section

of this data sheet. Internal 250-kΩ pull-up resistor.

SCLOCK 17 I

I

2

C clock Pin:

The I

2

C data clock shou ld be presen ted to this input as described in

the I

2

C section of this data shee t.

X1 1 I

Crystal Connection or External Reference Frequency Input:

Connec t to eit h er

a 14.318-MHz crystal or other reference signal.

X2 2 I

Crystal Connection:

An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

VDDQ3 9, 12, 20, 26 P

Po wer Connectio n:

Pow er suppl y for core logic and PLL circ uitry, PCI, 48/24MHz,

and Reference output buffers. Connect to 3.3V supply.

VDDQ2 23, 25 P

Po we r Connection:

Power supply for IOAPIC and CPU output buffers. Connect to

2.5V supply.

GND 3, 15, 19, 28 G

Ground Connection s:

Connect all ground pins to the common system ground

plane.

W48S111-14

PRELIMINARYPRELIMI-

3

Functional Description

I/O Pin Operation

Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic i nput, a llo wing the determinat ion of assigne d de vic e
functions . A short time after pow er-up , the logic state of th e pin
is latched and the pin becomes a clock output. This feature
reduces devi ce pin count by combi ning clock out puts with input
select pins .

An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V

DD

. Connection to ground sets a

latch to “0,” connection to V

DD

sets a latch to “1.” Fig ure 1 an d
Figure 2 show two suggested methods for strapping resistor
connections.

Upon W48S111-14 power-up, the first 2 ms of operation is
used for input logic selection. During this period, the Refer­ence clock output buffer is three-stated, allowing the output
strapping resistor on the l/O pin to pull the pin and its associ­ated capaci tiv e cloc k load t o either a l ogic HI GH or L O W state .
At the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is then latched. Next the output buffer

is enabled, which converts the l/O pin into an operating clock
output. The 2-ms timer is started when V

DD

reaches 2.0V. The

input bit can only be reset b y turning V

DD

off and then bac k on

again.
It should be noted tha t the stra ppi ng resi stor has no si gnifi cant

effect on clock output signal integrity. The drive impedance of
clock output is 40Ω (nominal) which is minimally affected by
the 10-kΩ strap to ground or V

DD

. As with th e se r ie s termi n a­tion resistor, the output strap ping resi stor shou ld be placed as
close to the l/O pin as possible in order to keep the intercon­necting trace short. The trace from the resistor to ground or
V

DD

should be kept less than two inches in length to prevent

system noise coupli ng duri ng input logic sampling.
When the clock output is enabled following the 2-ms input pe-

riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that V

DD

has stabilized. If VDD has not yet reached
full value , output frequency initi ally ma y be belo w target b ut will
increase to target once V

DD

voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.

Power-on
Reset
Timer

Output Three-state

Data

Latch

Hold

QD

W48S111-14

V

DD

Clock Load

10 k

Ω

Output
Buffer

(Load Option 1)

10 k

Ω

(Load Option 0)

Output
Low

Output Strapping Resistor

Series Termination Resistor

Figure 1. Input Logic Selection Through Resistor Load Option

Power-on
Reset
Timer

Output Thr ee- s tate

Data

Latch

Hold

QD

W48S111-14

V

DD

Clock Load

R

10 k

Ω

Output
Buffer

Output
Low

Output Strapping Resistor

Series Termination Resistor

Jumper Options

Resistor Value R

Figure 2. Input Logic Selection Through Jumper Option

W48S111-14

PRELIMINARYPRELIMI-

4

Serial Data Interface

The W48S111-1 4 features a two-pin, serial data interface t hat
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S111-14
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica­tions, SDATA and SCLOCK are typically driven by two logic

outputs of the chipset. Clock device register changes are nor­mally made upon system initialization, if required. The inter­face can also be us ed during system oper ation f or power man­agement functions. Table 2 summarizes the control functions
of the serial data interface.

Operation

Data is written to the W48S111-14 in ten bytes of eight bits
each. Bytes are written in the or der shown in Table 3.

T able 2. Serial Data Interface Control Func ti ons Sum mary

Control Function Description Common Application

Clock Output Disable Any indivi dual clock output(s) can be disabled. Dis-

abled outputs ar e actively held LO W.

Unused outputs are di sabled to reduce EMI
and system power. Examples are clock out­puts to unused PCI slots.

CPU Clock Fr equency
Selection

Provides CPU/PCI fr equency selections be yond the
100- and 66.8-MHz sel ecti ons t hat ar e provi ded by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.

For alternate microprocessors and power
management options . Smooth freque ncy tran­sition allows CPU frequency change under

normal system operation.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
T es t Mode All clock outputs t oggle i n rela tion t o X1 inp ut, i nter-

nal PLL is bypassed. Refer to Table 4.

Production PCB testing.

(Reserved) Reserved functio n for future de vice revisi on or pro-

duc tion devi c e t es t ing.

No user application . Regist er bit must be wri t-

ten as 0.

Table 3. Byte Writing Sequence

Byte

Sequence Byte Name Bit Sequence Byte Description

1 Slave Address 11010010 Commands the W48S1 11-14 to accept the bits in Data Bytes 3–6 for

internal registe r configurati on. Since other de vices may exist on the sam e
common serial data b us , it is neces sary to ha v e a sp ecific sl a ve a ddre ss
for each potent ial receiver. The slave receiver address for the
W48S111-14 is 11010010. Regi ster setting wil l not be made i f the Slav e
Address is not correct (or is for an alternate sla ve receiver).

2 Command

Code

Don’t Care Unused by the W48S111 -14, therefore bit values are ignored (“don’t

care”). This by te must be include d in the data write seq uence to mainta in
proper byt e allocation. The Command Code Byte is part of the sta ndard
serial communicat ion pr otocol and ma y be used whe n writin g to anoth er
addressed slave receiver on the serial data bus.

3 Byte Count Don’t Care Unused by the W48S111 -14, therefore bit values are ignored (“don’t

care”). This by te must be include d in the data write seq uence to mainta in
proper byt e all ocatio n. The B yte Count Byt e is part of t he stan dard seri al
communication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.
4 Data Byte 0 Don’t Care Refer to Cypress SDRAM drivers.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3 Refer to Table 4 The data bits in these bytes set internal W48S111-14 registers that con-

trol de vice operati on. The data bits are only accepted when the Address

Byte bit sequence is 11010010, as noted above. For description of bit

control functions, refer to Table 4, Data Byte Serial Configuration Map.

8 Data Byte 4
9 Data Byte 5

10 Data Byte 6