Cypress W48S101-04H Datasheet

PRELIMINARY

Spread Spectrum Motherboard Frequen cy Ge ner ato r

W48S101-04

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spec t r u m techno logy

•

I

2

C™ interface

•

Four copies of CPU output

•

Eight copies of PCI cloc k ( synchr onous w/CPU output)

•

T w o copies of 14.318-MHz IO APIC output

•

One copy of 48-MHz USB output

•

Selectable 24- /48-MHz clock-through-resistor
strapping

•

Three buffered copies of 14.318-MHz reference input

•

Input is a 14.318-MHz XTAL or reference signal

•

Selectable 100-M H z or 66-MHz CPU outputs

• Power man agem ent control input pins

• T est mode and out put three- state t hrou gh I

2

C interface

Key Specifications

Supply Voltages:......... .. ............ ............ .... V

DDQ3

= 3.3V±5%

V

DDQ2

= 2.5V±5%

CPU Cy cl e to Cyc le Jitter:............ .. .......... ... .. .......... .. ..2 0 0 p s

CPU0: 3 O u tp u t Skew : .. ... .. .......... .. ... .......... .. ..............175 ps

PCI_ F, PCI1:7 Out p u t Skew: ...... .. .. .......... ... ................500 ps

CPU to PCI Output Skew: ............1.5 to 4.0 ns (CPU Leads)

Logic inputs and REF0/SEL48# have 250K pull-up resistors
except SEL100/66#.

I2C is a trademark of Philips Corporation.

T able 1. Pin Selectable Frequency

SEL

100/66# CPU (MHz)

PCI

(MHz) SPREAD#=0

0 66.8 33.4 ±0.5% Center
1 100 33.3 ±0.5% Center

Pin ConfigurationBlock Diagram

VDDREF
REF0/SEL48#

VDDAPIC
APIC0

CPU0
CPU1

CPU2
CPU3

PCI_F

XTAL

PLL Ref Freq

PLL 1

100/66#_SEL

X2

X1

REF1

VDDPCI0

Stop

Clock

Control

Stop

Clock

Control

PCI1

PWR_DWN#

Power
Down
Control

PCI2
PCI3

PCI4
PCI5

48MHz
24/48MHz

PLL2

÷2/÷3

OSC

REF2

VDDCPU0

PCI_STOP#

CPU_STOP#

PCI6
PCI7

GNDPCI1

GND48MHz

VDD48MHz

GNDREF

APIC1

GNDAPIC

GNDCORE0/1

VDDCORE0/1

VDDPCI1

GNDPCI0

GNDCPU1

GNDCPU0
VDDCPU1

SPREAD#

I2C

SDATA

Logic

SCLK

REF0/SEL48#

REF1

GNDREF

X1
X2

GNDPCI0

PCICLK_F

PCI1

VDDPCI0

PCI2
PCI3

GNDPCI1

PCI4
PCI5

VDDPCI1

PCI6
PCI7

GNDPCI2

VDDCORE0

GNDCORE0

VDD48MHz

48MHz

24/48MHz

GND48MHz

VDDREF
REF2
VDDAPIC
APIC0
APIC1
GNDAPIC
NC
VDDCPU0
CPU0
CPU1
GNDCPU0
VDDCPU1
CPUCLK2
CPUCLK3
GNDCPU1
VDDCORE1
GNDCORE1
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SDATA
SCLK
SEL100/66#

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Note:

1. Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.

[1]

W48S101-04

PRELIMINARY

2

Pin Definitions

Pin Name Pin No. Pin Type Pin Description

CPU0:3 40, 39, 36,

35

O

CPU Clock Output s 0 through 3:

These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage sw ing is controll ed by voltage applied
to VDDQ2.

PCI1:7 8, 10, 11,

13, 14, 16,

17

O

PCI Bus Clock Outputs 1 thr ough 7:

These sev en PCI cloc k outputs are control led
by the PCI_STOP# cont rol pin. Output v oltage swing is cont rolled by v oltage applied
to VDDQ3.

PCI_F 7 O

Fixed PCI Clock Output:

Unlike PCI 1:7 o utputs , t his outp ut i s not contr olled b y the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.

CPU_STOP# 30 I

CPU_STOP# Input:

When brought LO W, clock outputs CPU0:3 are stop ped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outpu ts CPU0:3 st art beginning wi th a ful l cloc k cycle ( 2–3 CPU clock latency).

PCI_STOP# 31 I

PCI_STOP# Input:

The PCI_STOP# input enables t he PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.

SPREAD# 28 I

SPREAD# Input:

When brought LO W th is pin ac tiv at es Sp read Spect rum cloc king.

APIC0:1 45, 44 O

I/O APIC C lock O utputs:

Provides 14. 318-MHz fixe d frequency . The out put volt age

swing is controlled by VDDQ2.

48MHz 22 O

48-MHz Output:

Fixed cloc k outp uts at 48 MHz. Output vol ta ge swi ng is cont ro lled

by voltage applied to VDDQ3.

24/48MHz 23 O

24-MHz or 48-MHz Out put:

24-MHz output when pin 1 is strapped through 10-kΩ
resistor to VDDQ3. 48-MHz output when pin 1 is strapped t hrough 10-k Ω resistor to
GND.

REF0/SEL48# 1 I/O

I/O Dual Function REF0 and SEL48# pin:

During power on, SEL48# input will be
latched, which will set pin 23 to out put 24 MHz or 48 MHz. It then reverts to REF0
fixed output.

REF1:2 2, 47 O

Fixed 14.318-MHz Outputs 1 through 2:

Used for various system applicat ions.

Output voltage swing is controlled by voltage appl ied to VDDQ3.

SEL100/66# 25 I

Frequency Selection Input:

Selects power -up default CPU clock frequency as

shown in Tabl e 1 on page 1.

SCLK 26 I Clock pin for I

2

C circuitry.

SDATA 27 I/O Data pin for I

2

C circuitry.

X1 4 I

Crystal Connection or External Reference Frequency Input:

This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency i nput.

X2 5 I

Crystal Connection:

An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

PWR_DWN# 29 I

Power Down Contr ol:

When this input is LO W , de vice goe s into a lo w-pow er stand­by condition. All outputs are actively held LOW while in power-down. CPU and PCI
clock output s are stopped LOW after com pleting a full clock cycle (2–3 CPU clock
cycle latency ). When br ought HI GH, CPU , SDRAM and PCI output s start wi th a fu ll
clock cycle at full operating frequency (3 ms maximum latency).

VDDQ3 9, 15, 19,

21, 33, 48

P

Power Connecti on:

Connect to 3.3V supply.

VDDQ2 46, 41, 37 P

Power Connecti on:

Pow er supply for API C0:1 and CPU0:3 output buf fers. Connect

to 2.5V.

GND 3, 6, 12, 18,

20, 24, 32,

34, 38, 43

G

Ground Connections:

Connect all ground pins to the common system ground

plane.

W48S101-04

PRELIMINARY

3

Overview

The W48S101-04, a motherboard clock synthesizer, can pro­vide eith er a 2.5V or 3.3 V CPU clock swing, making it suit able
for a variety of CPU options. A fix ed 48-MHz clock is provided
for oth er syst em func tions . The W48S101 -04 s upports sprea d
spectrum clocking for reduced EMI.

Functional Description

I/O Pin Operation

Pin 1 is a dual-purpose l/O pin. Upon po wer-up this pi n acts as
a logic input, allowing the determination of assigned device
functions . A short time after pow er-up , the logic state of th e pin
is latched and the pin becomes a clock output. This feature
reduces devi ce pin count by combi ning clock out puts with input
select pins .

An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V

DD

. Connection to ground sets a

latch to “0,” connection to V

DD

sets a latch to “1.” Fig ure 1 an d
Figure 2 show two suggested methods for strapping resistor
connections.

Upon W48S101-04 power-up, the first 2 ms of operation is
used for input logic selection. During this period, the Refer­ence clock output buffer is three-stated, allowing the output

strapping resistor on the l/O pin to pull the pin and its associ­ated capacit iv e cloc k load to eith er a l ogic HIGH or LO W stat e .
At the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is then latched. Next the output buffer
is enabled, which converts the l/O pin into an operating clock
output. The 2-ms timer is started when V

DD

reaches 2.0V. The

input bit can only be reset b y turning V

DD

off and then bac k on

again.
It should be noted tha t the stra ppi ng resi stor has no si gnifi cant

effect on clock output signal integri ty. The drive impedance of
clock output is 40Ω (nominal) which is minimally affected by
the 10-kΩ strap to ground or V

DD

. As with th e se r ie s termi n a­tion resistor, the output strapping resistor should be pla ced as
close to the l/O pin as possible in order to keep the intercon­necting trace short. The trace from the resistor to ground or
V

DD

should be kept less than two inches in length to prevent

system noise coupli ng duri ng input logic sampling.
When the clock output is enabled fo ll owing the 2-ms input pe-

riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that V

DD

has stabilized. If VDD has not yet reached
full value , output frequency initi ally ma y be belo w target b ut will
increase to target once V

DD

voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.

Power-on
Reset
Timer

Outpu t Three-state

Data

Latch

Hold

QD

W48S101-04

V

DD

Clock Load

10 k

Ω

Output
Buffer

(Load Option 1)

10 k

Ω

(Load Option 0)

Output
Low

Output Strapping Resistor

Series Termination Resistor

Figure 1. Input Logic Selection Through Resistor Load Option

Power-on
Reset
Timer

Output Three-state

Data

Latch

Hold

QD

W48S101-04

V

DD

Clock Load

R

10 k

Ω

Output
Buffer

Output
Low

Output Strapping Resistor

Series Termination Resistor

Jumper Options

Resisto r Value R

Figure 2. Input Logic Selection Through Jumper Option

W48S101-04

PRELIMINARY

4

Spread Spectrum Clock Generation

The benefits of using Spr ead Spectrum Clock Generation are
depicted in Figure 3. An EMI emission profile of a clock har­monic is shown.

Contrast the typical clock EMI with the Cy press Spread Spec­trum Clock Generation. Notice the spike in the typical clock.
This spike can mak e system s fa il quasi -peak EM I testing . The
FCC and other regulatory agencies test for peak emissions.
With the Cypress clock, the peak energy is much lower (at
least 8 dB) because the energy is spread out across a wider
bandwidth.

Figure 3. Typical Clock and SSCG Comparison

SSFTG Typical Clock

Frequ en cy S p an (M H z)

-SS% +SS%

Amplitude (dB )

5dB/div

MAX (+0.5%)

MIN (–0.5%)

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

FREQUENCY

Figure 4. Typical Modulation Profile