Cypress W42C32-05M Datasheet

Spread Spectrum Frequency Timing Generator

W42C32-05

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 28, 1999, rev. **

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spec t r u m techno logy

• Generates a spread spectrum timing signal

• Reduces measured EMI by as much as 12 dB

• Integrated loop filter components

• Requires a single lo w -cost fundament al crystal (or
other frequency reference) for proper operation

• Special spread spectrum control functions

• Low-power CMOS design

• Av ailable in 16-pin SOIC package, (300 mil)

Overview

The W42C32 modulat es the output of a single PLL in order to
‘spread’ the bandwidth of a synthesized clock and, more im­portantly, decrease the peak amplitudes of its fundamental
harmonics. Since peak amplitudes are reduced, the radiated
electromagnet ic e missio ns o f the W42C32- 05 ar e s ignif icant ly
lower t han the typical narrow band signal produced by oscilla­tors and most frequency generators. Lowering a signal’s am­plitude by increasing its bandwidth is a method of reducing
EMI called ‘spread spectrum frequency timing generation’.
This patented techni que not only reduces the emis sions of the
primary clock, bu t also impact s ev ery signal synchroniz ed to it.

Key Specifications

Cycle-to-Cycle Jitter ....................................................250 ps

45/55 Duty Cycle.................................... approximately 1.4V

Selectable Frequency spread
2 ns rise/fall time 0.4V to 2.0V, 3.3V supply
2 ns rise/fall time 0.8V to 2.4V, 5.0V supply

T able 1. Frequency Spread Selection

W42C32-05

FS2 FS1 FS0

REFOUT

(MHz)

CLKOUT

(MHz)

VDD

(V)

0 0 0 22.1148 44.2296 ±

2.5%

5.0

0 0 1 22.1148 44.2296

±1.5%

5.0

0 1 0 14.7456 29.4912 ±

2.5%

5.0

0 1 1 18.432 18.432 ± 2.5% 5 .0
1 0 0 14.318 66.66 – 2% 3.3
1 0 1 Reserved 3.3
1 1 0 14.318 100 – 2% 3.3
1 1 1 Reserved 3.3

Pin Configuration

W42C32-05

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

PD#

X1
X2

GND

AGND

FS0

TEST

CLKOUT

REFOUT
FS2
FS1
SSON#
RESET
VDD
AVDD
REFEN#

SOIC

W42C32-05

2

Pin Definitions

[1]

Pin Name Pin No.

Pin

T ype Pin Description

CLKOUT 8 O

Output Modulated Frequency

: Frequency is set using FS0:2 (refer to Table 1).

REFOUT 16 O

Reference Output:

A buffered version of the input frequency.

X1 2 I

Crystal Connection or External Reference Frequency Input :

This pin has dual func­tions. It c an b e used a s ei ther an e xt ernal crystal con nectio n, or as an e xt ernal ref er enc e
frequency input.

X2 3 I

Crystal Connection:

If using an external reference, this pin must be left unconnecte d.

SSON# 13 I

Spread Spe ctrum Contro l (active LO W):

Pulling this input s ignal HIGH turns the internal

modulating wa veform off. This pin has an inte rnal pull-down resistor.

FS0 6 I

Frequency Select ion Bit 0:

This pin selects t he frequency and spreadi ng characteri stics.

Refer to Tabl e 1 . This pin has an internal pull-up resistor.

FS1 14 I

Frequency Select ion Bit 1:

This pin selects t he frequency and spreadi ng characteri stics.

Refer to Tabl e 1 . This pin has an internal pull-up resistor.

FS2 15 I

Frequency Select ion Bit 2:

This pin selects t he frequency and spreadi ng characteri stics.

Refer to Tabl e 1 (note the V

DD

specific ation). This pin has an internal pull-up resistor.

PD# 1 I

Po wer-down (active LOW):

Enabling power-down reduces current consumption and

disables the clock outputs. This pin has an internal pull-up resistor.

REFEN# 9 I

Reference Cloc k Selection Input:

Pulling this signal LOW turns the REFOUT cloc k

output on. This pin has an inter nal pull-up resistor.

RESET 12 I

Reset:

A reset starts the spread spec trum modulating frequency at the beginnin g point
of the modulation pr of ile . This pin has an i nternal pull -do wn resi stor. T o reset the spread
spectrum modulating frequency, pull thi s pin from LO W to HIGH.

VDD 11 P

Po wer Connection:

Connected to either 3.3V or 5.0V po wer supply . V

DD

and A VDD must

be the same voltage le vel.

AVDD 10 P

Analog Power Connection:

Connected to ei ther 3.3V or 5.0V power supply. V

DD

and

AV

DD

must be the same voltage level.

GND 4 G

Ground Connection :

Connect to the common system ground plane.

AGND 5 G

Analog Ground Connection:

Connect to the common system ground plane.

TEST 7 I

Three-state Input:

Pulling this input pin and REFEN# pin HI GH, CLKOUT will be

three-stated. This pin has an internal pull-down resistor.

[2]

Notes:

1. Pull-up resistors not CMOS level.

2. Pulling PD# and REFEN# input pins HIGH, REFOUT will be three-stated.

W42C32-05

3

Functional Description

The W42C32-05 uses a phase-locked loop (PLL) to multiply
the frequency of a low-cost, low-frequency cr ystal up to the
desired cl ock f req uency. The basic c ircuit top olog y is s ho wn i n
Figure 1. An on- chip crystal driver causes the crystal to osci l­late at its fundamental. The resulting reference signal is divid­ed by Q and fed to the phase detector. The VCO output is
divided by P and also fed back to the phase detect or . The PLL
will force the frequency of the VCO output signal to change
until the divi ded output signal and the di vided re f erenc e signal
match at the phase detector input. The output frequency is
then equal to the ratio of P/Q times the reference frequency.
The unique feature of the Spr ead Spec trum F requ ency Timin g
Generator is that a modulating waveform is superimposed at
the input to the VCO . Thi s causes t he VCO ou tput to b e sl ow ly
swept across a predetermined frequency band.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has little impact on system performance.

Frequency Selecti on W it h SSFTG

In Spread Spectr um frequency timing generat ion, EMI reduc­tion depends on the shape, modulation percentage, and fre­quency of the modulating waveform. While the shape and fre­quency of the modulating waveform in the W42C32 are fixed,
the modulati on percentage may be varied.

Using frequency select bits (FS2:0 pins), various spreading
percentages for different input frequency ranges can be cho­sen. For example, refer to the W42C32-05 in Ta b l e 1. If the
logic level on FS2:0 = 000, then an input reference frequency
between 14 and 24 MHz will produce an output frequency at
twice the reference frequency with a spread of ±2.5%.

A larger spreading per centage improves EMI reduction. How­ever, large spread percentages may either exceed system
maximum frequ ency ra tings or lo wer the a v erag e fr equency t o
a point where performance is affected. For these reasons,
spreading percentages between ±0.875% and ±2.5% are
most common.

Additional Features of the W42C32-05

A RESET pin is available to aid in applications which have
multiple PLL clock generators. When a reset is issued, the
modulation profile shown in Figure 3 is reset to its starting
point. This feature is necessary for applications in which two
spread spectrum systems must synchr onize with each other.

The REFOUT out pin provi des a buffered version of the input
clock frequency.

The SSON# pin disables the spread spectr um function when
set to logic HIGH. Otherwi se, an internal pull-down resistor
leaves this feature enab led.

The PD# pin reduces power consumption and disables the
clock output s when set to logic LOW. Otherwise, an internal
pull-up resistor places the W42C32-05 into normal mode .

Figure 1. System Block Diagra m (Co ncept, not actual impl eme ntat ion)

XTAL

Freq.

Phase

Modulating

VCO

Post

CLKOUT

Detector

Charge

Pump

Waveform

DividersDivider

Feedback

Divider

PLL

GND

V

DD

X1

X2

Crystal load
capacitors
as needed

Σ

Q

P