Cypress W40S01-04 Datasheet
W40S01-04
SDRAM Buffer - 4 DIMM
Features
• Eighteen skew contr ol led CMOS outputs (SDRAM0:17)
• Supports four SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel®’s 440BX chip set
2
•I
C serial configuration interface
• Output skew between any two outputs is less than
250 ps
• 1 to 5 ns propagati on delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 48-pin SSOP
(Small Shrink Outline Package)
Overview
The Cypress W40S01-04 is a low-voltage, eighteen-output
signal buffer. Output buffer impedance is approximately 15
which is idea l for driving SD RA M DIM M s .
Block Diagram
SDATA
SCLOCK
BUF_IN
Serial Port
Device Control
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
Key Specifications
Supply Voltages :......... .......... .. .......... .. ...... V
Operating Temperatur e:.... .. .......... .......... ......... . 0° C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: ...................................V
Input Frequency:...............................................0 to 133 MHz
BUF_IN to SDRAM0:17 Propagation Del ay:......1.0 to 5.0 ns
Output Edge Rate:............................................ ......>
Output Skew:............................................................ ±250 ps
Output Duty Cycle : .... ......... .......... .. ......... 4 5 /5 5 % wo r st ca s e
Output Impedance:.................... ....................15 ohms typi cal
Output Type:................................................CMOS rail-to-rail
Part to Part Skew:........................................................700 ps
Ω
DDQ3
Pin Configuration
SSOP
NC
NC
VDDQ3
SDRAM0
SDRAM1
GND
VDDQ3
SDRAM2
SDRAM3
GND
BUF_IN
VDDQ3
SDRAM4
SDRAM5
GND
VDDQ3
SDRAM6
SDRAM7
GND
VDDQ3
SDRAM16
GND
VDDQ3
SDATA
Note:
1. Internal pull-up resistor of 250K on SDATA , SCLOCK, and OE
inputs (not CMOS level).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
[1]
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
= 3.3V±5%
+ 0.5V
DDQ3
1.5 V/ns
NC
NC
VDDQ3
SDRAM15
SDRAM14
GND
VDDQ3
SDRAM13
SDRAM12
GND
[1]
OE
VDDQ3
SDRAM11
SDRAM10
GND
VDDQ3
SDRAM9
SDRAM8
GND
VDDQ3
SDRAM17
GND
GND
SCLOCK
[1]
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 20, 2000, rev. **
Pin Definitions
W40S01-04
Pin Name
No.
SDRAM0:17 4, 5, 8, 9,
Pin
Pin
Type Pin Description
O
13, 14, 17,
18, 21, 28,
31, 32, 35,
36, 40, 41,
44, 45
BUF_IN 11 I
SDATA 24 I/O
SCLOCK 25 I
VDDQ3 3, 7, 12, 16,
P
20, 23, 29,
33, 37, 42,
46
GND 6, 10, 15,
G
19, 22, 26,
27, 30, 34,
39, 43
OE 38 I
NC 1, 2, 47, 48 -
SDRAM Outputs:
Provides buffered copy of BUF_IN. The prop agation delay from a
rising input edge to a rising outp ut edge is 1 to 5 ns. All outputs are skew control led
to within ± 250 ps of each other.
Clock Input:
2
I
C Data Input:
This clock input has an input threshold voltage of 1.5V (typ).
Data should be pr esented to t his inpu t as described i n the I
2
C section
of this data sheet. Internal 250-kΩ pull-up resistor.
2
C clock In put:
I
2
the I
C section of this data sheet. Internal 250-kΩ pull-up resistor.
Power Connection:
2
The I
C data clock shou ld be pr ese nted to this input as de scribed in
Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection:
Output Enable:
No Connect:
Do not connect.
Connect all groun d pins to the common system ground plane.
Internal 250-kΩ pull-up resistor . Three-states outpu ts when LOW.
2
W40S01-04
Functional Description
Output Control Pins
Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in ph ase with BUF_IN but ar e phase del a yed by 1
to 5 ns. Outputs can also be controlled via the I
Output Drivers
The W40S01-04 output buffers are CMOS type which deliver
a rail-to-rail (GND to V
Table 1. Byte Writing Sequence
Byte
Sequence Byte Name Bit Sequence Byte Description
1 Slave Address 11010010 Commands the W40S01-04 t o accept t he bits in Data Byt es 0-6 for inter-
2 Command
Code
3 Byte Count Don’t Care Unused by the W40S0 1-04 , ther ef or e bit va lue s are i gnored (don ’t car e).
4 Data Byte 0 Refer to Table 2 The data bit s in thes e bytes set int ernal W40S01-04 r egister s that co ntrol
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3 Don’t Care Refer to Cypress clock drivers.
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
) output voltage swing into a nominal
DD
Don’t Care Unused by the W40S0 1-04 , ther ef ore bi t va lues ar e ign ored (don’t care).
2
C interface.
nal register configuration. Since other devices may exist on the same
common serial data b us , it is neces sary to have a specific slave addr ess
for each potential receiver. The slav e receiver address for the
W40S01-04 is 11010010. Regi ster setting will not be made if t he Slave
Address is not correct (or is for an alternat e slave rece iver).
This byte must be included i n the data write sequen ce to maintain pro per
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when wri ting to another addres sed slave r e ceiver on the serial da ta bus.
This byte must be included i n the data write sequen ce to maintain pro per
byte allocation. The Byte Count Byte is part of the standard serial communication pr otocol an d may be used when writ ing to another address ed
slave receiver on the serial data bus.
device oper ation. The data bits are only accepted when the Address Byte
bit sequence i s 11010010, as noted abov e. For description of bit cont rol
functio ns, refer to Table 2, Data Byte Serial Configuration Map.
capacitiv e load . Th us, o utput signal ing i s both TT L and CMOS
level compatibl e. Nominal output buff er imp edance is 15 ohms .
Operation
Data is written to the W40S01-04 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1 .
3
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