Cypress W199H Datasheet

PRELIMINARY

Spread Spectrum FTG for VIA Apollo Pro-133

W199

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 19, 1999, rev. **

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum Technology

• Single-chi p system frequency synthesizer f or VIA
Apollo Pro-133

• T wo copies of CPU output

• Six copies of PCI output

• One 48-MHz output for USB

• One 24-MHz output for SI O

• T wo buffered reference outputs

• One IOAPIC output

• 13 SDRAM outputs provide support for 3 DIMMs

• Supports frequencies up to 150 MHz

•I

2

C™ interface for programming

• Power man agem ent control inputs

• Available in 48-pin SSOP

Key Specific ati o n s

CPU Cycle-to-Cycle Jitter: .........................................250 ps

CPU to CPU Output Skew: ............... ................. ........ 175 ps

PCI to PCI Output Skew:............................................ 500 ps

V

DDQ3

: .................................................................... 3.3V±5%

V

DDQ2

: .................................................................... 2.5V±5%

SDRAMIN to SDRAM0 :1 1 Delay : ..... ... .. ................3.7 ns typ.

SDRAM0:11 (leads) to SDRAM_F Ske w :..............0.4 ns typ.

T able 1. Mode Input Table

Mode Pin 2

0PCI_STOP#
1REF0

T able 2. Pin Selectable Frequency

Input Address

CPU_F,

CPU1 (MHz)

PCI_F, 1:5

(MHz)FS3 FS2 FS1 FS0

1 1 1 1 133.3 33.3 (CPU/4)
1 1 1 0 124 31 (CPU/4)
1 1 0 1 150 37.5 (CPU/4)
1 1 0 0 140 35 (CPU/4)
1 0 1 1 105 35 (CPU/3)
1 0 1 0 110 36.7 (CPU/3)
1 0 0 1 115 38.3 (CPU/3)
1 0 0 0 120 40 (CPU/3)
0 1 1 1 100 33.3 (CPU/3)
0 1 1 0 133.3 44.43 (CPU/3)
0 1 0 1 112 37.3 (CPU/3)
0 1 0 0 103 34.3 (CPU/3)
0 0 1 1 66.8 33.4 (CPU/2)
0 0 1 0 83.3 41.7 (CPU/2)
0 0 0 1 75 37.5 (CPU/2)
0 0 0 0 124 41.3 (CPU/3)

I2C is a trademark of Philips Corporation.

Note:

1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.

Logic Block Diagram

Pin Configuration

[1]

VDDQ3

REF0/(PCI_STOP#)

GND

X1
X2

VDDQ3

PCI_F/MODE

PCI1/FS3

GND
PCI2
PCI3
PCI4
PCI5

VDDQ3

SDRAMIN

GND
SDRAM11
SDRAM10

VDDQ3
SDRAM9
SDRAM8

GND

SDATA

SCLK

W199

VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

I2C

{

VDDQ3
REF0/(PCI_STOP#)

VDDQ2

CPU1

PCI_F/MODE

XTAL

PLL Ref Freq

PLL 1

X2

X1

REF1/FS2

VDDQ3

Stop

Clock

Control

Stop

Clock

Control

PCI2
PCI3
PCI4

48MHz/FS0

24MHz/FS1

PLL2

÷2,3, 4

OSC

VDDQ2

CLK_STOP#

VDDQ3

IOAPIC

PCI5

I2C

SDATA

Logic

SCLK

I/O Pin
Control

SDRAM0:11

SDRAMIN

12

VDDQ3

PCI1/FS3

Stop

Clock

Control

Stop

Clock

Control

CPU_F

÷2

SDRAM_F

W199

PRELIMINARY

2

Pin Definitions

Pin Name Pin No.

Pin

T ype Pin Description

CPU_F 44 O

Free-running CPU Clock :

Output voltage swing is controlled by the voltage applied to

VDDQ2. See Tables 2 and 6 for detaile d frequency information.

CPU1 43 O

CPU Clock Output 1:

This CPU clock output is controlled by the CLK_STOP# control

pin. Output voltage swing is controlled by voltage appli ed to VDDQ2.

PCI2:5 10, 11, 12, 13O

PCI Clock Outputs 2 through 5:

These four PCI clock outputs are controll ed by the

PCI_STOP# contr ol pin. Output vol tage swing is cont rolled by vol tage applied to VDDQ3.

PCI1/FS3 8 I/O

Fixed PCI Clock Outpu t:

As an output. f requency is set b y the FS0 :3 inp uts or t hrough
serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP#
input. When an input, latches data sel ecting the frequency of the CPU and PCI ou tputs.

PCI_F/MODE 7 I/O

Fixed PCI Clock Outpu t:

As an output, f requency is set b y the FS0 :3 inp uts or t hrough
serial input int erf a ce, se e Tables 2 and 6. Thi s outpu t is no t aff ect ed b y the PCI _ST OP#
input. When an input, sets function of pin 2.

CLK_STOP# 41 I

CLK_STOP# Input:

When brought LOW, af f ect ed cloc k output s are s top ped LOW aft er
completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected
clock output s start, beginning with a full cloc k cycle (2–3 CPU clock lat ency).

IOAPIC 47 O

IOAPIC Cloc k Output:

Provides 14.318-MHz fi xed f requency. The output volta ge swing

is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.

48MHz/FS0 26 I/O

48-MHz Output:

48 MHz is provided in normal operation. In standard syst em s, this
output can be used as the reference for the Universal Serial Bus. Upon power-up FS0
input will be latched, which will set clock frequencies as described in Table 2.

24MHz/FS1 25 I/O

24-MHz Output:

24 MHz is provided in normal operation. In standard syst em s, this
output can be used as the cloc k input f or a Super I/O chip. Up on power -up FS1 input will
be latched, which will set clock frequencies as described in Table 2.

REF1/FS2 46 I/O

I/O Dual-Functio n REF0 a nd FS2 pin:

Upon power-up , FS2 input will be latched which
will set clock f requencies as described in Table 2. When an output, this pin provides a
fixed cl ock signal equal in frequency to the reference sig nal provided at the X1/X2 pins.

REF0/
(PCI_STOP#)

2I/O

Fixed 14.318-MHz Output 0 or PCI_STOP# Pin:

Function determined by MODE pin.
The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to
remain at logic 0 when LO W. The PCI_STOP signal is latc hed on the rising edge of
PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin
provides a fixed clock signal equal in frequency to the reference signal provided at the
X1/X2 pins.

SDRAMIN 15 I

Buffered Input Pin:

The signal provided to this input pin is buffered to 13 outputs

(SDRAM0:11, SDRAM_F).

SDRAM0:11 38, 37, 35,

34, 32, 31,
29, 28, 21,

20, 18, 17

O

Buffered Outputs:

These twelve ded icate d outp uts pro vide copi es of th e signal provi d­ed at the SDRAMIN input. The swing is set by VDDQ3, and they ar e deactivated when
CLK_STOP# input is set LOW.

SDRAM_F 40 O

Free-running Buff ered Output:

This dedic ated output pro vides a cop y of the SDRAMIN

input which is not affected by the CLK_STOP# input

SCLK 24 I Clock pin for I

2

C circuitry.

SDATA 23 I/O Data pin for I

2

C circuitry.

X1 4 I

Crystal Connection or External Refe rence Frequen cy Input:

This pin has dual func­tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.

X2 5 I

Crystal Connection:

An input connection for an external 14.318-MHz crystal. If using

an external reference, this pin must be left unconnected.

VDDQ3 1, 6, 14, 19,

27, 30, 36

P

Power Connecti on:

Power supply for core logic, PLL circuitry, SDRAM outputs, PCI

outputs, r efe rence out puts , 48 -MHz ou tput, and 24 -MHz out put. Connect t o 3.3V supp ly

VDDQ2 42, 48 P

Power Connecti on:

Po wer supply for IOAPIC, CPU_F, and CPU1 output buffers. Con-

nect to 2.5V or 3.3V.

GND 3, 9, 16, 22,

33, 39, 45

G

Ground Connections:

Connect all ground pins to t he com m on system ground plane.

W199

PRELIMINARY

3

Overview

The W199 was developed as a single-chip device to meet the
clocking needs of the VIA Apollo Pro-133 core logic chip set.
In addition to the typical outputs provided by standard
100-MHz FTGs, the W199 adds a thirteenth outpu t buffer , sup­porting SDRAM DIMM modules in conjunction with the
chipset.

Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en­abled, th is featur e reduces the peak EMI measurement s of not
only the output signals and their harmonics, but also of any
other cloc k signals that are properly syn chronized to them.

Functional Description

I/O Pin Operation

Pins 7, 8, 25 , 26, are 46 are dual-pu rpose l/O pins . Upon po w­er-up these pins act as logic in puts, al lowing the dete rmination
of assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.

An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V

DD

. Connection to ground sets a

latch to “0,” connection to V

DD

sets a latch to “1.” Fig ure 1 an d
Figure 2 show two suggested methods for strapping resistor
connections.

Upon W199 power-up, the first 2 ms of operation is used for
input logic selection. During th is period, the fiv e I/O pins (7, 8 ,
25, 26, 46) are three-stated, allowing the output strapping re­sistor on the l/O pins to pull the pins and their associated ca­pacitiv e clock load to e ither a logic HIGH or LOW state . At the
end of the 2-ms period, the established logic “0” or “1” condi­tion of the l/ O pin is latched. Next the output buffer is enabled,
converting the l/O pins into ope rating clock outputs. The 2-ms
timer starts when V

DD

reaches 2.0V. The input bits can only

be reset by turning V

DD

off and then back on again.

It should be noted that the strapping resistors have no signifi­cant effect on clock output signal integrity. The drive imped­ance of clock outputs is <40Ω (nominal), which is minimally
affected by the 10-kΩ strap to ground or V

DD

. As with the se­ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V

DD

should be ke pt less t han tw o i nches i n lengt h to

minimize system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input

period, the corresponding specified output frequency is deliv­ered on the pin, assuming that V

DD

has stabilized. If VDD has
not yet reached full value, output frequency initially may be
below target but will increase to target once V

DD

voltage has
stabilized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.

Power-on
Reset
Timer

Output Three -state

Data

Latch

Hold

QD

W199

V

DD

Clock Load

10 k

Ω

Output
Buffer

(Load Option 1)

10 k

Ω

(Load Option 0)

Output
Low

Output Strapping Resistor

Series Term ination R es istor

Figure 1. Input Logic Selection Through Resistor Load Option

Power-on
Reset
Timer

Output Three-state

Data

Latch

Hold

QD

W199

V

DD

Clock Load

R

10 k

Ω

Output
Buffer

Output
Low

Output Strapping Resistor

Series Termination Resistor

Jumper Opt i on s

Resistor Value R

Figure 2. Input Logic Selection Through Jumper Opti on

W199

PRELIMINARY

4

Spread Spectrum Frequency Tim ing G enera to r

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 3.

As shown in Figure 3, a harmonic of a modulated clock has a
much low er amplitude th an that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is

dB = 6.5 + 9*log10(P) + 9*log10(F)

Where P is the perce nta ge of de viati on and F is the frequen cy
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation f or the Reducti on of Radiated Emissio ns” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviati on select ed for this chi p is speci fied in Table 7. Figure 4
details the Cypress spr eading pat tern. Cypress does offer op­tions with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices .

Spread Spectrum clocking is activated or deactivated by se­lecting the appropriate v al ues fo r bits 1–0 in data byte 0 of the
I

2

C data stream. Refer to Table 7 for more d e ta ils.

Figure 3. Clock Harmonic with and without SSCG Modulation Freq uency Domain Representation

Spread

Spectrum

Enabled

EMI Reduction

Spread

Spectrum

Non-

MAX (0%)

MIN (–5%)

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

FREQUENCY

Figure 4. Typical Modulation Profile

W199

PRELIMINARY

5

Serial Data Interface

The W199 features a two-pin, seri al data int erface that can be
used to configure internal register settings that control partic­ular de vice funct ions. Upon power -up , the W199 i nitiali zes wit h
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chi p) and i s the dedi cated f unc tion of de v ice pi ns SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the

chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used duri ng system operation for power manage­ment functions. Ta b le 3 summarizes the control functions of
the serial data interface.

Operation

Data is written to the W199 in elev en bytes of eight bits each .
Bytes are written in the order sho w n in Table 4.

T able 3. Serial Data Interface Control Func ti ons Sum mary

Control Function Description Common Application

Clock Output Disable Any individual clock output(s) can be disabled.

Disabled out puts are actively hel d LOW.

Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.

CPU Clock Frequency
Selection

Provides CPU/PCI fr equency selections through
software. Frequency is changed in a smooth and
controlled fashion.

For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.

Spread Spectrum
Enabling

Enables or dis ables spread spectrum cl ocking. For EMI reduction.

Output Three-st ate Puts clock output into a high-impedance state. Production PCB testing.
(Reserved) Reserved function for future device revi sion or

production de vice testing.

No user application. Register bit must be
written as 0.

Table 4. Byte Writing Sequence

Byte

Sequence Byte Name Bit Sequence Byte Description

1 Slave Address 11010010 Commands the W199 to accept the bits in Dat a Bytes 0–6 for inte rn a l

register co nfigurati on. Since oth er devi ces may e xist on the same com­mon serial dat a bus, it is n ecessary to ha ve a specific sl av e address for
each potential receiver. The slave receiver address for the W199 is

11010010. Regist er setting wi ll not be mad e if the Slav e Addr ess is not
correct (or is f or an alternate slave receiver) .

2 Command Code Don’t Care Unused by the W199, therefore bit values are ignored (“don’t care”).

This byte must be included in the data write sequence to maintain
proper by te allocation . The Command Code Byte is part of t he standard
serial communi ca tion protoc ol and ma y be use d whe n writi ng t o a noth­er addressed slave receiver on the serial data bus.

3 Byte Count Don’t Care Unused by the W199, therefor e bit values are ignored (“don’t care”).

This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standar d
serial communi ca tion protoc ol and ma y be use d whe n writi ng t o a noth­er addressed slave receiver on the serial data bus.

4 Data Byte 0 Refer to Table 5 The data bit s in Data Bytes 0–7 s et internal W199 register s that c ontrol

device operation. The data bits are only accepted when the Address
Byte bit seq uence is 11010010, as noted above. For description of bit
control f unctions, refer to Table 5, Data Byte Serial Confi guration Map.

5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4

9 Data Byte 5
10 Data Byte 6
11 Data Byte 7