Cypress W184 Datasheet

Six Output Peak Reducing EMI Solution

Features

Cypress PREMIS™ family offering

•

• Generates an EMI optimized c locking signal at the
output

• Selectable i nput t o output frequency

• Six 1.25%, 3.75%, or 0% down or center spr ead outputs

• One non-Spread refer ence output

• Integrated loop filter components

• Operates with a 3.3 or 5V supply

• Low power CMOS design

• Available in 24-pin SSOP (Shrunk Small Outline
Package)

• Outputs may be selectively disabled

Key Specifications

Suppl y Voltages: ............ .. ... ....... .. ... ....... ... ....VDD = 3.3V±5%

Fr equency Range: ................. .......... ... 8 MHz ≤ F

Crystal Reference Range.................... 8 MHz ≤ F

Cycle to Cy c le Ji tte r:........... ....... .. ... ....... ... .. ..... 300 ps (max.)

Selectabl e Spread Percentage: ....... .. .......... .1.2 5% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output R is e a n d Fall Tim e : . .. .. ........ .. ... ....... .. ... .... 5 ns (max.)

or V

= 5V±10%

DD

≤

28 MHz

in

≤

28 MHz

in

Table 1. Modulation Width Selection

SS%

0F

1F

W184

Output

≥

≥

F

in

out

≥

F

in

out

– 1.25% F

F

in

≥

– 3.75% F

F

in

0.625%

–1.875%

W184-5

Output

+ 0.625% ≥ F

in

+ 1.875% ≥ F

in

T able 2. Frequency Range Selection

FS2 FS1 Frequency Range

00 8 MHz ≤ F
0 1 10 MHz ≤ F
10 15 MHz ≤ F
11 18 MHz ≤ F

IN

IN
IN
IN

≤

10 MHz

≤

15 MHz

≤

18 MHz

≤

28 MHz

Table 3. Output Enable

EN1 EN2 CLK0:4 CLK5

0 0 Low Low
01Low Active
10Active Low
1 1 Active Active

W184

≥

–

in

in≥

Simplified Block Diagram

3.3 or 5.0V

X1

XTAL
Input

Oscillator or
Ref e re nce Input

PREMIS is a trademark of Cypress Semiconductor Corporation.

X2

W184

3.3 or 5.0V

W184

Spread Spectrum
Outputs

(EMI suppres s ed )

Spread Spectrum

Outputs

(EMI suppressed)

Pin Configuration

SSOP

REFOUT

FS2

GND
SS%

EN2
GND

CLK0
VDD
CLK1
CLK2

X1
X2

1
2
3
4

5
6

7

8
9

10

11

12

24
23

W184/W184-5

22
21
20
19
18
17
16
15

14
13

SSON#
RESET
FS1
VDD
VDD

NC
EN1

CLK5
VDD
CLK4

GND
CLK3

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 2 5, 2000, rev. *B

Pin Definitions

W184

Pin Name Pin No.

CLK0:5 9, 11, 12 , 13,

15, 17

CLKIN or X1 3 I

NC or X2 4 I

SS% 6 I

Reset 23 I

REFOUT 14 O

EN1:2 18, 7 I

SSON# 24 I

FS1:2 22, 2 I

VDD 10, 16, 20, 21 P

Pin

Ty pe Pin Description

O

Modulated Frequency O utputs:

ulated input clock (SSON# asserted).

Crystal Connection or External Reference Frequency Input:

dual functions. It may ei ther be connected to an external crystal, or to an
external reference clock.

Crystal Connection:

connected.

Modulation Width Selection:

this pin is used to selec t t he am ount of v ariation and peak EM I r eduction that
is desired on the output signal. This pin has an int ernal pull-up resistors.

Modulation Profile Restart:

pattern at the begi nning of its de fined path . This pin has an internal pul l-do wn
resistor.

Non-Modulated Output:

This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.

Output Enable Select Pins:

buffers. Set them to di sable unused outputs using Table 3 as a guid e.

Spread Spectrum Contro l (Active LOW):

turns the internal modul ation wav e f orm on. Thi s pin has an internal pul l-do wn
resistor.

Frequency Selection Bit 1 and 2:

tion. Refer to Table 1. These pins have internal pull-up resistors.

Po wer Connec tion:

If using an external re ference, this pin must be left un-

This pin provides a copy of the ref erence frequ ency.

Connected to 3.3V or 5V po wer supply.

Fr equency modu lat ed copi es of th e unmod -

This pin has

When Spread Spectrum feature is turned on,

A rising edge on this input restarts the modulati on

These pins contr ol the act ivi ty of spec ifi c output

Asserting this signal (acti ve LOW )

These pins select the frequency of opera-

2

W184

Overview

The W184 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advanc es in PLL spread spectrum frequency synthesizer t ech­niques. By frequency modulating the output with a low­frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.

In a system, not only i s EMI reduce d in the v arious cl oc k li nes,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and dat a lines in the syst em. The Sim­plified Block Diagram sho ws a simple implementa ti on.

Functional Description

The W184 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detec tor als o . The PLL will f or ce the frequen cy of
the VCO output sign al to change until the divid ed output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q

times the ref er ence fre quenc y. (Note: Fo r the W 184 the ou tpu t
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to th e VCO. This causes the VCO output to be s low ly
swept across a predetermined frequency band.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re­duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percent age m ay be varied .

Using frequency select bits (FS1:2 pins), the f requency range
can be set. Spreading percentage may be selected to 1.25%
or 3.75% (see Tabl e 1).

A larger spreading per centage improv es EMI reduction. Ho w­ever, large spread percentages may either exceed system
maximum frequ ency ra tings o r lo wer the a v er age fr eque ncy to
a point where performance is affected. For these reasons,
spreading percent age options are provided.

V

DD

Clock Input

Reference Input (EMI suppressed)

Freq. Phase

Q

Detector

Feedback

Divider

P

Charge

Pump

GND

Σ

Modulating

Waveform

VCO

PLL

Post

DividersDivider

CLKOUT

Figure 1. Functional Block Diagram

3

W184

Spread Spectrum Frequency Timing
Generation

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in

As shown in

)LJXUH 

, a harmonic of a modulated clock has a
much low er amplit ude than that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

Amplitude (dB)

(P) + 9*log10(F)

10

SSFTG Typical Clock

)LJXUH 

.

Where P is the pe rcentag e of de vi ation an d F is the frequency
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

)LJXUH 

. This waveform, as discussed in “Spread Spectrum
Clock Gener ation f or the Redu ct ion of Radiat ed Emission s” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiat ed electro magnetic emis sions.



details the Cypress spreading pattern. Cypress does offer

)LJXUH

options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.

EMI Reduction

Spread

Spectrum

Enabled

Amplitude (dB)

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Down Spread

Figure 2. Clock Har monic with and without SSCG Modulat ion Frequenc y Domain Represent ation

MAX.

10%

20%

30%

40%

50%

60%

70%

80%

FREQUENCY

MIN.

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

Figure 3. Typical Modulation Profile

90%

100%

4

Absolute Maximum Ratings

W184

Stresses greater than those listed in this table may cause per­manent damage to the de vice . These represent a stress ratin g
only. Operation of the device at these or any other conditions

.

above those specified in the operating sections of t his specifi­cation is not implied. Maximum conditions for ex tended peri­ods may affect reliability.

Parameter Description Rating Unit

V

, V

DD

IN

T

STG

T

B

T

A

P

D

DC Electr i cal C h ar acteristics

Voltage on any pin with respect to GND –0.5 to +7 .0 V
Storage Temperature –65 to +150 °C
Ambient Temperature under Bias –55 to +125 °C
Operating Temperature 0 to +70 °C
Power Dissipation 0.5 W

:

0°C < T

< 70°C, VDD = 3.3V ±5%

A

Parameter Description T est Condition Min. Typ. Max. Unit

I

DD

t

ON

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OL

I

OH

C

I

C

I

R

P

Z

OUT

Note:

1. Inputs FS1:2, SS% have a pull-up resistor; Input SSON# has a pull-down resistor.

Supply Current 18 32 mA
Power Up Time First locked clock c ycle after Power

5ms

Good
Input Low Voltage 0.8 V
Input High Voltage 2.4 V
Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Input Low Current Note 1 –50 µA
Input High Current Note 1 50 µA
Output Low Current @ 0.4V, VDD = 3.3V 15 mA
Output High Current @ 2.4V, VDD = 3.3V 15 mA
Input Capacitance All pins e xcept CLKIN 7 pF
Input Capacitance CLKIN pin only 6 10 pF
Input Pull-Up Resistor 500 kΩ
Clock Output I mp edance 25 Ω

5

W184

DC Electr i cal C h ar acteristics:

0°C < T

< 70°C, VDD = 5V ±10%

A

Parameter Description Test Condi ti on Min. Typ. Max. Unit

I

DD

t

ON

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OL

I

OH

C

I

C

I

R

P

Z

OUT

AC Electrical Characteristics:

Supply Current 30 50 mA
Power Up Time First locked clock cycle after

5ms

Power Good
Input Low Voltage 0.15V
Input High Voltage 0.7V

DD

DD

Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Input Low Current Note 2 –50 µA
Input High Current Note 2 50 µA
Output Low Current @ 0.4V, VDD = 5V 24 mA
Output High Current @ 2.4V, VDD = 5V 24 mA
Input Capacitance All pins except CLKIN 7 pF
Input Capacitance CLKIN pin only 6 10 pF
Input Pull-Up Resistor 500 kΩ
Clock Output I mp edance 25 Ω

TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%

Symbol Parameter T est Condition Min. Typ. Max. Unit

f

IN

f

OUT

t

R

t

F

t

OD

t

ID

t

JCYC

EMI

RED

Input Frequency Input Clock 8 28 MHz
Output Frequency Spread Off 8 28 MHz
Output Rise Time VDD, 15-pF load 0.8V–2.4V 2 5 ns
Output Fall Time VDD, 15-pF load 2.4V–0.8V 2 5 ns
Output Duty Cycle 15-pF load 40 60 %
Input Duty Cycle 40 60 %
Jitter, Cycle-to-Cy c le 250 300 ps
Harmonic Reduction f

= 40 MHz, thir d harmonic

out

measured, reference board,

8dB

15-pF load

t

SK

Note:

2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

Output to Output Skew 200 ps

V
V

6

W184

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power
supply decoupli ng scheme sho wn in Figure 4 should be used .

decoupling is important to both reduce phase jitter and

V

DD

EMI radiation. The 0.1-µF decoupling capacitor should be

W184

Clock Output

XTAL connection or NC

Clock Output

Clock Output
Clock Output

R1

Logic Input

Reference Input

Logic Input
Logic Input

R1

R1
R1

C1

0.1 µF

1
2
3
4

5
6
7

8

9

10
11
12

3.3 or 5V System Supply

placed as close to the V

pin as possible, otherwise the in-

DD

creased trace inductance will negate i ts decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V

connection can be

DD

made via a ferrite bead, as shown.

Logic Input

24

Logic Input

23
22
21

20
19

18
16

15
14

13

17

Logic Input

NC

Logic Input

R1

R1

R1

FB

Clock
Clock

Clock

Output
Output

Output

C2
10-

C1

0.1

C1

0.1

µF Tantalum

µF

µF

C1

0.1 µF

Ordering Information

Ordering Code

W184
W184-5

Document #: 38-00797-B

Figure 4. Recommended Circuit Configuration

Package

Name

Package Type

H 24-Pin SSOP (209-mil)

7

Package Diagram

W184

24-Pin Shrink Small Outline Package (SSOP, 209 mils)

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.