Cypress W182 Datasheet
Full Feature Peak Reducing EMI Solution
Features
Cypress PREMIS™ family offering
•
• Generates an EMI optimized c locking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% dow n or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14 -p i n S OIC (S mall Outl in e Int e g ra te d
Circuit)
Key Specifications
Suppl y Voltages: .............. .......... .......... .. .......VDD = 3.3V±5%
Fr equency Range: ........ ............ ..........8 M H z ≤ F
Cycle to Cy c le Ji tte r:........... .. .. .......... .......... .....300 ps (max.)
Selectabl e Spread Percentage: .......... ..........1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output R is e a n d Fall Tim e : . .. .. .......... .......... ......... 5 ns (max.)
or V
= 5V±10%
DD
≤
28 MHz
in
T able 1. Modulation Width Selection
W182
SS%
0F
1F
≥
F
in
– 1.25%
≥
F
in
– 3.75%
Output
≥
F
out
≥
F
out
in
in
F
in
– 0.625%
F
in
–1.875%
Table 2. Frequency Range Selection
FS2 FS1 Frequency Range
00 8 MHz ≤ F
0 1 10 MHz ≤ F
10 15 MHz ≤ F
11 18 MHz ≤ F
IN
IN
IN
IN
W182
W182-5
Output
+ 0.625% ≥ F
+ 1.875% ≥ F
≤
10 MHz
≤
15 MHz
≤
18 MHz
≤
28 MHz
in
in≥
≥
Simplified Block Diagram
3.3V or 5.0V
X1
XTAL
Input
Oscilla tor or
Reference Input
X2
W182
3.3V or 5.0 V
W182
Spread Spectrum
Output
(EMI su ppressed)
Spread Spectrum
Output
(EMI suppressed)
Pin Configuration
SOIC
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
7
W182/W182-5
13
12
11
10
9
8
OE#
SSON#
Reset
VDD
VDD
CLKOUT
REFOUT
14
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000 , rev. *A
Pin Definitions
W182
Pin Name Pin No.
CLKOUT 8 O
REFOUT 14 O
CLKIN or X1 2 I
NC or X2 3 I
SSON# 12 I
SS% 6 I
OE# 13 I
Reset 11 I
FS1:2 7, 1 I
VDD 9,10 P
GND 4,5 G
Pin
Ty pe Pin Description
Output Modulated Frequency
(SSON# asserted).
Non-Modulated Output:
This output will not have the Spread Spect rum feature enabl ed regardless of
the state of logic input SSON#.
Crystal Connection or External Reference Frequency Input:
dual functions. It may either be connected to an ex ternal crystal , or to an
external reference clock.
Crystal Connection:
ternal reference, this pin mus t be left unconnected.
Spread Spectrum Contro l (Active LOW):
turns the internal modul ation wav e f orm on. Thi s pin has an internal pul l-do wn
resistor.
Modulation Width Selection:
this pin is used to select the am ount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull -up resistor.
Output Enable (Active LOW):
are placed in a high-impedance mode.This pin has an internal pull-down resistor.
Modulation Profile Restart:
pattern at the begi nning of its de fined path . This pin has an internal pul l-do wn
resistor.
Frequency Selection Bit(s):
ation. Refer to Table 2. These pins have internal pull-up resistors.
Po wer Connec tion:
Ground Connection:
Input connectio n for an external crystal. If using an ex-
Connected to 3.3V or 5V po wer supply.
Connect all g round pins to the common ground plane.
: Freq uency modulat ed copy of the input clock
This pin provides a copy of the ref erence frequ ency.
This pin has
Asserting this signal (acti ve LOW )
When Spread Spectrum feature is turned on,
When this pi n is he ld HIGH, th e output b uff er s
A rising edge on this input restarts the modulati on
These pins select the frequency range of oper-
2
W182
Overview
The W182 product is one of a seri es of de v ices i n the Cypr ess
PREMIS family. The PREMIS family incorporates the latest
advanc es in PLL spread spectrum frequency synthesizer t echniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatl y reduced. Use of this technology allows s ystems to pass increasingl y diff icult EMI testin g
without resorting to costly shielding or redesign.
In a system, not only i s EMI reduce d in the v arious cl oc k li nes,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and dat a lines in the syst em. The Simplified Block Diagram shows a simple implementation.
Functional Description
The W182 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detec tor als o . The PLL will f or ce the frequen cy of
the VCO output sign al to change until the divid ed output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the ref er ence fre quenc y. (Note: F or t he W182 t he outpu t
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to th e VCO. This cau ses the VCO out put to be slo wl y
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum process has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be va ried .
Using frequency select bits (FS2: 1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.
A larger spreading per centage improves EMI reduction. However, large spread percentages may either exceed system
maximum frequ ency ra tings o r lo wer the a v er age fr eque ncy to
a point where performance is affected. For these reasons,
spreading percent age options are provided.
V
DD
Clock Input
Reference Input (EMI suppressed)
Freq. Phase
Q
Detector
Feedback
Divider
P
Charge
Pump
GND
Σ
Modulating
Waveform
VCO
PLL
Post
DividersDivider
CLKOUT
Figure 1. Functional Block Diagram
3
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