Cypress W181-03, W181-02, W181-01 Datasheet

Peak Reducing EMI Solution

W181

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 21 , 2000, rev. *B

Features

•

Cypress PREMIS™ family offering

• Generates an EMI optimized c loc king signa l at the out­put

• Selectable i nput t o output frequency

• Single 1.25% or 3.75% dow n or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated Cir­cuit) or 14-pin TSSOP (Thin Shrink Sm all Outline Pac k­age select options only)

Key Specifications

Supply Voltages: .... .......... ... ......... ... .. .......... ..VDD = 3.3V±5%

or V

DD

= 5V±10%

Frequency Range: ................... .........28 MHz ≤ F

in

≤

75 MHz

Crystal Reference Range.................. 28 MHz ≤ F

in

≤

40 MHz

Cycle to Cy c le Ji tte r: .. ... ......... ... .. .......... ... ....... 300 ps (max .)

Selectabl e Spread Percentage: ....................1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output R is e a n d Fall Tim e : .......... ... .......... .. ......... 5 ns (max.)

T able 1. Modulation Width Selection

SS%

W181-01, 02, 03

Output

W181-51, 52, 53

Output

0F

in

≥

F

out

≥

F

in

–

1.25%

F

in

+ 0.625% ≥ F

in

≥

– 0.625%

1F

in

≥

F

out

≥

F

in

–

3.75%

F

in

+ 1.875% ≥ F

in≥

–1.875%

Table 2. Frequency Range Selection

W181 Option#

FS2 FS1

-01, 51
(MHz)

-02, 52
(MHz)

-03, 53
(MHz)

0 0 28 ≤ F

IN

≤

38 28 ≤ F

IN

≤

38 N/A

0 1 38 ≤ F

IN

≤

48 38 ≤ F

IN

≤

48 N/A

1 0 46 ≤ F

IN

≤

60 N/A 46 ≤ F

IN

≤

60

1 1 58 ≤ F

IN

≤

75 N/A 58 ≤ F

IN

≤

75

PREMIS is a trademark of Cypress Semiconductor Corporation.

Simplified Block Diagram

Pin Configurations

W181-02/03

8
7

6
5

1
2

3
4

CLKIN or X1

NC or X2

GND
SS%

SSON#
FS1

VDD
CLKOUT

W181-01/51

8
7
6
5

1
2
3
4

CLKIN or X1

NC or X2

GND
SS%

FS2
FS1
VDD
CLKOUT

SOIC

Spread Spectrum

W181

(EMI suppressed)

3.3 or 5.0V

Oscilla tor or

Spread Spectrum

W181

(EMI suppressed)

3.3 or 5.0V

XTAL

X1

X2

Reference Input

Input

Output

Output

40 MHz

Max.

W181-01

8

1
2
3
4

CLKIN or X1

NC or X2

GND
SS%

NC

FS1

VDD

CLKOUT

5
6

7

9

10

11

12

13

14

FS2

NC

NC

NC

NC

NC

TSSOP

W181-52/53

W181

2

Pin Definitions

Pin Name

Pin No.

(SOIC)

Pin No.

(TSSOP)(-01)

Pin

Type Pin Description

CLKOUT 5 8 O

Output Modulated Frequency

: Frequency modulated copy

of the unmodulated input clock (SSON# asserted).

CLKIN or X1 1 2 I

Crystal Connection or External Reference Frequency In­put:

This pin has dual functi ons. It may eit her be connected

to an external crystal , or t o an external ref erence clock.

NC or X2 2 3 I

Crystal Connection:

If using an e xternal refere nce, this pin

must be left unconnected.

SSON# 8(02/03/52/

53)

-- I

Spread Spectrum Control (Active LO W):

Asserting this si g­nal (active LO W) turns the inte rnal modulation wa v eform on.
This pin has an internal pull- down resistor.

FS1:2 7, 8 (01/51) 12, 1 I

Frequency Selection Bit(s) 1 and 2:

These pins select the
frequency ra nge of operation. Refer to Table 2. These pins
have internal pull-up resistors.

SS% 4 6 I

Modulation Width Selection:

When Spread Spectrum fea­ture is turned on, this pin is used to sel ect the amount of
variation and peak EMI reduction that is desired on th e output
signal. This pin has an internal pull-up resistor.

VDD 6 10 P

Po wer Connec tion:

Connected to 3.3V or 5V pow er supply.

GND 3 4 G

Ground Connection:

Connect all ground pins to the com-

mon system groun d plane.

NC 5, 7, 9, 11, 13,

14

NC

No Connection.

W181

3

Overview

The W181 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advanc es in PLL spread spectrum frequency synthesizer t ech­niques. By frequency modulating the output with a low­frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shieldi ng or redesign.

In a system, not only i s EMI reduce d in the v arious cl oc k li nes,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and dat a lines in the syst em. The Sim­plified Block Diagram on page 1 shows a simple implementa­tion.

Functional Description

The W181 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detec tor also. The PLL will f or ce the fr equen cy of
the VCO output sign al to change until the divided out put signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q

times the ref er ence fre quenc y. (Note: F or t he W181 t he outpu t
frequency is eq ual to the input frequency.) Th e unique feature
of the Spread Spect rum Fr equ ency Timi ng Gener ator is that a
modulating wa vef orm is supe rimposed at t he input to the VCO .
This causes the VCO output to be slowly swept across a pre­determined frequency ban d.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re­duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be va ried .

Using frequency s elect bits (FS1:2 pins), the frequency range
can be set. Spr eading p erc entage i s set to be 1 .25% o r 3 .75%
(see Tabl e 1).

A larger spreading per centage improves EMI reduction. How­ever, large spread percentages may either exceed system
maximum frequ ency ra tings o r lo wer the a v er age fr equency t o
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.

Freq. Phase

Modulating

VCO

Post

CLKOUT

Detector

Charge

Pump

Waveform

DividersDivider

Feedback

Divider

PLL

GND

V

DD

Σ

Q

P

Clock Input

Reference Input (EMI suppressed)

Figure 1. Functional Block Diagram