Cypress W147GH Datasheet
PRELIMINARY
Frequency Generator for Integrated Core Logic
W147G
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **
Features
• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum Technology
• Low jitter and tight ly controlled clock skew
• Highly int egrated device pr oviding clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• T wo copies of synchronous APIC c lock
• T wo copies of 4 8-MHz cloc k (non-spre ad spectrum) optimized for USB refer ence input and video dot clock
• T w o copies of 66-MHz fixed cl ock
• One copy of 14.31818-M Hz reference clock
• Power-down control
•I
2
C interface for turning off unused clock s
Key Specifications
CPU, SDRA M Ou t p ut s C y cl e -to - C yc le Ji tt er:............ ..2 5 0 ps
APIC, 48MHz, 3V66, PCI Output s
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: .........................250 ps
CPU, 3V66 O ut p u t Skew: ............... ............. ............ ....1 7 5 p s
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V6 6 Skew (@ 66 MH z ): . ............ ..........7.0 to 8. 0 n s
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to AP IC S kew: . ... .. ............ ...................... ............ .±0.5 ns
T able 1. Pin Selectable Functions
SEL1 SEL0 Function
0 0 Three-state
01 Test
1 0 66-MHz CPU
1 1 100-MHz CPU
Block Diagram
Pin Configuration
VDDQ3
VDDQ2
CPU2_ITP
PCI0_ICH
XT A L
PLL REF FREQ
PLL 1
X2
X1
REF/APICDIV
PCI1:7
USB
DOT
PLL2
OSC
VDDQ3
I2C
SDATA
Logic
SCLK
3V66_0:1
CPU0:1
SEL0:1
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
7
2
VDDQ3
2
2
DCLK
SDRAM0:7
8
PWRDWN#
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
W147G
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
USB
DOT
VDDQ3
SEL0
PWRDWN#
SCLK
SDATA
SEL1
W147G
PRELIMINARY
2
Pin Definitions
Pin Name Pin No.
Pin
T ype Pin Description
REF/APICDIV 1 I/O
Reference Cloc k:
3.3V 14.318-MHz clock output. This pin doubles as th e select
strap fo r APIC clock fre quency. If stra pped LOW during power up , APIC clock runs
at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed.
X1 3 I
Crystal Input:
This pin has dual functi ons. It can be used as an ext ernal
14.318-MHz crystal connection as an external reference frequency input.
X2 4 I
Crystal Output:
An input connection f or an external 14.318-MHz crystal. If using
an external reference, thi s pin must be left unconnected.
PCI0_ICH,
PCI1:7
11, 12, 13, 15,
16, 18, 19. 20
O
PCI Clock 0 through 7:
3.3V 33-MHz PCI clock outputs. PCI 1:7 can be i ndividually
turne d of f vi a I
2
C interface.
3V66_0:1 7, 8 O
66-MHz Clock Outp ut:
3.3V fix ed 66-MHz clock.
USB 25 O
USB Clock Output:
3.3V fixe d 48-MHz, non- spread sp ectrum USB cloc k outputs .
DOT 26 O
Dot Clock Output:
3.3V 48-MHz, non-spread spectrum signal.
SEL0:1 28, 29 I
Clock Function Selection pins:
LVTTL-compatible input to select device func-
tions. See Table 1 for det ail ed descriptions.
PWRDWN# 32 I
Power Down Control:
LVTTL-compati ble asynchronous input that places the de-
vice in power- down mode when held LOW.
CPU2_ITP,
CPU0:1
49, 52, 50 O
CPU Clock Outputs:
Clock output s for the host bus interface and inte grated test
port. Output frequen cies run at 66 MHz o r 100 MHz dependi ng on the conf iguration
of SEL0:1. Voltage swing set by V
DDQ2
.
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36, 34O
SDRAM Clock Outputs:
3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I
2
C interface.
APIC0:1 55, 54 O
Sychronous APIC Clock Outputs:
Clock outputs running di vide synchronous
with the PCI clock out puts. Output freque ncy is controlled by the st rap option on
REF. Voltage swing set by V
DDQ2
.
SDATA 30 I/O Data pin for I
2
C circuitry .
SCLK 31 I Clock pin for I
2
C circuitry.
VDDQ3 2, 9, 10, 21, 27,
33, 38, 44
P
3.3V Pow er Connection:
Po wer supply for SDRAM output buffers, PCI out put
buffe rs, 3V66 o utput b u ff ers, reference output buff ers, and 48-MHz output buf fer s .
Connect to 3.3V.
VDD3 22 P
3.3V Pow er Connection:
Po wer supply for cor e logi c, PLL circuitry. Connect to
3.3V.
VDDQ2 51, 53 P
2.5V Power Conne ction:
Powe r supply f or IO APIC and CPU output bu ff ers. Con-
nect to 2.5V or 3.3V.
GND 5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
G
Ground Connections:
Connect all ground pins to the common system ground
plane.
W147G
PRELIMINARY
3
Overview
The W147G is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics in tegrated core logic.
Functional Description
I/O Pin Operation
REF/APICDIV is a dual purpose l/O pin. Upon power-up the
pin acts as a logic input. If the pin is strapped to a LOW state
externally, APIC cloc k outputs will run divide synchronously at
half PCI clock speed. If it is pulled HIGH, APIC clock will run
synchronous to PCI cloc ks. An external 10-kΩ s trapp ing r esi stor should be used. Figure 1 shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output freq uency initiall y m ay be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Function s
Table 1 outlines the device functions selectable through
SEL0:1. Specific outputs available at each pin is detailed in
Table 2 below. The SEL0 pin requires a 220Ω pull-up resistor
to 3.3V for the W147G to sense the maximum host bus frequency of the processor and configure itself accordingly.
Notes:
1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
2. Provided for board level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W147G
V
DD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Whitney Truth Table
SEL1 SEL0 CPU SDRAM 3V66 PCI 48MHz REF APIC
[1]
Notes
0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2
0 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 4, 5
1 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7
1 1 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7
W147G
PRELIMINARY
4
Offsets Among Clock Signal Groups
Figure 2 and Figur e 3 represe nt the pha se rel ation shi p amon g
the different groups of clock outputs from W147G when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
Figure 2. Group Offset W aveforms (66-MH z CPU Clock)
40 ns30 ns20 ns10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
SDR A M 10 0 P e riod
CPU 100 Period
Hub-PCI
Figure 3. Group Offset Waveforms (100-MHz CPU Clock)
40 ns30 ns20 ns10 ns
Loading...