Cypress W144H Datasheet
PRELIMINARY
440BX AGPset Spread Spectrum
Features
• Maximized EMI suppression usi ng Cypress’s Spread
Spec trum te chnol ogy
• Single chip system frequency synthesizer for Intel
®
440BX AGPset
• T wo copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SI O
• T wo buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
2
•I
C™ interface for programming
• Power man agement control inputs
Key Specific ati o n s
CPU Cycle-to-Cycle Jitter: ........... ........... .. ................. 250 ps
CPU to CPU Output Skew: ............... ................. ........ 175 ps
PCI to PCI Output Skew:........................... .. .. .............500 ps
: .................................................................... 3.3V±5%
V
DDQ3
: .................................................................... 2.5V±5%
V
DDQ2
SDRAM IN to SDRAM0:1 1 De lay: ..... .......... .......... .3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew:..............0.4 ns typ.
Logic Block Diagram
VDDQ3
REF0/(PCI_STOP#)
X1
X2
CLK_STOP#
SDATA
SCLK
SDRAMIN
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
PLL 1
I2C
Logic
PLL2
XTAL
OSC
I/O Pin
Control
÷2,3,4
Stop
Clock
Control
PLL Ref Freq
Stop
Clock
Control
Stop
Clock
Control
Stop
Clock
Control
÷2
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
T able 1. Mode Input Table
0PCI_STOP#
1REF0
T able 2. Pin Selectable Frequency
1 1 1 1 133.3 33.3 (CPU/4)
1110 124 31 (CPU/4)
1 1 0 1 150 37.5 (CPU/4)
1100 140 35 (CPU/4)
1011 105 35 (CPU/3)
1 0 1 0 110 36.7 (CPU/3)
1 0 0 1 115 38.3 (CPU/3)
1000 120 40 (CPU/3)
0 1 1 1 100 33.3 (CPU/3)
0 1 1 0 133.3 44.43 (CPU/3)
0 1 0 1 112 37.3 (CPU/3)
0 1 0 0 103 34.3 (CPU/3)
0 0 1 1 66.8 33.4 (CPU/2)
0 0 1 0 83.3 41.7 (CPU/2)
0 0 0 1 75 37.5 (CPU/2)
0 0 0 0 124 41.3 (CPU/3)
Pin Configuration
Frequency Synthesizer
Mode Pin2
Input Address
REF0/(PCI_STOP#)
VDDQ3
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
{
I2C
SCLK
Note:
1. Internal pull-up resistors should not be relied upon for setting
I/O pins HGH. Pin function with parentheses determined by
MODE pin resistor strapping. Unlike other I/O pins, input FS3
has an internal pull down resistor.
CPU_F , CPU1
(MHz) PCI_F, 1:5 (MHz)FS3 FS2 FS1 FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W144
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
W144
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Novembe r 2, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name Pin No.
CPU_F 44 O
CPU1 43 O
PCI2:5 10, 11, 12, 13O
PCI1/FS3 8 I/O
PCI_F/MODE 7 I/O
CLK_STOP# 41 I
IOAPIC 47 O
48MHz/FS0 26 I/O
24MHz/FS1 25 I/O
REF1/FS2 46 I/O
REF0/
(PCI_STOP#)
SDRAMIN 15 I
SDRAM0:11 38, 37, 35,
SDRAM_F 40 O
SCLK 24 I Clock pin f or I
SDATA 23 I/O Data pin for I
X1 4 I
X2 5 I
VDDQ3 1, 6, 14,
VDDQ2 42, 48 P
GND 3, 9, 16,
2 I/O
34, 32, 31,
29, 28, 21,
20, 18, 17
19, 27, 30,
36
22, 33, 39,
45
Pin
Ty pe Pin Description
Free-running CPU Clock:
VDDQ2. See Tables 2 and 6 for deta il ed frequency inf ormation.
CPU Clock Output 1:
pin. Output v oltage swing is contr olled by voltage applied to VDDQ2.
PCI Clock Outputs 2 through 5:
PCI_STO P# contro l pin. O utput v olt age s wing is control led b y v olt age appli ed to VDDQ3.
Fixed PCI Clock Output:
serial input i nterf ace, se e T ables 2 and 6. This output is af fect ed by the PCI _ST OP# input.
When an input, latches data selecting the frequ ency of the CPU and PCI outputs.
Fixed PCI Clock Output:
serial input interface, see Tables 2 and 6. This output is not affected by th e PCI_STOP#
input. When an input , set s function of pin 2.
CLK_STOP# input:
completing a full c lock c ycle (2–3 CPU clock latency) . When br ought HIGH, affec ted cloc k
outputs start, beginni ng with a full clock cycle (2–3 CPU clock latency) .
IOAPIC Clock Output:
is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48-MHz Output:
can be use d as the reference fo r the Univer sal Serial Bus. Upon power-up FS0 input will
be latched, which will set clock frequencies as desc rib ed in Table 2 .
24-MHz Output:
can be used as the clock input for a Super I/O chip
latched, which wil l set clock frequencies as described in Table 2.
I/O Dual-Function REF0 and FS2 pin:
will set clock frequencies as described in Table 2. When an output, this pin prov ides a
fixed cl ock signal equal in frequency to the reference signal provided at the X1/X2 pins.
Fixed 14.318-MHz Output 0 or PCI_STOP# Pin :
The PCI_STO P# input enables the PCI 1:5 output s when HIGH and causes them to
remain at logic 0 when LO W . The PCI_STOP si gnal is latched on the rising edge of PCI_ F .
Its eff ects take plac e on the next PCI_F cl ock cycle. W hen an output, this pin provides a
fixed cl ock signal equal in frequency to the reference signal provided at the X1/X2 pins.
Buffered Input Pin:
(SDRAM0:11, SDRAM_F).
Buffered Outputs:
O
at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
CLK_STOP# i nput is set LOW.
Free-running Buffered Output:
input which is not affected by the CLK_ST O P# input
Crystal Connection or External Reference Frequency Input:
tions. It can be used as an external 14.318-M Hz crystal connection or as an external
reference frequency input.
Crystal Connection:
external re ference, this pin must be left unconnected.
Power Co nnect ion :
P
outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply.
Power Connection:
to 2.5V or 3.3V.
Ground Connections:
G
Output voltage swing is controlled by the voltage applied to
This CPU clock output is controlled by the CLK_STO P# control
These four PCI clock outputs are con tr olled by the
As an output. frequency is set by the FS0:3 inputs or through
As an output, frequency is set by the FS0:3 inputs or through
When brought LOW, affected clock outputs are stopped LOW after
Provides 14.318-MHz fixed frequency. The output vol tage swing
48 MHz is provided i n normal operation. I n standard systems , this output
24 MHz is provided i n normal operation. I n standard systems , this output
Upon power-up, FS2 input will be latched, which
The signal provided to th is input pin is buff ered to 13 outputs
These twelv e dedi cated outputs p rovide c opies of t he signa l provided
This dedicated output provides a cop y of the SDRAMIN
2
C Circuitry
2
C Circuitry
An input connect ion fo r an external 14.318-MHz cryst al. If using an
Power supply for core logi c, PLL circuitry, SDRAM outputs, PCI
Powe r supply for IOAPIC , CPU_F , and CPU1 output buffer s. Connect
Connect all ground pins to the common system gr ound plane.
.
Upon power-up FS1 i nput will be
Function determined by M ODE pin.
This pin has dual func-
W144
2
PRELIMINARY
W144
Overview
The W144 was developed as a single-chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX
FTGs,
the W144 adds a thirteen output buffer, supporting SDRAM
DIMM modules in conjunct ion with the chipset.
Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When enabled, th is feat ure reduces the peak EMI measurement s of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to th em.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, and 46 ar e dual-purpose l/O pi ns. Upon power-up these pi ns act as logic in puts, al lowing the dete rmination
of assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V
latch to “0,” connection to V
Figure 2 show two suggested methods for strapping resistor
connections.
W144
Power-on
Reset
Timer
. Connection to ground sets a
DD
sets a latch to “1.” Fig ure 1 an d
DD
Output
Buffer
Output Three -state
Hold
Output
Low
QD
Data
Latch
Upon W144 power up, the first 2 ms of operation is used for
input logic selection. During th is period, the fiv e I/O pins (7, 8 ,
25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pin and their associated capacitiv e clock load to either a logic HIG H or LOW state . At the
end of the 2ms period, the estab lished logi c “0” or “1” condition
of the l/O pin is latched. Next the output buf fer is enabled con verting the l/O pin s int o opera ting clo ck ou tpu ts. The 2-ms ti mer starts when VDD reaches 2.0V. The input bits can only be
reset by turning VDD off and then bac k on again.
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs are <40Ω (nominal) which is minimally
affected by the 10-kΩ strap to ground or V
ries termination resistor, the output strapping resistor should
. As with the se-
DD
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
should be ke pt less t han tw o i nches i n lengt h t o
DD
prevent system noise coupli ng duri ng input logic sampling.
When the clock out puts are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
full value , output frequency initi ally ma y be belo w target b ut will
increase to target once V
case, a short output clock cycle may be produced from the
has stabilized. If VDD has not yet reached
DD
voltage has stabilized. In either
DD
CPU clock outputs when the outputs are enabled.
V
10 k
(Load Option 1)
10 k
(Load Option 0)
DD
Ω
Ω
Output Strapping Resistor
Series Term ination R es istor
Clock Load
W144
Power-on
Reset
Timer
Figure 1. Input Logic Selecti on Through Resistor Load Option
Jumper Opt ions
Output St rapping Resistor
V
DD
Series Termination Resistor
R
Output
Buffer
Output Three-state
QD
Data
Latch
Hold
Output
Low
10 k
Ω
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Opti on
3
Clock Load
PRELIMINARY
Figure 3. Clock Harmonic with and without SSCG
Modulation Frequency Domain Representation
SSFT G
Typical Clock
Frequency Span (MHz)
-SS%
+SS%
Am plitud e (d B )
5dB/ div
Spread Sp ectrum Feature
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much low er amplitu de than that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is t he percent age of de vi ati on and F is the freq uency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Gener at ion f or t he Reduct ion o f Radiate d Emissi ons ” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in T a bl e 7. Figur e 4
details the Cypress spreading patt ern. Cypress does offer options with more spread and greater EMI reduction. Contact
your local Sales representative for details on th ese devices.
Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the
2
I
C data stream. Refer to Table 7 for more details.
W144
-
MAX (+0.5%)
10%
20%
30%
40%
50%
60%
70%
80%
FREQUENCY
MIN (–0.5%)
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Figure 4. Typical Modulation Profile
4
PRELIMINARY
W144
Serial Data Interface
The W144 features a two-pin, serial data i nterface that can be
used to configure internal register settings that control particular de vice funct ions. Upon po wer-up , the W144 i nitiali zes wit h
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chi p) and i s the dedi cated f unc tion of de v ice pi ns SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
T able 3. Serial Data Interface Control Func ti ons Sum mary
Control Function Description Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled out puts are actively held LOW.
CPU Clock Frequency
Selection
Spread Spectrum
Enabling
Output Three-st ate Puts clock output into a high-impedance sta te. Production PCB testing.
(Reserved) Reserved function for future device revision or
Provides CPU/PCI fr equency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Enables or dis ables spread spectrum cl ocking. For EMI reduction.
production device testing.
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operat ion for power management functions. Ta b le 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W144 in elev en bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence Byte Name Bit Sequence Byte Description
1 Slave Address 11010010 Commands the W144 to accept the bi ts in Data Bytes 0–6 for internal
2 Command Code Don’t Care Unused by the W144, th erefore bit values are ignored (“don’t care”).
3 Byte Count Don’t Care Unused by th e W144 , therefore bit v alues are ignored (“don’t care”).
4 Data Byte 0 Refer to Table 5 The data bit s in Data Bytes 0–7 s et internal W144 regis ters that c ontrol
5 Data Byt e 1
6 Data Byt e 2
7 Data Byt e 3
8 Data Byt e 4
9 Data Byt e 5
10 Data Byte 6
11 Data Byte 7
register co nfigurati on. Since oth er devi ces may e xist on the same common serial dat a bus , it is n ecessary to ha ve a specifi c slav e address for
each potential receiver. The slav e receiver address for the W144 is
11010010. Regist er setting wi ll not be mad e if the Slav e Addr ess is not
correct (or is f or an alternate slave receiver) .
This byte must be included in the data write sequence to maintain
proper by te allocation . The Command Code Byte is part of t he standard
serial communi ca tion protoc ol and ma y be use d whe n writi ng t o a nother addressed slave receiver on the serial data bus.
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard
serial communi ca tion protoc ol and ma y be use d whe n writi ng t o a nother addressed slave receiver on the serial data bus.
device operation. The data bits are only accepted when the Address
Byte bit seq uence is 11010010, as noted above. For description of bit
control f unctions, refer to Table 5, Data Byte Serial Configuration Map.
5
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