Cypress W137H Datasheet

W137

Bx Notebook System Frequency Synthesizer

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum Technology

• T wo copies of CPU output

• Six copies of PCI output (Synch ronous w/CPU output)

• One 48-MHz output for USB support

• One selectable 24-/48-MHz output

• T w o Buffered copies of 14.318-MHz input reference
signal

• Supports 100-MHz or 66-MHz CPU opera ti on

• Power man agement control input pins

• Av ailable in 28-pin SSOP (209 mils)

• SS function can be disabled

• See W40S11-02 for 2 SDRAM DIMM support

Key Specific ati o n s

Supply Voltages:.......................................V

CPU0:1 Output to Output Skew: ........................ ........ 175 ps

CPU0:1 Cycle to Cycle Jit ter:............... .. .................... 200 ps

V

DDQ3
DDQ2

= 3.3V±5%
= 2.5V±5%

Block Diagram

X1
X2

CPU_STOP#

SPREAD#

SEL0
SEL1

SEL133/100#

XTAL

OSC

PLL 1

÷2

÷2/÷1.5

STOP
Clock
Logic

STOP
Clock
Logic

2

4

2

4

REF0:1

CPU0:3

CPUdiv2_0:1

3V66_0:3

PCI_ F, PCI1:5 Out p u t to Ou tp u t Skew : ... .............. ... ....5 0 0 ps

PCI_ F, PCI1:5 Cyc le to Cy c le Jit te r: .. .............. ... .........250 ps

CPU to PCI Output Skew: ...............1.5–4 .0 ns (CPU Leads)

Output Duty Cycle:.................................................... 45/55%

PCI_F, PCI Edge Rate:............................ .. ............... .>

1 V/ns

CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#,
PWR_DWN# all have a 250-kΩ pull-up resistor.

T able 1. Pin Selectable Frequency

SEL100/66# OE CPU PCI Spread%

0/1 0 HI-Z HI-Z Don’t Care

0 1 66.6 MHz 33.3 See
1 1 100 MHz 33.3 See

Table 2
Table 2

Table 2. Spread Spectrum Feature

SPREAD# Spread Profile

0 –0.5% (down spread)
1 0% (spread disable d)

Pin Configuration

GND

X1
X2

PCI_F

PCI1
PCI2
GND

VDDQ3

PCI3
PCI4
PCI5

VDDQ3

48MHz

24/48MHz/OE

1
2
3
4
5
6
7
8
9
10
11
12
13
14

VDDQ3

28

REF0/SEL48#

27

REF1/SPREAD#

26

VDDQ2

25

CPU0

24

CPU1

23

GND

22

GND

21

PCI_STOP#

20

VDDQ3

19

CPU_STOP#

18

PWR_DWN#

17

SEL100/66#

16
15

GND

PWRDWN#

PCI_STOP#

Power

Down

Logic

PLL2

÷2

Three-state

Logic

÷2

Cypress Semiconductor Corporation

1

PCI_F

STOP
Clock

Logic

7

3

1

PCI1:7

IOAPIC0:2

48MHz

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 12, 1999, r ev . **

Pin Definitions

Pin Name

CPU0:1 24, 23 O

PCI1:5 5, 6, 9, 1 0 , 11O

PCI_F 4 O

CPU_STOP# 18 I

PCI_STOP# 20 I

REF0/SEL48# 27 I/O

REF1/SPREAD# 26 I/O

24/48MHz/OE 14 I/O

48MHz 13 O

SEL100/66# 16 I

X1 2 I

X2 3 I

PWR_DWN# 17 I

VDDQ3 8, 12, 19, 28 P
VDDQ2 25 P
GND 1, 7, 15, 21, 22G

Pin
No.

Type Pin Description

Pin

CPU Clock Outputs 0 and 1:

These two CPU clock out puts are controlled by th e
CPU_STOP# control pin. Output volta ge swing is controlled by voltage app li ed to
VDDQ2. Frequency is selected per Table 1.

PCI Bus Clock Outputs 1 through 5:

These five PCI clock outputs are controlled
by the PCI _ST OP# contr ol p in. Outpu t v ol tage s wing is co ntr olle d by v o ltage appli ed
to VDDQ3. Frequency is selected per Table 1.

Fixed PCI Clock Output:

Unlike PCI1:5 outp uts, this output is not controlled b y the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is control led by vol tage appl ied to VDDQ3. F req uency is selected per Table 1.

CPU_STOP# Input:

When brought LOW, clock outputs CPU0:1 are stopped LOW
after completi ng a full clock cycl e (2–3 CPU cloc k latency). When brought HIGH,
clock outputs CPU0:1 start with a full cloc k cycle (2–3 CPU cl o ck l a tency).

PCI_STOP# Input :

The PCI_STO P# input enables the PCI1:5 outputs when HIGH
and causes them to remai n at logi c 0 when LO W. The PCI_STOP# signa l is latc hed
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.

I/O Dual-Function REF0 and SEL48# Pin:

latched. The state i s set b y either a 10K resis tor to GND or to V
GND causes pin 14 to provide a 48-MHz clock. If the pi n is strapped to V

Upon power-up, the state of SEL48# is

. A 10K resistor to

DD

will provide a 24-MHz cl ock. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.

I/O Dual-Function REF1 and SPREAD# Pin:

Upon power-up, the state of
SPREAD# is latched. The state is set by either a 10K resistor to GND or to V
10K resistor to GND enables Spr ead Spectrum function. If the pin is str apped to V
Spread Spectrum is disabled. After 2 ms, the pin beco me s a high- drive output that
produces a copy of 14.318 MHz.

I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input:

power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to
GND or to V
stated. If the pin is strapped to V

. A 10K resistor to GND latches OE LOW, and all outputs are three-

DD

, OE is latched HIGH and all outputs are active.

DD

After 2 ms, the pin becomes an out put whose freque ncy is set b y the state of pin 27
on power-up.

48-MHz Output:

Fixed 48-MHz USB output. Output voltage swing is controll ed by

voltage applied to VDDQ3.

Frequency Selecti on Input:

Select power -up default CPU cloc k frequency as shown

in Table 1 .

Crystal Connection or External Ref erence Frequency Input:

This pin can either

be used as a connection to a crystal or to a reference signal.

Crystal Connection:

An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

Power Down Contr ol:

When thi s input is LO W , de vice goes in to a low-p ower standb y
condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completi ng a full clock cycl e (2–3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full cloc k cycle at full operating frequency
(3 ms maximum latency).

Power Connection:
Power Connection:
Ground Connection:

Connected to 3.3V.
Power suppl y for CPU0:1 output buffers. Connected to 2.5V.

Connect all gro und pins t o the comm on syst em g round pl an e.

W137

, pin 14

DD

DD

Upon

. A

DD

,

2

W137

Overview

The W137 was developed to meet the Intel® Mobile Clock
specification for the BX chipset, including Super I/O and USB
support. The W40S11-02 is the Intel-defined companion part
used for driving 2 SDRAM DIMM modules. Please see that
data sheet for additional information.

Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en­abled, th is feat ure reduces the peak EMI measurement s of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
The –0 .5% modulation pr ofile match es that defined as accep t­able in Intel’s clock specification.

Functional Description

I/O Pin Operation

Pins 14, 26, and 27 ar e dua l-purpose l/ O pins . Upon po wer -up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins then become
clock outputs. This feature reduces device pin count by com­bining cloc k outputs with input selec t pins.

An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or V
latch to “0”, connect ion to V

. Connection to gr ound sets a

DD

sets a latch to “1”. Figure 1 an d

DD

Figure 2 show two suggested methods for strapping resistor
connection.

Upon W137 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the out put buffers are
three-stated, a llowin g the output str apping res istor on ea ch l/O
pin to pull the pin and its associated capacitive clock load to
either a logic HIGH or logic LOW sta te. At the end of the 2-ms
period, the established logic 0 or 1 conditi on of each l/O pin is
then latched. Next, the output buffers are enabled, which con­verts both l/O pins in to operati ng clock output s. The 2- ms timer
is started when V
be reset by turning V

reaches 2.0V. The input latches can only

DD

off and then back on again.

DD

It should be noted that the strapping resistors have no signifi­cant effect on clock output signal integrity. The drive imped­ance of the clock out put i s <
affected by the 10-kΩ strap to ground or V
ries termination resistor, the output strapping resistor should

40Ω (nominal) which is minimally

. As with the se-

DD

be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V

should be ke pt less t han tw o i nches i n lengt h t o

DD

prevent system noise coupli ng during input logic samplin g .
When the clock out puts are enabled following the 2-ms input

period, target ( normal) output f requenc y is deliv ered a ssuming
that V
output frequenc y initi ally ma y be below t arget b ut will in crease
to target once V
short output clock cycle may be produced from the CPU clock

has stabilized. If VDD has not yet reached full value,

DD

voltage has stabilized. In either case, a

DD

outputs when the outputs are enabled.

W137

Power-on
Reset
Timer

W137

Power-on
Reset
Timer

V

Output Three-state

Output
Buffer

QD

Data

Latch

Hold
Output
Low

10 k

(Load Option 1)

10 k

(Load Option 0)

DD

Ω

Ω

Output Strapping Resistor

Series Termination Resistor

R

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

V

DD

Series Termin ation Resistor

R

Output Three-st ate

Output
Buffer

QD

Data

Latch

Hold
Output
Low

10 k

Ω

Clock Load

Clock Load

Figure 2. Input Logic Select ion Thr ough Jum per Option

3