CYPRESS Ultra37000 CPLD User Manual
1Ultra37000 Family
Features
Ultra37000: December 13, 1996
查询CY37256VP256-100BBC供应商
Revision: March 15, 2001
Ultra37000™ CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
—JTAG interface for reconfigurability
—Design changes don’t cause pinout changes
—Design changes don’t cause timi ng changes
• High density
—32 to 512 macrocells
—32 to 264 I/O pins
—5 dedicated inputs including 4 clock pins
• Simple timing model
—No fanout delays
—No expander delays
—No dedicated vs. I/O pin delays
—No additional delay through PIM
—No penalty for using full 16 product terms
—No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI Compatible
• Programmable Bus-Hold capabilities on all I/Os
• Intelligent product term allocator provides:
—0 to 16 product terms to any macrocell
—Product term steering on an individual basis
—Product term sharing among local macrocells
• Flexible clocking
—4 synchronous clocks per device
—Product Term clocking
—Clock polarity control per logic block
• Consistent packa ge/pinout offering across al l densities
—Simplifies design migration
—Same pinout for 3.3V and 5.0V devices
• Packages
—44 to 400 Leads in PLCC, CLCC, PQFP, TQFP , CQFP,
BGA, and Fine-Pitch BGA packages
[1]
General Description
The Ultra37000™ family of CMOS CPLDs provides a ran ge of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flex ibility, ease of use, and p erf ormance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The
PIM distributes signals from the logic block outputs and all input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and InSystem Reprogrammable (ISR), which simplifies both design
and manuf acturing flow s, thereb y reducing cos ts. The ISR f eature provides the ab ility to reconfigu re the dev ices without ha ving design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI
and TDO pins, respec tively. Because of the superior rout ability
and simple timing mo del of the Ultra3 7000 dev ices, ISR allo ws
users to change existing logic designs while simultaneously
fixing pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000
family f ea tures user progr ammab le b us-ho ld capabi lities on al l
I/Os.
Ultra37000 5.0V Devices
The Ultra37000 d evices ope rate with a 5V supply and can support 5V or 3.3V I/O levels. V
pability of inter fa cing to e ither a 5V or 3.3V b us . By connec ting
the V
outputs. If V
3.3V JEDEC standard CMOS levels and are 5V tolerant.
pins to 5V the user insures 5V TTL levels on the
CCO
is connected to 3.3V the output levels meet
CCO
These devices require 5V ISR programming.
Ultra37000V 3.3V Device s
Devices op erating with a 3.3V supply require 3.3V on all V
pins, reducing the device’s power consumption. These devices
support 3.3V JEDEC standard CMOS output levels, and are
5V tolerant. These devices allow 3.3V ISR programming.
connections provide the ca-
CCO
CCO
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
, PCI VIH=2V.
CC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 15, 2001
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Selection Guide
5.0V Selection Guide
General Information
Device Macrocells
CY37032 32 5 32 6 200
CY37064 64 5 32/64 6 200
CY37128 128 5 64/128 6.5 167
CY37192 192 5 120 7.5 154
CY37256 256 5 128/160/192 7.5 154
CY37384 384 5 160/192 10 118
CY37512 512 5 160/192/264 10 118
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032 X X X
CY37064 X X X
CY37128 X X X
CY37192 X X X
CY37256 X X X
CY37384 X X
CY37512 X X X
Dedicated
Inputs I/O Pins Speed (tPD) Speed (f
MAX
)
Device-Package Offering & I/O Count
Device
CY37032 37 37
CY37064 37373769 69
CY37128 69 69 69 133
CY37192 125
CY37256 133 133 165 197
CY37384 165 197
CY37512 165 165 197 269
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
160-
Lead
CQFP
208-
Lead
PQFP
208-
Lead
CQFP
256Lead
BGA
352Lead
BGA
2
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
3.3V Selection Guide
General Information
Device Macrocells
CY37032V 32 5 32 8.5 143
CY37064V 64 5 32/64 8.5 143
CY37128V 128 5 64/80/128 10 125
CY37192V 192 5 120 12 100
CY37256V 256 5 128/160/192 12 100
CY37384V 384 5 160/192 15 83
CY37512V 512 5 160/192/264 15 83
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032V X X
CY37064V X X
CY37128V
CY37192V XX
CY37256V XXX
CY37384V XX
CY37512V
Shaded areas indicate preliminary speed bins.
Dedicated
Inputs I/O Pins Speed (tPD) Speed (f
XX X
XXX
MAX
)
Device-Package Offering & I/O Count
Device
CY37032V 37 37 37
CY37064V3737373769 6969
CY37128V 69 69 69 85 133
CY37192V 125
CY37256V 133 133 165 197 197
CY37384V 165 197
CY37512V 165 165 197 269 269
44-
44-
44-
48-
84-
84-
100-
100-
160-
160-
208-
208-
256-
256-
Lead
TQFP
Lead
PLCC
Lead
CLCC
Lead
Lead
Lead
Lead
Lead
Lead
Lead
Lead
CLCC
TQFP
PLCC
FBGA
TQFP
FBGA
CQFP
Lead
PQFP
BGA
Lead
CQFP
Lead
352-
BGA
Lead
FBGA
400-
Lead
FBGA
3
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the l ogi c blocks. Th e PIM provid es extre mely
robust interconnection to avoid fitting and density limitations.
The inputs to the PIM consist of all I /O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic bloc ks. The output s from the PIM are si gnals routed to
the appropriate logic blocks. Each logic block receives 36 inputs from the PI M and t heir comp lements, allowi ng for 32- bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timi ng. The propagation delay through the PIM is accounted for in the timing
specifications for each device. There is no ad ditional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user . All routing is accomplished b y softw are—no hand routin g
is necessary. Warp™ and third-party development packages
automatically route d esigns for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are f or gener al-purpose use for the
16 macrocells in the logic block. Four of the remaining seven
product terms in the logic b lock are outp ut enable (OE) pro duct
terms. Each of the OE product terms contr ols up to eight of the
16 macrocells and is selectable on an individual macrocell basis. In other w ords, e ach I/O cell can select betw een one of tw o
OE product terms to control the output buffer. The first two of
these four OE product terms are available to the upper half of
the I/O macrocells in a logic block. The other two OE product
terms are available to the lower half of the I/O macrocells in a
logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset p roduct terms. The
final product term is the product term cloc k. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
FROM
PIM
TO
PIM
72 x 87
PRODUCT TERM
ARRAY
3
0−16
PRODUCT
TERMS
7
8036
16
8
PRODUCT
TERM
ALLOCATOR
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
MACRO-
CELL
0
MACRO-
CELL
1
MACRO-
CELL
14
MACRO-
CELL
15
Figure 1. Logic Block with 50% Buried Macrocells
I/O
CELL
0
to cells
2, 4, 6 8, 10, 12
I/O
CELL
14
2
2
4
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator , softw are automatically distributes product terms among the 16 macrocells in the logic
block as ne eded. A total of 80 produc t terms are avai lable from
the local product term array. The product term allocator provides two important capabi lities without aff ecting perf ormance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed . F or example, if one ma crocel l
requires ten product terms while anot her n eeds j ust thre e, th e
product term allocator will “steer” ten product terms to one
macrocell and three to the other . On Ultr a37000 de vices, product terms ar e st e er ed on an ind i vi du al ba s is. A ny numbe r be tween 0 and 16 product terms can be ste ered to any macrocell.
Note that 0 product te rms is useful in c ases wher e a particular
macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the proc ess of using th e same produc t
term am ong multiple macrocell s. For example, if more th an
one output has one or more pro duc t terms in its eq uati on th at
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator allows sharing acr oss gro ups of f our output mac rocells in a v ariable fashion. The software automatically takes advantage of
this capability—the user does not have to intervene.
Note that neither produc t term sharing nor product term steering hav e an y eff ec t on the speed of the p roduct. Al l wor st-case
steering and sharing co nfiguratio ns ha ve be en incorporated in
the timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried M acrocell
Figure 2 displays the architecture of buried macrocells. The
buried macrocel l features a register that can be configur ed as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronou sly set o r asynch ronously reset at the logic b lock le v el with the sepa rate set an d reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based
on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global synchronous clocks and a prod uct term clock are av ailab le to cl ock th e
register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as
rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.
The buried macrocell also supports input register capability.
The buried macr ocell can be confi gured to a ct as a n input re gister (D-type or latch) whose input comes from the I/O pin associated with the neighb oring mac rocell . The o utput o f all b uried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supp orts the same func tions as the buried macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or activ e HIGH si gnals. Th is has the added advan tage of
allowing signi ficant logi c reduction to occur in many appli cations.
The Ultra37000 macroc ell f eatur es a f eedbac k path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an impro v e d v ers ion of the popul ar internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remai n unconn ected on the board, which i s particularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to V
or GND. For more information, see the application note “Understanding Bus-Hold − A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each output has a pro gr amma b le c onf igur ation bit, whic h set s
the output slew rate to f ast or sl ow . F or designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance.
CC
5
Ultra37000: December 13, 1996
Revision: March 15, 2001
f
FROM PTM
0−16
PRODUCT
TERMS
FROM PTM
0−16
PRODUCT
TERMS
0
1
2
3
4
C0
0
1
2
3
4
C0C1
Ultra37000™ CPLD Family
I/O MACROCELL
0
1
C25
P
D/T/L
O
C24
C1
C24
1
0
0
1
C25
Q
1
0
R
BURIED MACROCELL
0
O
1
C7
Q
D/T/L Q
0
1
DECODE
C2 C3
P
R
O
0
1
DECODE
C2 C3
0
1
C4
O
FAST
SLEW
SLOW
C26
O
“0”
“1”
0
1
2
3
C6 C5
I/O CELL
O
ASYNCHRONOUS
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET
POLARITY MUXES
FROM CLOCK
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
Figure 2. I/O and Buried Macrocells
INPUT PIN
0
1
2
3
C10
O
C11
D
Q
D
Q
LE
Figure 3. Input Macrocell
OE0
OE1
0
1
O
D
Q
2
3
C12 C13
TO PIM
6
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
INPUT/CLOCK PIN
FROM CLOCK
POLARITY INPUT
CLOCK PINS
0
1
O
2
3
C8
C9
D
Q
D
Q
LE
D
Figure 4. Input/Clock Macrocell
Clocking
Each I/O and b uried macrocell has a ccess to fou r synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has
access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins o n each membe r of the U ltra 37000 f a mily are desi gnated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user : combinator ial, registe red,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the inpu t pins , inp ut/clo c k pin s can b e comb inatorial, re gistered, double-registered, or latched. In addition, these pins
feed the clocking structures throughout the device. The clock
path at the input has user-configurable polarity.
Product Term Clocking
In addition to th e four synchronous clo cks, the Ultra3700 0 family also has a product term clock for asynchronous clocking.
Each logic b lock has an ind ependent prod uct term cloc k which
is available to all 16 macrocells. Each product term clock also
supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5
illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. F or sync hronous syste ms, the inp ut setup time to the output m acrocells f or an y input is 3.5 n s and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
0
O
1
C12
0
1
O
2
Q
3
C10C11
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO PIM
0
O
1
C13, C14, C15 OR C16
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing dela ys
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
COMBINATORIAL SIGNAL
= 6.5 ns
t
INPUT
PD
REGISTERED SIGNAL
INPUT
CLOCK
tS = 3.5 ns
D,T,L O
t
CO
= 4.5 ns
Figure 5. Timing Model for CY37128
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37 000 f amil y’ s simp le and predi ctab le timing model ensures co mp lia nc e with the PCI AC specific ati on s
independent of the design.
TO CLOCK MUX
IN EACH
LOGIC BLOCK
OUTPUT
OUTPUT
7
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
IEEE 1149.1 Compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample /Preload , Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is sh o w n in Figure 6.
Instruction Register
TDI
TMS
TCK
JTAG
TAP
CONTROLLER
Bypass Reg.
Boundary Scan
idcode
Usercode
ISR Prog.
Data Registers
TDO
Figure 6. JTAG Interface
In-System Reprogramming (ISR)
In-System Reprog ramming is the combinatio n of the capabi lity
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
™
Warp
Warp is a state-of-th e-art compiler and complete CPLD design
tool. For de sign entry , Warp provides an IEEE-STD-1076/1164
VHDL text edito r, an IEEE-STD-1364 V erilog t e xt editor, and a
graphical finite state machine editor. It pro vides o ptimize d synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused
memory and by perfect communication between fitting and
synthesis. To facilitate design and debugging, Warp provides
graphical timing simulation and analysis.
Warp Professional
Warp Professional contains several ad dit ional features. It provides an extra method of design entry with its graphical block
diagram editor. It allows up to 5 ms timing simulation instead
of only 2 ms. It allows comparison of waveforms before and
after design changes.
Warp Enterprise
Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simula-
™
™
tion as well as a deb ugger . It has th e ability to g ener ate gr aphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the Warp for PC, Warp for UNIX , Warp Professional an d
Warp Enterprise data sheets on Cypress’s web site
(www.cypress.com).
Third-P a rty Software
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
Ultra37000 family of devices. Refer to the third-p arty softwar e
data sheet or c ontact y our local sales off ice f or a list of currently supported third-party vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ul tra37000 d evic es are route d to a connector at the edge of the printed circuit bo ard. The 37000 Ultr aISR
programming cable is then connected between the parallel
port of the PC and this connector. A simple configuration file
instructs the ISR software of the programming operations to
be performed on each of the Ultra37000 d evices in the system.
The ISR software then automatically co mp letes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For
more information on the Cypress ISR Interface, see the ISR
Programming Kit data sheet (CY3700i).
The second method f or pro gramming Ultra37000 d evice s is on
automatic test equi pment (ATE). This is accomplished through
a file created b y t he ISR so ftw are . Chec k t he Cy press w eb site
for the latest ISR software download inf ormation.
The third progra mm in g opti on for Ultra37000 devices is to utilize the embedded controller or processor that already exists
in the system. The Ultra37000 ISR software assists in this
method by converting the device JEDEC maps into the ISR
serial stream that contai ns the ISR instru ction inf ormation an d
the addresses and data of locations to be programmed. The
embedded controller t hen simply directs thi s ISR stream to the
chain of Ultra 370 00 d evices to comp lete the desired reconfi guring or diagnostic operations. Contact your local sales office
for information on availability of this option.
The fourth method for programming Ultra37000 devices is to
use the same program m er tha t is cu rren tly bein g us ed to pr o-
370i devices.
LASH
gram F
For all pinout, electrical, and timing requirements, refer to de-
vice data sheets. For ISR cable and software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-P a rty Prog ramm er s
As with de velopment software , Cypress supp ort is avail able on
a wide variety of third-party progr ammers. Al l major thi rd-party
programmers (inc luding BP Micro , Data I/O , and SMS) support
the Ultra37000 family.
8
Ultra37000: December 13, 1996
Revision: March 15, 2001
Logic Block Diagrams
Ultra37000™ CPLD Family
CY37032 / CY37032V
I/O0−I/O
16 I/Os
15
CY37064 / CY37064V (100-Lead TQFP)
0
-I/O
16 I/Os
15
16 I/Os
31
I/O
I/O16-I/O
BLOCK
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
4
LOGIC
A
Clock/
Input
Input
Clock/
Input
4
36
LOGIC
BLOCK
16
4
36
16
36
16
B
16
LOGIC
BLOCK
LOGIC
BLOCK
1
36
16
16
36
16
36
16
PIM
Input
1
PIM
TDI
TCK
TMS
4
4
D
C
16 I/Os
JTAG Tap
Controller
JTAG
I/O
−I/O
16
16 I/Os
16 I/Os
EN
31
I/O48-I/O
I/O32-I/O
TDO
63
47
TDI
TCK
TMS
JTAG Tap
Controller
TDO
32
32
9
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Logic Block Diagrams
(continued)
CY37128 / CY37128V (160-Lead TQFP)
16 I/Os
–I/O
I/O
0
15
I/O16–I/O
I/O32–I/O
I/O28–I/O
16 I/Os
31
16 I/Os
47
16 I/Os
63
CLOCK
INPUTS
INPUTS
41
INPUT
MACROCELL
INPUT/CLOCK
MACROCELLS
4 4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
64
36
16
36
16
PIM
36
16
36
16
36 36
16
36
16
16
36
16
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
LOGIC
BLOCK
64
TDI
TCK
TMS
JTAG Tap
Controller
JTAG
EN
TDO
16 I/Os
I/O
–I/O
112
127
16 I/Os
I/O96–I/O
111
16 I/Os
F
I/O80–I/O
95
16 I/Os
E
I/O64–I/O
79
CY37192 / CY37192V (160-Lead TQFP)
10 I/Os
–I/O
I/O
0
9
10 I/Os
19
10 I/Os
29
10 I/Os
39
10 I/Os
49
10 I/Os
59
TDO
TDI
TCK
TMS
I/O10–I/O
I/O20–I/O
I/O30–I/O
I/O40–I/O
I/O50–I/O
JTAG Tap
Controller
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
Clock/
Input
Input
1
36
16
36
16
36
16
36
16
36
16
36
16
PIM
4
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
LOGIC
BLOCK
H
LOGIC
BLOCK
G
6060
4
10 I/Os
I/O
–I/O
110
119
10 I/Os
I/O
–I/O
100
109
10 I/Os
I/O90–I/O
99
10 I/Os
I/O80–I/O
89
10 I/Os
I/O70–I/O
79
10 I/Os
I/O60–I/O
69
36
16
36
16
36
16
36
16
36
16
36
16
10
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Logic Block Diagrams
(continued)
CY37256 / CY37256V (256-Lead BGA)
12 I/Os
−I/O
I/O
0
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
12 I/Os
−I/O
12
23
12 I/Os
−I/O
24
35
12 I/Os
−I/O
36
47
12 I/Os
−I/O
48
59
12 I/Os
−I/O
60
71
12 I/Os
−I/O
72
83
12 I/Os
−I/O
84
95
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
LOGIC
BLOCK
G
LOGIC
BLOCK
H
Clock/
Input
Input
1
4
4
36
16
36
16
36
16
36
16
36
PIM
16
36
16
36
16
36
16
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
P
LOGIC
BLOCK
O
LOGIC
BLOCK
N
LOGIC
BLOCK
M
LOGIC
BLOCK
L
LOGIC
BLOCK
K
LOGIC
BLOCK
J
LOGIC
BLOCK
I
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
180
168
156
144
132
120
108
96
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
191
179
167
155
143
131
119
107
TDI
TCK
TMS
JTAG Tap
Controller
TDO
96
96
11
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Logic Block Diagrams
(continued)
CY37384 / CY37384V (256-Lead BGA)
12 I/Os
I/O
I/O
−
0
11
12 I/Os
I/O
I/O
−
12
23
12 I/Os
I/O
I/O
−
24
35
12 I/Os
I/O
I/O
−
36
47
12 I/Os
I/O
I/O
−
48
59
12 I/Os
I/O
I/O
−
60
71
12 I/Os
I/O
I/O
−
72
83
12 I/Os
I/O
I/O
−
84
95
4
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
AJ
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
Input
1
PIM
Clock/
Input
4
4
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
BL
LOGIC
BLOCK
BK
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
LOGIC
BLOCK
BD
LOGIC
BLOCK
BC
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
168
156
144
132
120
108
96
96
I/O
−
191
I/O
−
179
I/O
−
167
I/O
−
155
I/O
−
143
I/O
−
131
I/O
−
119
I/O
−
107
TDI
TCK
TMS
JTAG Tap
Controller
TDO
96
96
12
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Logic Block Diagrams
(continued)
CY37512 / CY37512V (352-Lead BGA)
12 I/Os
I/O
I/O
−
0
11
12 I/Os
I/O
−
12
23
12 I/Os
I/O
−
24
35
12 I/Os
I/O
−
36
47
12 I/Os
I/O
−
48
59
12 I/Os
I/O
−
60
71
12 I/Os
I/O
−
72
83
12 I/Os
I/O
−
84
95
12 I/Os
I/O
−
96
107
12 I/Os
I/O
−
119
12 I/Os
I/O
−
131
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
108
120
4
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
AJ
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
LOGIC
BLOCK
AM
LOGIC
BLOCK
AN
LOGIC
BLOCK
AO
LOGIC
BLOCK
AP
Input
Clock/
Input
1
4
4
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
PIM
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
LOGIC
BLOCK
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
BP
LOGIC
BLOCK
BO
LOGIC
BLOCK
BN
LOGIC
BLOCK
BM
LOGIC
BLOCK
BL
LOGIC
BLOCK
BK
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
LOGIC
BLOCK
BD
LOGIC
BLOCK
BC
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
144
252
240
228
216
204
192
180
168
156
132
I/O
−
263
I/O
−
251
I/O
−
239
I/O
−
227
I/O
−
215
I/O
−
203
I/O
−
191
I/O
−
179
I/O
−
167
I/O
−
155
I/O
−
143
TDI
TCK
TMS
JTAG Tap
Controller
132132
TDO
13
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
5.0V Device Characteristics
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage.............................................4.5 to 5.5V
Current into Outputs....................................................16 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Supply Voltage to Ground Potential...............–0.5V to +7.0V
Operating Range
Range
[2]
Ambient
Temperature
[2]
Junction
Temperature
Output
Condition V
CC
V
CCO
Commercial 0°C to +70°C 0°C to +90°C 5V 5V ± 0.25V 5V ± 0.25V
3.3V 5V ± 0.25V 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
Military
[3]
–55°C to +125°C –55°C to +130°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”
3. T
is the “Instant On” case temperature.
A
14
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
5.0V Device Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
V
OH
V
OHZ
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
BHL
I
BHH
I
BHLO
I
BHHO
Inductance
Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)
Output HIGH Voltage with
Output Disabled
Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)
Input HIGH Voltage Guaranteed Input Logical HIGH Voltage
Input LOW Voltage Guaranteed Input Logical LOW Voltage
Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10
Output Leakage Current VO = GND or VCC, Output Disabled,
Output Short Circuit
[8, 5]
Current
Input Bus-Hold LO W
Sustaining Current
Input Bus-Hold HIGH
Sustaining Current
Input Bus-Hold LO W Ov erdrive
Current
Input Bus-Hold HIGH Ov erdrive
Current
[5]
Parameter Description
L Maximum Pin
Inductance
Capacitance
[5]
[5]
Test
Conditions
VIN = 5.0V
at f = 1 MHz
IOH = –2.0 mA (Mil)
VCC = Max. IOH = 0 µA (Com’l)
IOH = 0 µA (Ind/Mil)
IOH = –100 µA (Com’l)
IOH = –150 µA (Ind/Mil)
[4]
for all Inputs
for all Inputs
IOL = 12 mA (Mil)
[7]
[7]
Bus-Hold Disabled
VCC = Max., V
= 0.5V –30 –160 mA
OUT
VCC = Min., VIL = 0.8V +75
VCC = Min., VIH = 2.0V –75
VCC = Max. +500
VCC = Max. –500
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
2 5 2 8 5 8 9 11 nH
[4]
2.4 V
[4]
[6]
[6]
[6]
[6]
2.4 V
[4]
4.2 V
4.5 V
3.6 V
3.6 V
0.5 V
0.5 V
2.0 V
CCmax
–0.5 0.8 V
–50 50
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
208-
Lead
PQFP Unit
V
µ
µA
µA
µA
µA
µA
A
Parameter Description Test Conditions Max. Unit
C
I/O
C
CLK
C
DP
Endurance Characteristics
Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 10 pF
Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 12 pF
Dual Function Pins
[5]
[9]
VIN = 5.0V at f = 1 MHz at TA = 25°C 16 pF
Parameter Description Test Conditions Min. Typ. Unit
N Minimum Reprogramming Cycles Normal Programming Conditions
Notes:
= –2 mA, IOL = 2 mA for TDO.
4. I
OH
5. Tested initially and after any design or process changes that may affect these parameters.
6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
9. Dual pins are I/O with JTAG pins.
[2]
1,000 10,000 Cycles
= 0.5V has been chosen to avoid test
OUT
15
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
3.3V Device Characteristics
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Po wer Applied.............................................–55°C to +125°C
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage.............................................3.0 to 3.6V
Current into Outputs......................................................8 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Supply Voltage to Ground Potential...............–0.5V to +4.6V
Operating Range
[2]
Range Ambient Temperature
[2]
Junction Temperature V
CC
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 3.3V ± 0.3V
[3]
Military
3.3V Device Electrical Characteristics
–55°C to +125°C –55°C to +130°C 3.3V ± 0.3V
Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
[4]
[4]
[4]
[4]
2.4 V
0.5 V
2.0 5.5 V
–0.5 0.8 V
–50 50
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
BHL
I
BHH
I
BHLO
I
BHHO
Inductance
Output HIGH Voltage VCC = Min. IOH = –4 mA (Com ’l)
IOH = –3 mA (Mil)
Output LOW Voltage VCC = Min. IOL = 8 mA (Com’l)
IOL = 6 mA (Mil)
Input HIGH Voltage Guaranteed Input Lo gical HIGH V oltage for
all Inputs
Input LOW Voltage Guaranteed Inpu t Logical LO W Voltage for
all Inputs
[7]
[7]
Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10
Output Leakage Current VO = GND or VCC, Output Disabled,
Bus-Hold Disabled
Output Short Circuit Current
Input Bus-Hold LOW Sustaining
[8, 5]
VCC = Max., V
= 0.5V –30 –160 mA
OUT
VCC = Min., VIL = 0.8V +75
Current
Input Bus-Hold HIGH Sustaining
VCC = Min., VIH = 2.0V –75
Current
Input Bus-Hold LOW Overdrive
VCC = Max. +500
Current
Input Bus-Hold HIGH Overdrive
VCC = Max. –500
Current
[5]
µ
µ
µA
µA
µ
µA
A
A
A
Parameter Description
L Maximum Pin
Inductance
Test
Conditions
VIN = 3.3V
at f = 1 MHz
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
208-
Lead
PQFP Unit
2 5 2 8 5 8 9 11 nH
16
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Capacitance
[5]
Parameter Description Test Conditions Max. Unit
C
I/O
C
CLK
C
DP
Endurance Characteristics
Input/Output Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 8 pF
Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 12 pF
Dual Functional Pins
[5]
[9]
VIN = 3.3V at f = 1 MHz at TA = 25°C 16 pF
Parameter Description Test Conditions Min. Typ. Unit
N Minimum Reprogramming Cycles Normal Programming Conditions
[2]
1,000 10,000 Cycles
AC Characteristics.
5.0V AC Test Loads and Waveforms
5 pF
238Ω (COM'L)
319Ω(MIL)
170Ω (COM'L)
236Ω(MIL)
3.0V
GND
ALL INPUT PULSES
90%
10%
<2 ns
(c)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
238Ω (COM'L)
319Ω(MIL)
35 pF
170Ω (COM'L)
236Ω(MIL)
(a) (b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
90%
10%
<2 ns
Equivalent to: THÉVENIN EQUIVALENT
99Ω (COM'L)
136Ω (MIL)
OUTPUT
5 OR 35 pF
3.3V AC Test Loads and Waveforms
295Ω (COM'L)
35 pF
393Ω(MIL)
340Ω (COM'L)
453Ω(MIL)
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
(a) (b)
Equivalent to: THÉVENIN EQUIVALENT
158Ω (COM’L)
OUTPUT
270Ω (MIL)
5 OR 35 pF
2.08V (COM'L)
2.13V (MIL)
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1.77V (COM'L)
1.77V (MIL)
5 pF
295Ω (COM'L)
393Ω(MIL)
340Ω (COM'L)
453Ω(MIL)
3.0V
GND
<2 ns
ALL INPUT PULSES
90%
10%
(c)
90%
10%
<2 ns
17
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
t
ER(–)
t
ER(+)
t
EA(+)
t
EA(–)
[10]
V
1.5V
2.6V
1.5V
V
the
X
Parameter
(d) Test Waveforms
Note:
measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
10. t
ER
Output Wave form—Measurement Level
V
OH
0.5V
0.5V
V
OL
0.5V
V
X
V
X
0.5V
V
X
V
X
V
OH
V
OL
18
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Switching Characteristics
Over the Operating Range
[11]
Parameter Description Unit
Combinatorial Mode Param ete r s
[12, 13, 14]
t
PD
[12, 13, 14]
t
PDL
t
PDLL
[12, 13, 14]
t
EA
[10, 12]
t
ER
[12, 13, 14]
Input to Combinatorial Output ns
Input to Output Through Transparent Input or Output Latch ns
Input to Output Through Transparent Input and Output Latches ns
Input to Output Enable ns
Input to Output Disable ns
Input Register Para meters
t
WL
t
WH
t
IS
t
IH
t
ICO
t
ICOL
[12, 13, 14]
[12, 13, 14]
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time ns
Input Register or Latch Hold Time ns
Input Register Clock or Latch Enable to Combinatorial Output ns
Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
[8]
[8]
Synchronous Clocking Parameters
[13, 14]
t
CO
t
S
t
H
t
CO2
t
SCS
t
SL
t
HL
[12]
[12]
[12, 13, 14]
[12]
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output ns
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns
Register or Latch Data Hold Time ns
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinat orial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enab le to Outp ut Synchro nous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
Set-Up Time from Inpu t Through Transparent Latch to Output Regis ter Synch ronous Cloc k (CLK0
, CLK2, or CLK3) or Latch Enable
CLK
1
Hold Time for Input Throug h Transparent Latch from Output Register Synchrono us Clock (CLK0,
, CLK2, or CLK3) or Latch Enable
CLK
1
Product Term Clocking Parameters
[12, 13, 14]
t
COPT
t
SPT
t
HPT
t
ISPT
t
IHPT
t
CO2PT
[12]
[12, 13, 14]
Product Term Clock or Latch Enable (PTCLK) to Output ns
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns
Register or Latch Data Hold Time ns
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time ns
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns
Pipelined Mode Parameters
[12]
t
ICS
Notes:
11. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
12. Logic Blocks operating in Low-Power Mode, add t
13. Outputs using Slow Output Slew Rate, add t
14. When V
= 3.3V, add t
CCO
Input Register Synchronou s Cloc k (CLK0, CLK1, CLK2, or CLK3) to Output Regist er Synchro nous
Clock (CLK0, CLK1, CLK2, or CLK3)
to this spec.
LP
to this spec.
to this spec.
3.3IO
SLEW
ns
ns
ns
ns
ns
ns
ns
ns
19
Ultra37000: December 13, 1996
Revision: March 15, 2001
Ultra37000™ CPLD Family
Switching Characteristics
Over the Operating Range
[11]
(continued)
Parameter Description Unit
Operating Frequency Parameters
f
MAX1
f
MAX2
f
MAX3
f
MAX4
Maximum Frequency with Internal Feedback (Lesser of 1/t
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),
+ tH), or 1/tCO)
1/(t
S
[5]
, 1/(tS + tH), or 1/tCO)
SCS
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)
Maximum Frequency in Pipelin ed M ode (Les se r of 1/(tCO + tIS), 1/t
or 1/t
SCS
[5]
)
, 1/(tWL + tWH), 1/(tIS + tIH),
ICS
[5]
[5]
Reset/Preset Parameters
t
RW
[12]
t
RR
[12, 13, 14]
t
RO
t
PW
[12]
t
PR
[12, 13, 14]
t
PO
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Output ns
Asynchronous Preset Width
Asynchronous Preset Recovery Time
Asynchronous Preset to Output ns
[5]
[5]
[5]
[5]
User Option Parameter s
t
LP
t
SLEW
t
3.3IO
Low Power Adder ns
Slow Output Slew Rate Adder ns
3.3V I/O Mode Timing Adder
[5]
JTAG Timing Parameters
t
S JTAG
t
H JTAG
tCO
f
JTAG
JTAG
Set-Up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
Falling Edge of TCK to TDO
[5]
[5]
Maximum JTAG Tap Controller Frequency
[5]
[5]
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
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