Cypress STK22C48 User Manual
STK22C48
16 Kbit (2K x 8) AutoStore nvSRAM
Features
STORE/
RECALL
CONTROL
POWER
CONTROL
STATIC RAM
ARRAY
32 X 512
Quantum Trap
32 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
0
1
2
3
4
5
6
7
Logic Block Diagram
Functional Description
■ 25 ns and 45 ns access times
■ Hands off automatic STORE on power down with external 68
µF capacitor
■ STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■ RECALL to SRAM initiated by software or power up
■ Unlimited Read, Write, and Recall cycles
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5V+10% operation
■ Commercial and industrial temperatures
■ 28-pin 300 mil and (330 mil) SOIC package
■ RoHS compliance
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent n onvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware ST ORE is initiated with
the HSB
pin.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-51000 Rev. ** Revised January 30, 2009
[+] Feedback
STK22C48
Pin Configurations
V
CAP
A
7
A
6
A
5
A
4
V
CC
HSB
WE
A
8
A
9
OE
A
10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
SS
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions
Pin Name Alt IO Type Description
A
0–A10
DQ
-DQ
0
7
WE
CE
OE
V
V
SS
CC
W
E
G
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Input Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Input Chip Enable Input, Active LOW . When LOW, select s the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE
HIGH causes the IO pins to tri-state.
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware S tore is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51000 Rev. ** Page 2 of 14
[+] Feedback
STK22C48
Device Operation
9FF
9
&$3
PK
2N
)
5
Y
PK2N
:(
+6%
9VV
)
5
VVDS\
%
The STK22C48 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE
pins A
0–10
Read is initiated by an address transition, the outputs are valid
after a delay of t
or OE, the outputs are valid at t
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
tions on any control input pins, and remains valid until a nother
and HSB are HIGH. The address specified on
determines the 2,048 data bytes accessed. When the
(Read cycle 1). If the Read is initiated by CE
AA
access time without the need for transi-
AA
ACE
or at t
, whichever is later
DOE
address change or until CE or OE is brought HIGH, or WE or
HSB
is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
is HIGH. The address inputs must be stable prior to entering
HSB
the Write cycle and must remain stable until either CE
or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE
are written into the memory if it has valid tSD, before
0–7
controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE
internal circuitry turns off the output buffers t
LOW.
HZWE
is left LOW ,
after WE goes
AutoStore Operation
During normal operation, the device draws current from VCC to
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2 shows the proper connection of the storage capacitor
(V
) for automatic store operation. A charge storage capacitor
CAP
between 68 µF and 220 µF (+
pin drops below V
CC
pin from VCC. A STORE
CAP
20%) rated at 6V should be
pin. This stored
CAP
, the part
SWITCH
capacitor.
CAP
Figure 2. AutoStore Mode
In system power mode, both VCC and V
+5V power supply without the 68 μF capacitor. In this mode, the
are connected to the
CAP
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the 10 ms
STORE
cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB
unless at least one
recent STORE
shown connected to HSB
WRITE operation takes place since the most
or RECALL cycle. An optional pull up resistor is
. This is used to signal the system that
LOW are ignored,
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
(Figure3). This is
CAP
disabled. If the STK22C48 is operated in this configuration, references to V
In this mode, STORE
are changed to V
CC
operations are triggered with the HSB pin.
throughout this data sheet.
CAP
It is not permissible to change between these three options “on
the fly”.
CC
Document Number: 001-51000 Rev. ** Page 3 of 14
[+] Feedback
STK22C48
Figure 3. AutoStore Inhibit Mode
Data Protection
VVDS\%
)
5
9
&$3
9VV
9FF
:(
+6%
PK2N
PK2N
Hardware STORE (HSB) Operation
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
LOW, the STK22C48 conditionally initiates a STORE operation
after t
SRAM takes place since the last STORE or RECALL cycle. The
. An actual STORE cycle only begins if a Write to the
DELAY
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull up this pin with an external 10K
ohm resistor to V
if HSB is used as a driver.
CAP
SRAM Read and Write operations, that are in progress when
is driven LOW by any means, are given time to complete
HSB
before the STORE operation is initiated. After HSB
the STK22C48 continues SRAM operations for t
, multiple SRAM Read operations take place. If a Write is
t
DELAY
in progress when HSB
is pulled LOW, it allows a time, t
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB
returns HIGH.
is not used, it is left unconnected.
If HSB
pin is used to
pin is driven
goes LOW,
. During
DELAY
to
DELAY
pin LOW, releasing it
pin
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
less than V
and WE are low) at power up after a RECALL or after a STORE,
. If the STK22C48 is in a Write mode (both CE
SWITCH
the Write is inhibited until a negative transition on CE
is
CC
or WE is
detected. This protects against inadvertent writes during power
up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and V
as possible. As with all high speed CMOS ICs, careful routing of
using leads and traces that are as short
SS,
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage conditions. When V
operations and SRAM Writes are inhibited. AutoStore can be
CAP<VSWITCH
, all externally initiated STORE
completely disabled by tying VCC to ground and applying +5V to
V
. This is the AutoStore Inhibit mode; in this mode, STOREs
CAP
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK22C48 depends on the
following items:
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of Reads to Writes
■ CMOS versus TTL input levels
■ The operating temperature
■ The V
■ IO loading
CC
level
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When V
RESET
SWITCH
HRECALL
, a RECALL
to complete.
CC
Document Number: 001-51000 Rev. ** Page 4 of 14
[+] Feedback
STK22C48
Figure 4. Current Versus Cy c le Time (Read)
Notes
1. I/O state assumes OE
< VIL. Activation of nonvolatile cycles does not depend on state of OE.
2. HSB
STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode,
inhibiting all operations until HSB
rises.
Figure 5. Current Versus Cyc le Time (Write)
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it must overpower the internal pull down device. This
Table 2. Hardware Mode Selection
of at least 2.2V,
OH
device drives HSB
LOW for 20 ns at the onset of a STORE.
When the STK22C48 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on V
and V
attempts to pull HSB
V
attempt.
crosses V
CC
, the part stops trying to pull HSB LOW and abort the STORE
IL
on the way down, the STK22C48
SWITCH
LOW. If HSB does not actually get below
CAP
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these v alues. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume that an NV array is
in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■ The V
and a maximum value size. The best practice is to meet this
requirement and not exceed the maximum V
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
V
CAP
discuss their V
value specified in this data sheet includes a minimum
CAP
value because
CAP
value to make sure there is extra store charge should
size selection with Cypress.
CAP
)
CE WE HSB A10–A0 Mode IO Power
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z I
Document Number: 001-51000 Rev. ** Page 5 of 14
CC2
[1]
[2]
[+] Feedback
Loading...