STK22C48
16 Kbit (2K x 8) AutoStore nvSRAM
Features
STORE/
RECALL
CONTROL
POWER
CONTROL
STATIC RAM
ARRAY
32 X 512
Quantum Trap
32 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
0
1
2
3
4
5
6
7
Logic Block Diagram
Functional Description
■ 25 ns and 45 ns access times
■ Hands off automatic STORE on power down with external 68
µF capacitor
■ STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■ RECALL to SRAM initiated by software or power up
■ Unlimited Read, Write, and Recall cycles
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5V+10% operation
■ Commercial and industrial temperatures
■ 28-pin 300 mil and (330 mil) SOIC package
■ RoHS compliance
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent n onvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware ST ORE is initiated with
the HSB
pin.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-51000 Rev. ** Revised January 30, 2009
[+] Feedback
STK22C48
Pin Configurations
V
CAP
A
7
A
6
A
5
A
4
V
CC
HSB
WE
A
8
A
9
OE
A
10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
SS
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions
Pin Name Alt IO Type Description
A
0–A10
DQ
-DQ
0
7
WE
CE
OE
V
V
SS
CC
W
E
G
HSB
V
CAP
NC No Connect No Connect. This pin is not connected to the die.
Input Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Input Chip Enable Input, Active LOW . When LOW, select s the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE
HIGH causes the IO pins to tri-state.
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware S tore is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51000 Rev. ** Page 2 of 14
[+] Feedback
STK22C48
Device Operation
9FF
9
&$3
PK
2N
)
5
Y
PK2N
:(
+6%
9VV
)
5
VVDS\
%
The STK22C48 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE
pins A
0–10
Read is initiated by an address transition, the outputs are valid
after a delay of t
or OE, the outputs are valid at t
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
tions on any control input pins, and remains valid until a nother
and HSB are HIGH. The address specified on
determines the 2,048 data bytes accessed. When the
(Read cycle 1). If the Read is initiated by CE
AA
access time without the need for transi-
AA
ACE
or at t
, whichever is later
DOE
address change or until CE or OE is brought HIGH, or WE or
HSB
is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
is HIGH. The address inputs must be stable prior to entering
HSB
the Write cycle and must remain stable until either CE
or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE
are written into the memory if it has valid tSD, before
0–7
controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE
internal circuitry turns off the output buffers t
LOW.
HZWE
is left LOW ,
after WE goes
AutoStore Operation
During normal operation, the device draws current from VCC to
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2 shows the proper connection of the storage capacitor
(V
) for automatic store operation. A charge storage capacitor
CAP
between 68 µF and 220 µF (+
pin drops below V
CC
pin from VCC. A STORE
CAP
20%) rated at 6V should be
pin. This stored
CAP
, the part
SWITCH
capacitor.
CAP
Figure 2. AutoStore Mode
In system power mode, both VCC and V
+5V power supply without the 68 μF capacitor. In this mode, the
are connected to the
CAP
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the 10 ms
STORE
cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB
unless at least one
recent STORE
shown connected to HSB
WRITE operation takes place since the most
or RECALL cycle. An optional pull up resistor is
. This is used to signal the system that
LOW are ignored,
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
(Figure3). This is
CAP
disabled. If the STK22C48 is operated in this configuration, references to V
In this mode, STORE
are changed to V
CC
operations are triggered with the HSB pin.
throughout this data sheet.
CAP
It is not permissible to change between these three options “on
the fly”.
CC
Document Number: 001-51000 Rev. ** Page 3 of 14
[+] Feedback
STK22C48
Figure 3. AutoStore Inhibit Mode
Data Protection
VVDS\%
)
5
9
&$3
9VV
9FF
:(
+6%
PK2N
PK2N
Hardware STORE (HSB) Operation
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
LOW, the STK22C48 conditionally initiates a STORE operation
after t
SRAM takes place since the last STORE or RECALL cycle. The
. An actual STORE cycle only begins if a Write to the
DELAY
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull up this pin with an external 10K
ohm resistor to V
if HSB is used as a driver.
CAP
SRAM Read and Write operations, that are in progress when
is driven LOW by any means, are given time to complete
HSB
before the STORE operation is initiated. After HSB
the STK22C48 continues SRAM operations for t
, multiple SRAM Read operations take place. If a Write is
t
DELAY
in progress when HSB
is pulled LOW, it allows a time, t
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB
returns HIGH.
is not used, it is left unconnected.
If HSB
pin is used to
pin is driven
goes LOW,
. During
DELAY
to
DELAY
pin LOW, releasing it
pin
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
less than V
and WE are low) at power up after a RECALL or after a STORE,
. If the STK22C48 is in a Write mode (both CE
SWITCH
the Write is inhibited until a negative transition on CE
is
CC
or WE is
detected. This protects against inadvertent writes during power
up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and V
as possible. As with all high speed CMOS ICs, careful routing of
using leads and traces that are as short
SS,
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage conditions. When V
operations and SRAM Writes are inhibited. AutoStore can be
CAP<VSWITCH
, all externally initiated STORE
completely disabled by tying VCC to ground and applying +5V to
V
. This is the AutoStore Inhibit mode; in this mode, STOREs
CAP
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK22C48 depends on the
following items:
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of Reads to Writes
■ CMOS versus TTL input levels
■ The operating temperature
■ The V
■ IO loading
CC
level
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When V
RESET
SWITCH
HRECALL
, a RECALL
to complete.
CC
Document Number: 001-51000 Rev. ** Page 4 of 14
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STK22C48
Figure 4. Current Versus Cy c le Time (Read)
Notes
1. I/O state assumes OE
< VIL. Activation of nonvolatile cycles does not depend on state of OE.
2. HSB
STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode,
inhibiting all operations until HSB
rises.
Figure 5. Current Versus Cyc le Time (Write)
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it must overpower the internal pull down device. This
Table 2. Hardware Mode Selection
of at least 2.2V,
OH
device drives HSB
LOW for 20 ns at the onset of a STORE.
When the STK22C48 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on V
and V
attempts to pull HSB
V
attempt.
crosses V
CC
, the part stops trying to pull HSB LOW and abort the STORE
IL
on the way down, the STK22C48
SWITCH
LOW. If HSB does not actually get below
CAP
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these v alues. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume that an NV array is
in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■ The V
and a maximum value size. The best practice is to meet this
requirement and not exceed the maximum V
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
V
CAP
discuss their V
value specified in this data sheet includes a minimum
CAP
value because
CAP
value to make sure there is extra store charge should
size selection with Cypress.
CAP
)
CE WE HSB A10–A0 Mode IO Power
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z I
Document Number: 001-51000 Rev. ** Page 5 of 14
CC2
[1]
[2]
[+] Feedback
STK22C48
Maximum Ratings
Notes
3. V
CC
reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V
CAP
if VCC is connected to ground.
4. CE
> VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Temperature under bias..............................–55°C to +125°C
Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to V
CC
+ 0.5V
Voltage on DQ
or HSB .......................–0.5V to Vcc + 0.5V
0-7
Power Dissipation .........................................................1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V
CC
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
[3]
Parameter Description Test Conditions Min Max Unit
I
CC1
I
CC2
I
CC3
Average VCC Current tRC = 25 ns
= 45 ns
t
RC
Dependent on output loading and cycle
rate. Values obtained without output loads.
I
= 0 mA.
OUT
Average VCC Current during
STORE
Average VCC Current at tRC=
200 ns, 5V, 25°C Typical
All Inputs Do Not Care, VCC = Max
Average current for duration t
WE > (VCC – 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values
STORE
Commercial 8565mA
mA
Industrial 9065mA
mA
3mA
10 mA
obtained without output loads.
I
CC4
I
SB1
[4]
Average V
AutoStor e Cycle
Current during
CAP
Average Vcc Current
(Standby, Cycling TTL Input
Levels)
All Inputs Do Not Care, VCC = Max
Average current for duration t
tRC = 25 ns, CE > V
tRC = 45 ns, CE > V
IH
IH
STORE
2mA
Commercial 2518mA
mA
Industrial 2619mA
mA
I
SB2
[4]
VCC Standby Current CE > (VCC – 0.2V). All others V
Standby current level after nonvolatile cycle is complete.
< 0.2V or > (VCC – 0.2V).
IN
1.5 mA
Inputs are static. f = 0 MHz.
I
ILK
I
OLK
V
V
V
V
V
V
IH
IL
OH
OL
BL
CAP
Input Leakage Current VCC = Max, VSS < V
Off State Output Leakage
VCC = Max, VSS < V
Current
< V
IN
CC
< VCC, CE or OE > V
IN
or WE < V
IH
-1 +1 μA
IL
-5 +5 μA
Input HIGH Voltage 2.2 VCC +
0.5
Input LOW Voltage VSS – 0.5 0.8 V
Output HIGH Voltage I
Output LOW Voltage I
Logic ‘0’ Voltage on HSB Output I
Storage Capacitor Between V
= –4 mA except HSB 2.4 V
OUT
= 8 mA except HSB 0.4 V
OUT
= 3 mA 0.4 V
OUT
nom.
pin and Vss, 6V rated. 68 uF -10%, +20%
CAP
61 220 µF
V
Data Retention and Endurance
Parameter Description Min Unit
DATA
R
NV
C
Document Number: 001-51000 Rev. ** Page 6 of 14
Data Retention 100 Years
Nonvolatile STORE Operations 1,000 K
[+] Feedback
STK22C48
Capacitance
5.0V
Output
30 pF
R1 963Ω
R2
512Ω
5.0V
Output
5 pF
R1 963
Ω
R2
512
Ω
For Tri-state Specs
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <
5 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
5. These parameters are guaranteed by design and are not tested.
In the following table, the capacitance parameters are listed.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
Output Capacitance 7pF
CC
[5]
8pF
= 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter Description Test Conditions
Θ
Θ
JA
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
Figure 6. AC Test Loads
[5]
AC Test Conditions
28-SOIC
(300 mil)
TBD TBD °C/W
TBD TBD °C/W
28-SOIC
(330 mil)
Unit
Document Number: 001-51000 Rev. ** Page 7 of 14
[+] Feedback
STK22C48
AC Switching Characteristics
W
5&
W
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W
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W
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W
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W
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Notes
6. WE
and HSB must be High during SRAM Read cycles.
7. Device is continuously selected with CE
and OE both Low.
8. Measured ±200 mV from steady state output voltage.
SRAM Read Cycle
Parameter
Cypress
Parameter
t
ACE
[6]
t
RC
[7]
t
AA
t
DOE
[7]
t
OHA
[8]
t
LZCE
[8]
t
HZCE
[8]
t
LZOE
[8]
t
HZOE
[5]
t
PU
[5]
t
PD
t
t
t
t
t
t
t
t
t
t
t
Alt
ELQV
AVAV, tELEH
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
Chip Enable Access Time 25 45 ns
Read Cycle Time 25 45 ns
Address Access Time 25 45 ns
Output Enable to Data Valid 10 20 ns
Output Hold After Address Change 5 5 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 10 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 10 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 25 45 ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
Description
25 ns 45 ns
Min Max Min Max
[6, 7]
Unit
Document Number: 001-51000 Rev. ** Page 8 of 14
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
[6]
[+] Feedback
STK22C48
SRAM Write Cycle
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
9. If WE
is Low when CE goes Low, the outputs remain in the high impedance state.
10.HSB
must be high during SRAM Write cycles.
11.
CE
or WE must be greater than VIH during address transitions.
Parameter
Cypress
Parameter
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
[8,9]
t
HZWE
[8]
t
LZWE
t
AVAV
t
WLWH, tWLEH
t
ELWH, tELEH
t
DVWH, tDVEH
t
WHDX, tEHDX
t
AVWH, tAVEH
t
AVWL, tAVEL
t
WHAX, tEHAX
t
WLQZ
t
WHQX
Alt
Switching Waveforms
25 ns 45 ns
Description
Min Max Min Max
Write Cycle Time 25 45 ns
Write Pulse Width 20 30 ns
Chip Enable To End of Write 20 30 ns
Data Setup to End of Write 10 15 ns
Data Hold After End of Write 0 0 ns
Address Setup to End of Write 20 30 ns
Address Setup to Start of Write 0 0 ns
Address Hold After End of Write 0 0 ns
Write Enable to Output Disable 10 14 ns
Output Active After End of Write 5 5 ns
Figure 9. SRAM Write Cycle 1: WE Controlled
[10, 11]
Unit
Document Number: 001-51000 Rev. ** Page 9 of 14
Figure 10. SRAM Write Cycle 2: CE Controlled
[10, 11]
[+] Feedback
STK22C48
AutoStore or Power Up RECALL
WE
Notes
12.t
HRECALL
starts from the time VCC rises above V
SWITCH
.
13.CE
and OE low for output behavior.
14.CE
and OE low and WE high for output behavior.
15.HSB
is asserted low for 1us when V
CAP
drops through V
SWITCH
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store
takes place.
Parameter Alt Description
[13]
[10]
[12]
[14, 15]
t
RESTORE
t
HLHZ
t
HLQZ , tBLQZ
Power up RECALL Duration 550 μs
STORE Cycle Duration 10 ms
Time Allowed to Complete SRAM Cycle 1 μs
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.6 V
Low Voltage Trigger (V
t
HRECALL
t
STORE
t
DELAY
V
SWITCH
V
RESET
t
VSBL
Switching Waveform
Figure 11. AutoStore/Power Up RECALL
STK22C48
Min Max
) to HSB Low 300 ns
SWITCH
Unit
Document Number: 001-51000 Rev. ** Page 10 of 14
[+] Feedback
STK22C48
Hardware STORE Cycle
Note
16.t
DHSB
is only applicable after t
STORE
is complete.
Parameter Alt Description
[13, 16]
t
DHSB
t
PHSB
t
HLBL
t
RECOVER, tHHQX
t
HLHX
Hardware STORE High to Inhibit Off 700 ns
Hardware STORE Pulse Width 15 n s
Hardware STORE Low to STORE Busy 300 ns
Switching Waveform
Figure 12. Hardware STORE Cycle
STK22C48
Min Max
Unit
Document Number: 001-51000 Rev. ** Page 11 of 14
[+] Feedback
STK22C48
Ordering Information
Packaging Option:
TR = Tape and Reel
Blank = Tube
Speed:
25 - 25 ns
45 - 45 ns
Package:
S = Plastic 28-pin 330 mil SOIC
STK22C48 - N F 45 I TR
Temperature Range:
Blank - Commercial (0 to 70°C)
N = Plastic 28-pin 300 mil SOIC
Lead Finish
F = 100% Sn (Matte Tin)
I - Industrial (-40 to 85°C)
Speed (ns) Ordering Code Package Diagram Package Type Operating Range
25 STK22C48-NF25TR 51-85026 28-pin SOIC (300 mil) Commercial
STK22C48-NF25 51-85026 28-pin SOIC (300 mil)
STK22C48-SF25TR 51-85058 28-pin SOIC (330 mil)
STK22C48-SF25 51-85058 28-pin SOIC (330 mil)
STK22C48-NF25ITR 51-85026 28-pin SOIC (300 mil) Industrial
STK22C48-NF25I 51-85026 28-pin SOIC (300 mil)
45 STK22C48-NF45TR 51-85026 28-pin SOIC (300 mil) Commercial
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
STK22C48-SF25ITR 51-85058 28-pin SOIC (330 mil)
STK22C48-SF25I 51-85058 28-pin SOIC (330 mil)
STK22C48-NF45 51-85026 28-pin SOIC (300 mil)
STK22C48-SF45TR 51-85058 28-pin SOIC (330 mil)
STK22C48-SF45 51-85058 28-pin SOIC (330 mil)
STK22C48-NF45ITR 51-85026 28-pin SOIC (300 mil) Industrial
STK22C48-NF45I 51-85026 28-pin SOIC (300 mil)
STK22C48-SF45ITR 51-85058 28-pin SOIC (330 mil)
STK22C48-SF45I 51-85058 28-pin SOIC (330 mil)
Document Number: 001-51000 Rev. ** Page 12 of 14
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STK22C48
Package Diagrams
PIN 1 ID
0.291[7.39]
0.300[7.62]
0.394[10.01]
0.419[10.64]
0.050[1.27]
TYP.
0.092[2.33]
0.105[2.67]
0.004[0.10]
0.0118[0.30]
SEATING PLANE
0.0091[0.23]
0.0125[3.17]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
0.026[0.66]
0.032[0.81]
0.697[17.70]
0.713[18.11]
0.004[0.10]
114
15 28
*
*
*
PART #
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
MIN.
MAX.
NOTE :
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
3. DIMENSIONS IN INCHES
4. PACKAGE WEIGHT 0.85gms
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
51-85026-*D
51-85058-*A
Figure 13. 28-Pin (300 mil) SOIC (51-85026)
Document Number: 001-51000 Rev. ** Page 13 of 14
Figure 14. 28-Pin (330 mil) SOIC (51-85058)
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STK22C48
Document History Page
Document Title: STK22C48 16 Kbit (2K x 8) AutoStore nvSRAM
Document Number: 001-51000
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 2625139 GVCH/PYRS 01/30/09 New data sheet
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006- 2009. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warrant ed no r int e nded to be used fo r
medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express writte n agreement with Cypress. Furthermore, Cypress does not authorize it s pr o ducts for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cy press
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not
assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51000 Rev. ** Revised January 30, 2009 Page 14 of 14
AutoStore and Quant umTrap are registered trad emarks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be th e trademarks of their re spective
holders.
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