Cypress STK17T88 User Manual
STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Features
■ nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watc hdog Timer, Clock Alarm, Power
Monitor)
■ Capacitor or Battery Backup for RTC
■ 25, 45 ns Read Access and R/W Cycle Time
■ Unlimited Read/Write Endurance
■ Automatic Nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
■ 200K STORE Cycles
■ 20-Year Nonvolatile Data Retention
■ Single 3V +20%, -10% Power Supply
■ Commercial and Industrial Temperatures
■ 48-pin 300-mil SSOP Package (RoHS-Compliant)
Logic Block Diagram
A
5
A
6
A
7
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
ROW DECODER INPUT BUFFERS
STATIC RAM
ARRAY
512 X 512
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A
Quantum Trap
512 X 512
STORE
RECALL
10
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-ti me ala rms or peri odi c
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
V
V
CC
POWER
CONTROL
STORE/
RECALL
CONTROL
RTC
MUX
CAP
V
V
SOFTWARE
DETECT
RTCbat
RTCcap
HSB
A13 – A
X
X
INT
A14 – A
G
0
1
2
0
E
W
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600
Document Number: 001-52040 Rev. *A Revised March 17, 2009
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Pin Configurations
Figure 1. 48-Pin SSOP
V
CAP
1
2
A
14
3
A
4
12
A
7
5
A
6
6
A
5
7
INT
8
A
4
9
NC
10
NC
11
NC
12
V
SS
13
NC
14
V
RTCbat
15
DQ
0
16
A
3
17
A
2
18
A
1
19
A
20
0
DQ
1
21
DQ
2
22
X
23
1
X
2
24
(TOP)
STK17T88
Relative PCB Area Usage
V
48
CC
CNCN
47
46
HSB
45
W
A
44
13
A
6
43
A
9
42
NC
41
A
40
11
39
NC
38
NC
37
NC
36
V
SS
35
NC
V
34
RTCcap
DQ
33
6
G
32
A
31
10
30
E
DQ
29
7
DQ
28
5
DQ
27
4
DQ
3
26
V
CC
25
[1]
Pin Descriptions
Pin Name IO Type Description
A
14-A0
DQ
-DQ
7
0
E Input Chip Enable: The active low E input selects the device.
W
G Input Output Enable: The active low G input enables the data output buffers during read cycles.
X
1
X
2
V
RTCcap
V
RTCbat
V
CC
HSB
INT Output Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the
V
CAP
V
SS
NC No Connect Unlabeled pins have no internal connections.
Note
1. For detailed package size specifications, see Package Diagram on page 21.
Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes
in the clock register map.
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC.
Input Write Enable: The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E.
De-asserting G
high caused the DQ pins to tri-state.
Output Crystal Connection, drives crystal on startup.
Input Crystal Connection for 32.768 kHz crystal.
Power Supply Capacitor supplied backup RTC supply voltage (Left unconnected if V
Power Supply Battery supplied backup RTC supply voltage (Left unconnected if V
RTCcap
RTCbat
is used).
is used).
Power Supply Power: 3.0V, +20%, -10%
I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
Power Supply Autostore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile storage elements.
Power Supply Ground
Document Number: 001-52040 Rev. *A Page 2 of 22
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Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
Voltage on DQ
or HSB......................–0.5V to (VCC + 0.5V)
0-7
...........–0.5V to (VCC + 0.5V)
SS
Temperature under Bias...............................–55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation.............................................................1W
DC Output Current (1 output at a time, 1s duration)....15 mA
RF (SSOP-48) Package Thermal Characteristics
θ
6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]
jc
DC Characteristics
(V
= 2.7V-3.6V)
CC
Symbol Parameter
I
CC
I
CC
I
CC
I
CC
Average VCC Current 65
1
Average VCC Current
2
during STORE
Average V
3
at t
3V, 25°C, Typical
Average V
4
Current during
AVAV
CC
= 200ns
CAP
AutoStore™ Cycle
I
SB
V
Standby Current
CC
(Standby, Stable
CMOS Levels)
I
ILK
Input Leakage
Current
Current
Commercial Industrial
Min Max Min Max
50
3 3 mA All Inputs Don’t Care, VCC = max
10 10 mA W
3 3 mA All Inputs Don’t Care
33mAE
±1 ±1 µAV
STK17T88
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational section s
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Units Notes
70
55
mAmAt
= 25 ns
AVAV
t
= 45 ns
AVAV
Dependent on output loading and cycle rate.
Values obtained without output loads.
Average current for duration of STORE
cycle (t
≥ (V
All Other Inputs Cycling at CMOS Levels
STORE
– 0.2V)
CC
)
Dependent on output loading and cycle rate.
Values obtained without output loads.
Average current for duration of STORE cycle
(t
STORE
)
≥ (VCC -0.2V)
All Others V
Standby current level after nonvolatile cycle
≤ 0.2V or ≥ (V
IN
CC
-0.2V)
complete
= max
CC
V
= VSS to V
IN
CC
I
OLK
V
IH
V
IL
Note:The HSB
Note:The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.
Off-St ate Output
Leakage Current
Input Logic “1”
Voltage
Input Logic “0”
Voltage
pin has I
OUT
±1 ±1 µAV
= max
CC
V
= VSS to VCC, E or G ≥ VIH
IN
2.0 VCC + 0.5 2.0 VCC + 0.5 V All Inputs
VSS –0.5 0.8 VSS –0.5 0.8 V All Inputs
=-10uA for VOH of 2.4V, this parameter is characterized but not tested.
Document Number: 001-52040 Rev. *A Page 3 of 22
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DC Characteristics (continued)
(V
= 2.7V-3.6V)
CC
Symbol Parameter
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
Output Logic “1”
Voltage
Output Logic “0”
Voltage
Operating Temperature
Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10%
Storage Capacitance 17 57 17 57 µFBetween V
Nonvolatile STORE
operations
Data Retention 20 20 Years At 55°C
R
Min Max Min Max
200 200 K
Commercial Industrial
Units Notes
2.4 2.4 V I
0.4 0.4 V I
0 70 –40 85 °C
OUT
OUT
= –2 mA
= 4 mA
CAP
STK17T88
pin and VSS, 5V rated.
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times...................................................≤ 5ns
Input and Output Timing Reference Levels....................1.5V
Output Load..................................See Figure 2 and Figure 3
Capacitance
Symbol Parameter
C
IN
C
OUT
Input Capacitance 7 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 2. AC Output Loading Figure 3. AC Output Loading for Tristate Specs (THZ, tLZ,
[2]
Max Units Conditions
, t
, t
, t
t
WLQZ
WHQZ
GLQX
GHQZ
)
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-52040 Rev. *A Page 4 of 22
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RTC DC Characteristics
STK17T88
Symbol Parameter
Units Notes
Min Max Min Max
IBAK RTC Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat
Commercial Industrial
VRTCbat RTC Battery Pin
1.8 3.3 1.8 3.3 V Typical = 3.0 Volt s during normal operation
Voltage
VRTCcap RTC Capacitor Pin
1.2 2.7 1.2 2.7 V Typical = 2.4 Volt s during normal operation
Voltage
tOSCS RTC Oscillator time to
start
— 10 — 10 sec At Minimum T emperature from Power up or
Enable
—5—5secAt 25°C from Power up or Enable
Figure 4. RTC Component Configuration
1
C
2
C
RF
1
Y
X
1
X
2
Recommended Values
Y
= 32.768 KHz
1
RF
= 10M Ohm
= 0 (install cap footprint,
C
1
but leave unloaded)
C
= 56 pF ± 10% (do not vary from this value)
2
Document Number: 001-52040 Rev. *A Page 5 of 22
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SRAM READ Cycles #1 and #2
STK17T88
NO.
Symbols
#1 #2 Alt. Min Max Min Max
1t
2t
AVAV
3t
AVQV
4t
5t
AXQX
6t
7t
8t
9t
10 t
11 t
DQ (DATA OUT)
[3]
[4]
[4]
ADDRESS
ELQV
t
ELEH
t
AVQV
GLQV
t
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCL
EHICCH
[5]
[6]
[5]
[3]
[3]
Parameter
STK17T88-25 STK17T88-45
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 25 45 ns
Read Cycle Time 25 45 ns
Address Access Time 25 45 ns
Output Enable to Data Valid 12 20 ns
Output Hold after Address Change 3 3 ns
Address Change or Chip Enable to
33ns
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 10 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 25 45 ns
Figure 5. SRAM READ Cycle #1: Address Controlled
2
t
AVAV
3
t
t
AXQX
5
AVQV
DATA VALID
Units
10 15 ns
[3,4,6]
Figure 6. SRAM READ Cycle #2: E and G Controlled
Notes
must be high during SRAM READ cycles.
3. W
4. Device is continuously selected with E
5. Measured ± 200mV from steady state output voltage.
must remain high during READ and WRITE cycles.
6. HSB
and G both low
2
6
3
8
10
1
4
29
[6]
11
7
9
Document Number: 001-52040 Rev. *A Page 6 of 22
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SRAM WRITE Cycles #1 and #2
STK17T88
NO.
12 t
AVAV
13 t
WLWHtWLEH
14 t
ELWH
15 t
DVWHtDVEH
16 t
WHDXtEHDX
17 t
AVWH
18 t
AVWL
19 t
WHAX
20 t
WLQZ
21 t
WHQX
Symbols
STK17T88-25 STK17T88-45
Parameter
#1 #2 Alt. Min Max Min Max
ADDRESS
t
AVAV
t
ELEH
t
AVEH
t
AVEL
t
EHAX
E
t
t
t
t
t
t
t
t
t
t
Write Cycle Time 25 45 ns
WC
Write Pulse Width 20 30 ns
WP
Chip Enable to End of Write 20 30 ns
CW
Data Set-up to End of Write 10 15 ns
DW
Data Hold after End of Write 0 0 ns
DH
Address Set-up to End of Write 20 30 ns
AW
Address Set-up to Start of Write 0 0 ns
AS
Address Hold after End of Write 0 0 ns
WR
Write Enable to Output Disable 10 15 ns
WZ
Output Active after End of Write 3 3 ns
OW
Figure 7. SRAM WRITE Cycle #1: W Controlled
12
t
AVAV
14
t
ELWH
[7, 8]
19
t
WHAX
Units
t
W
DATA IN
DATA IN
DATA OUT
ADDRESS
E
W
DATA IN
Notes
7. If W
or W must be ≥ V during address transitions.
8. E
DATA OUT
is low when E goes low, the outputs remain in the high-impedance state.
18
AVWL
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
20
t
WLQZ
Figure 8. SRAM WRITE Cycle #2: E Controlled
12
t
AVAV
t
AVEL
18
17
t
AVEH
14
t
ELEH
13
t
WLEH
HIGH IMPEDANCE
t
DVEH
15
DATA VALID
16
t
WHDX
[7, 8]
t
EHAX
16
t
EHDX
21
t
WHQX
19
Document Number: 001-52040 Rev. *A Page 7 of 22
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