STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Features
■ nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watc hdog Timer, Clock Alarm, Power
Monitor)
■ Capacitor or Battery Backup for RTC
■ 25, 45 ns Read Access and R/W Cycle Time
■ Unlimited Read/Write Endurance
■ Automatic Nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
■ 200K STORE Cycles
■ 20-Year Nonvolatile Data Retention
■ Single 3V +20%, -10% Power Supply
■ Commercial and Industrial Temperatures
■ 48-pin 300-mil SSOP Package (RoHS-Compliant)
Logic Block Diagram
A
5
A
6
A
7
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
ROW DECODER INPUT BUFFERS
STATIC RAM
ARRAY
512 X 512
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A
Quantum Trap
512 X 512
STORE
RECALL
10
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-ti me ala rms or peri odi c
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
V
V
CC
POWER
CONTROL
STORE/
RECALL
CONTROL
RTC
MUX
CAP
V
V
SOFTWARE
DETECT
RTCbat
RTCcap
HSB
A13 – A
X
X
INT
A14 – A
G
0
1
2
0
E
W
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600
Document Number: 001-52040 Rev. *A Revised March 17, 2009
[+] Feedback
Pin Configurations
Figure 1. 48-Pin SSOP
V
CAP
1
2
A
14
3
A
4
12
A
7
5
A
6
6
A
5
7
INT
8
A
4
9
NC
10
NC
11
NC
12
V
SS
13
NC
14
V
RTCbat
15
DQ
0
16
A
3
17
A
2
18
A
1
19
A
20
0
DQ
1
21
DQ
2
22
X
23
1
X
2
24
(TOP)
STK17T88
Relative PCB Area Usage
V
48
CC
CNCN
47
46
HSB
45
W
A
44
13
A
6
43
A
9
42
NC
41
A
40
11
39
NC
38
NC
37
NC
36
V
SS
35
NC
V
34
RTCcap
DQ
33
6
G
32
A
31
10
30
E
DQ
29
7
DQ
28
5
DQ
27
4
DQ
3
26
V
CC
25
[1]
Pin Descriptions
Pin Name IO Type Description
A
14-A0
DQ
-DQ
7
0
E Input Chip Enable: The active low E input selects the device.
W
G Input Output Enable: The active low G input enables the data output buffers during read cycles.
X
1
X
2
V
RTCcap
V
RTCbat
V
CC
HSB
INT Output Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the
V
CAP
V
SS
NC No Connect Unlabeled pins have no internal connections.
Note
1. For detailed package size specifications, see Package Diagram on page 21.
Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes
in the clock register map.
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC.
Input Write Enable: The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E.
De-asserting G
high caused the DQ pins to tri-state.
Output Crystal Connection, drives crystal on startup.
Input Crystal Connection for 32.768 kHz crystal.
Power Supply Capacitor supplied backup RTC supply voltage (Left unconnected if V
Power Supply Battery supplied backup RTC supply voltage (Left unconnected if V
RTCcap
RTCbat
is used).
is used).
Power Supply Power: 3.0V, +20%, -10%
I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
Power Supply Autostore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile storage elements.
Power Supply Ground
Document Number: 001-52040 Rev. *A Page 2 of 22
[+] Feedback
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
Voltage on DQ
or HSB......................–0.5V to (VCC + 0.5V)
0-7
...........–0.5V to (VCC + 0.5V)
SS
Temperature under Bias...............................–55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation.............................................................1W
DC Output Current (1 output at a time, 1s duration)....15 mA
RF (SSOP-48) Package Thermal Characteristics
θ
6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]
jc
DC Characteristics
(V
= 2.7V-3.6V)
CC
Symbol Parameter
I
CC
I
CC
I
CC
I
CC
Average VCC Current 65
1
Average VCC Current
2
during STORE
Average V
3
at t
3V, 25°C, Typical
Average V
4
Current during
AVAV
CC
= 200ns
CAP
AutoStore™ Cycle
I
SB
V
Standby Current
CC
(Standby, Stable
CMOS Levels)
I
ILK
Input Leakage
Current
Current
Commercial Industrial
Min Max Min Max
50
3 3 mA All Inputs Don’t Care, VCC = max
10 10 mA W
3 3 mA All Inputs Don’t Care
33mAE
±1 ±1 µAV
STK17T88
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational section s
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Units Notes
70
55
mAmAt
= 25 ns
AVAV
t
= 45 ns
AVAV
Dependent on output loading and cycle rate.
Values obtained without output loads.
Average current for duration of STORE
cycle (t
≥ (V
All Other Inputs Cycling at CMOS Levels
STORE
– 0.2V)
CC
)
Dependent on output loading and cycle rate.
Values obtained without output loads.
Average current for duration of STORE cycle
(t
STORE
)
≥ (VCC -0.2V)
All Others V
Standby current level after nonvolatile cycle
≤ 0.2V or ≥ (V
IN
CC
-0.2V)
complete
= max
CC
V
= VSS to V
IN
CC
I
OLK
V
IH
V
IL
Note:The HSB
Note:The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.
Off-St ate Output
Leakage Current
Input Logic “1”
Voltage
Input Logic “0”
Voltage
pin has I
OUT
±1 ±1 µAV
= max
CC
V
= VSS to VCC, E or G ≥ VIH
IN
2.0 VCC + 0.5 2.0 VCC + 0.5 V All Inputs
VSS –0.5 0.8 VSS –0.5 0.8 V All Inputs
=-10uA for VOH of 2.4V, this parameter is characterized but not tested.
Document Number: 001-52040 Rev. *A Page 3 of 22
[+] Feedback
DC Characteristics (continued)
(V
= 2.7V-3.6V)
CC
Symbol Parameter
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
Output Logic “1”
Voltage
Output Logic “0”
Voltage
Operating Temperature
Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10%
Storage Capacitance 17 57 17 57 µFBetween V
Nonvolatile STORE
operations
Data Retention 20 20 Years At 55°C
R
Min Max Min Max
200 200 K
Commercial Industrial
Units Notes
2.4 2.4 V I
0.4 0.4 V I
0 70 –40 85 °C
OUT
OUT
= –2 mA
= 4 mA
CAP
STK17T88
pin and VSS, 5V rated.
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times...................................................≤ 5ns
Input and Output Timing Reference Levels....................1.5V
Output Load..................................See Figure 2 and Figure 3
Capacitance
Symbol Parameter
C
IN
C
OUT
Input Capacitance 7 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 2. AC Output Loading Figure 3. AC Output Loading for Tristate Specs (THZ, tLZ,
[2]
Max Units Conditions
, t
, t
, t
t
WLQZ
WHQZ
GLQX
GHQZ
)
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-52040 Rev. *A Page 4 of 22
[+] Feedback
RTC DC Characteristics
STK17T88
Symbol Parameter
Units Notes
Min Max Min Max
IBAK RTC Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat
Commercial Industrial
VRTCbat RTC Battery Pin
1.8 3.3 1.8 3.3 V Typical = 3.0 Volt s during normal operation
Voltage
VRTCcap RTC Capacitor Pin
1.2 2.7 1.2 2.7 V Typical = 2.4 Volt s during normal operation
Voltage
tOSCS RTC Oscillator time to
start
— 10 — 10 sec At Minimum T emperature from Power up or
Enable
—5—5secAt 25°C from Power up or Enable
Figure 4. RTC Component Configuration
1
C
2
C
RF
1
Y
X
1
X
2
Recommended Values
Y
= 32.768 KHz
1
RF
= 10M Ohm
= 0 (install cap footprint,
C
1
but leave unloaded)
C
= 56 pF ± 10% (do not vary from this value)
2
Document Number: 001-52040 Rev. *A Page 5 of 22
[+] Feedback
SRAM READ Cycles #1 and #2
STK17T88
NO.
Symbols
#1 #2 Alt. Min Max Min Max
1t
2t
AVAV
3t
AVQV
4t
5t
AXQX
6t
7t
8t
9t
10 t
11 t
DQ (DATA OUT)
[3]
[4]
[4]
ADDRESS
ELQV
t
ELEH
t
AVQV
GLQV
t
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCL
EHICCH
[5]
[6]
[5]
[3]
[3]
Parameter
STK17T88-25 STK17T88-45
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 25 45 ns
Read Cycle Time 25 45 ns
Address Access Time 25 45 ns
Output Enable to Data Valid 12 20 ns
Output Hold after Address Change 3 3 ns
Address Change or Chip Enable to
33ns
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 10 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 25 45 ns
Figure 5. SRAM READ Cycle #1: Address Controlled
2
t
AVAV
3
t
t
AXQX
5
AVQV
DATA VALID
Units
10 15 ns
[3,4,6]
Figure 6. SRAM READ Cycle #2: E and G Controlled
Notes
must be high during SRAM READ cycles.
3. W
4. Device is continuously selected with E
5. Measured ± 200mV from steady state output voltage.
must remain high during READ and WRITE cycles.
6. HSB
and G both low
2
6
3
8
10
1
4
29
[6]
11
7
9
Document Number: 001-52040 Rev. *A Page 6 of 22
[+] Feedback
SRAM WRITE Cycles #1 and #2
STK17T88
NO.
12 t
AVAV
13 t
WLWHtWLEH
14 t
ELWH
15 t
DVWHtDVEH
16 t
WHDXtEHDX
17 t
AVWH
18 t
AVWL
19 t
WHAX
20 t
WLQZ
21 t
WHQX
Symbols
STK17T88-25 STK17T88-45
Parameter
#1 #2 Alt. Min Max Min Max
ADDRESS
t
AVAV
t
ELEH
t
AVEH
t
AVEL
t
EHAX
E
t
t
t
t
t
t
t
t
t
t
Write Cycle Time 25 45 ns
WC
Write Pulse Width 20 30 ns
WP
Chip Enable to End of Write 20 30 ns
CW
Data Set-up to End of Write 10 15 ns
DW
Data Hold after End of Write 0 0 ns
DH
Address Set-up to End of Write 20 30 ns
AW
Address Set-up to Start of Write 0 0 ns
AS
Address Hold after End of Write 0 0 ns
WR
Write Enable to Output Disable 10 15 ns
WZ
Output Active after End of Write 3 3 ns
OW
Figure 7. SRAM WRITE Cycle #1: W Controlled
12
t
AVAV
14
t
ELWH
[7, 8]
19
t
WHAX
Units
t
W
DATA IN
DATA IN
DATA OUT
ADDRESS
E
W
DATA IN
Notes
7. If W
or W must be ≥ V during address transitions.
8. E
DATA OUT
is low when E goes low, the outputs remain in the high-impedance state.
18
AVWL
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
20
t
WLQZ
Figure 8. SRAM WRITE Cycle #2: E Controlled
12
t
AVAV
t
AVEL
18
17
t
AVEH
14
t
ELEH
13
t
WLEH
HIGH IMPEDANCE
t
DVEH
15
DATA VALID
16
t
WHDX
[7, 8]
t
EHAX
16
t
EHDX
21
t
WHQX
19
Document Number: 001-52040 Rev. *A Page 7 of 22
[+] Feedback
AutoStore/Power Up RECALL
STK17T88
NO.
22 t
23 t
24 V
25 V
Symbols
STK17T88
Parameter
Standard Alternate Min Max
HRECALL
STORE
SWITCH
CCRISE
t
HLHZ
Power up RECALL Duration 40 ms 9
STORE Cycle Duration 12.5 ms 10, 11
Low Voltage Trigger Level 2.65 V
V
Rise Time 150 µS
CC
Figure 9. AutoStore Power Up RECALL
25
Units Notes
23 23
22
22
NOTE: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below V
Notes
9. t
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
11. Industrial Grade Devices require 15 ms Max.
starts from the time VCC rises above V
HRECALL
SWITCH
SWITCH
Document Number: 001-52040 Rev. *A Page 8 of 22
[+] Feedback
Software-Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
STK17T88
[12, 13]
NO.
Symbols
Parameter
STK17T88-35 STK17T88-45
E Cont Alternate Min Max Min Max
26 t
27 t
28 t
29 t
30 t
AVAV
AVEL
ELEH
EHAX
RECALL
t
t
t
RC
AS
CW
STORE / RECALL Initiation Cycle Time 25 45 ns 13
Address Set-up Time 0 0 ns
Clock Pulse Width 20 30 ns
Address Hold Time 1 1 ns
RECALL Duration 100 100 ms
Figure 10. Software Store/Recall Cycle: E CONTROLLED
26
27
28
29
26
23 30
Units Notes
[13]
Notes
12.The software sequence is clocked on the falling edge of E
13.The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table . W must be high during all six consecutive cycles.
controlled READs
Document Number: 001-52040 Rev. *A Page 9 of 22
[+] Feedback
Hardware STORE Cycle
STK17T88
NO.
Symbols
Standard Alternate Min Max
31 t
32 t
DELAY
HLHX
t
HLQZ
Hardware STORE to SRAM Disabled 1 70 µs14
Hardware STORE Pulse Width 15 ns
Soft Sequence Commands
Parameter
Units Notes
Figure 11. Hardware STORE Cycle
32
23
31
STK17T88
NO.
Symbols Parameter STK17T88 Units Notes
Standard Min Max
33 t
SS
Soft Sequence Processing Time 70 µs 15, 16
Figure 12. Soft Sequence Command
33 33
Notes
14.On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
15.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16.Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command
Document Number: 001-52040 Rev. *A Page 10 of 22
[+] Feedback
MODE Selection
STK17T88
E W G A14-A
0
Mode I/O Power Notes
H X X X Not Selected Output High Z S tandby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
LH L0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0 Nonvolatile Store Output High Z I
LH L0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active 17,18, 19
CC2
Active
17,18, 19
Notes
17.The six consecutive addresses must be in the order listed. W
18.While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes.
19.I/O state depends on the state of G
. The I/O table shown assumes G low.
must be high during all six consecutive cycles to enable a nonvolatile cycle.
Document Number: 001-52040 Rev. *A Page 11 of 22
[+] Feedback
STK17T88
nvSRAM Operation
The STK17T88 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM
memory cell and a nonvolatile QuantumTrap™ cell. The SRAM
memory cell operates like a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell t o SRAM (the RECALL
operation). This unique architecture allows all cells to be stored
and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The
STK17T88 supports unlimited read and writes like a typical
SRAM. In addition, it provides unlimited RECALL operations
from the nonvolatile cells and up to 200K STORE operations.
SRAM READ
The STK17T88 performs a READ cycle whenever E and G are
low while W
A
0-14
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
initiated by E
whichever is later (READ cycle #2). The data outputs repeatedly
respond to address changes within the t
without the need for transitions on any cont rol input pins, and
remain valid until another address change or until E
brought high, or W
Figure 13. AutoStore Mode
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid t
of a W
controlled WRITE.
It is recommended that G
cycle to avoid data bus contention on common I/O lines. If G
left low, internal circuitry turns off the output buffers t
goes low.
W
AutoStore Operation
The STK17T88 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
and HSB are high. The address specified on pins
determine which of the 32,768 data bytes are accessed.
(READ cycle #1). If the READ is
and G, the outputs are valid at t
CAP
V
AVQV
and HSB is brought low.
V
CAP
V
CC
W
ELQV
AVQV
V
10k Ohm
or at t
GLQV
access time
or G is
CC
0.1µF
or W goes
before the end
controlled WRITE or t
DVEH
DVWH
before the end of an E
be kept high during the entire WRITE
is
after
WLQZ
(activated by HSB
), Software Store (activated by an address
sequence), and AutoStore (on power down).
AutoStore operation, a unique feature of Cypress QuanumTrap
technology that is a standard feature on the STK17T88.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
pin drops below V
CC
pin from VCC. A STORE
CAP
pin. This stored
CAP
STORE operation.
SWITCH
CAP
Figure 5 shows the proper connection of the storage capacitor
(V
) for automatic store operation. Refer to the DC Character-
CAP
istics table for the size of the capacitor . The volt age on the V
pin is driven to 5V by a charge pump internal to the chip. A pull
up should be placed on W
to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
,
place. The HSB
signal can be monitored by the system to detect
an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The STK17T88 provides the HSB pin for controlling and
acknowledging the
used to request a hardware
STORE operations. The HSB pin can be
STORE cycle. When the HSB pin is
driven low, the STK17T88 conditionally initiates a
operation after t
WRITE to the SRAM took place since the last STORE or
. An actual STORE cycle only begins if a
DELAY
RECALL cycle. The HSB pin has a very resistive pull up and is
internally driven low to indicate a busy condition while the
STORE (initiated by any means) is in progress. This pin should
be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in progress when
is driven low by any means are given time to complete
HSB
before the STORE operation is initiated. After HSB
goes low, the
STK17T88 continues to allow SRAM operations for t
During t
If a WRITE is in progress when HSB
time, t
requested after HSB
, multiple SRAM READ operations may take place.
DELAY
, to complete. However, any SRAM WRITE cycles
DELAY
goes low will be inhibited until HSB returns
is pulled low, it is allowed a
high.
During any
the STK17T88 will continue to drive the HSB
it only when the
STORE operation, regardless of how it was initiated,
pin low, releasing
STORE is complete. Upon completion of the
STORE operation, the STK17T88 will remain disabled until the
HSB
pin returns high.
If HSB
is not used, it should be left unconnected.
Hardware Recall (POWER UP)
During power up or after any low-power condition
(V
CC<VSWITCH
When V
RECALL cycle is automatically initiated and takes t
complete.
), an internal RECALL request will be latched.
once again exceeds the sense voltage of V
CC
CC
, the part
capacitor.
CAP
STORE
STORE
DELAY
SWITCH
HRECALL
to
.
, a
to
Document Number: 001-52040 Rev. *A Page 12 of 22
[+] Feedback
STK17T88
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK17T88
software
STORE cycle is initiated by executing sequential E
controlled READ cycles from six specific address locations in
exact order. During the
STORE cycle, previous data is erased
and then the new data is programmed into the nonvolatile
elements. Once a
STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
To initiate the software
STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
Once the sixth address in the sequence has been entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles be used in
the sequence. After the t
SRAM is again activated for READ and WRITE operation.
cycle time has been fulfilled, the
STORE
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software
RECALL
cycle is initiated with a sequence of READ operations in a manner similar to the software
STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally,
RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the t
cycle time, the
RECALL
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
Data Protection
The STK17T88 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition is detected when
V
CC<VSWITCH
.
If the STK17T88 is in a WRITE mode (both E
power up, after a
RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E
and W low) at
or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The STK17T88 is a high-speed memory and so must have a
high-frequency bypass capacitor of 0.1 µF connected between
both V
V
SS
all high-speed CMOS ICs, careful routing of power, ground, and
pins and VSS ground plane with no plane break to chip
CC
. Use leads and traces that are as short as possible. As with
signals reduce circuit noise.
Preventing AutoStore
Because of the use of nvSRAM to store critical RTC data, the
AutoStore function can not be disabled on the STK17T88.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, etc. should always program a unique NV
pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or
more random bytes) as part of the final system manufacturing
test to ensure these system routines work consistently.
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state (autostore enabled, etc.). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, etc.).
■ The OSCEN bit in the Calibration register at 0x7FF8 should be
set to 1 to preserve battery life when the system is in storage
(see Stopping and Starting the RTC Oscillator on page 14.
■ The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
nvSRAM internal algorithm calculates V
on this max Vcap value. Customers that want to use a larger
V
CAP
time should discuss their V
understand any impact on the V
a t
value specified in this datasheet includes a minimum
CAP
value because the
CAP
charge time based
CAP
value to make sure there is extra store charge and store
size selection with Cypress to
RECALL
cap
period.
voltage level at the end of
CAP
Document Number: 001-52040 Rev. *A Page 13 of 22
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STK17T88
Real Time Clock
The clock registers maintain time up to 9,999 years in
one-second increments. The user can set the time to any
calendar time and the clock automatically keeps track of days of
the week and month, leap years, and century transitions. There
are eight registers dedicated to the clock functions which are
used to set time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in BCD format.
Bits defined as “0” are currently not used and are reserved for
future use by Cypress.
Reading the Clock
The user should halt internal updates to the real time clock
registers before reading clock data to prevent reading of data in
transition. Stopping the internal register updates does not affect
clock accuracy.
Write a “1” to the read bit “R” (in the Flags register at 0x7FF0) to
capture the current time in holding registers. Clock updates do
not restart until a “0” is written to the read bit. The RTC registers
can now be read while the internal clock continues to run.
Within 20ms after a “0” is written to the read bit, all real time clock
registers are simultaneously updated.
Setting the Clock
Set the write bit “W” (in the Flags register at 0x7FF0) to a “1”
enable the time to be set. The correct day, date and time can then
be written into the real time clock registers in 24-hour BCD
format. The time written is referred to as the “Base Time.” This
value is stored in nonvolatile registers and used in calculation of
the current time. Reset the write bit to “0” to transfer the time to
the actual clock counters, The clock starts counting at the new
base time.
Backup Power
The RTC is intended to keep time even when system power is
lost. When primary power, V
time clock switches to the backup power supply connected to
either the V
RTCcap
or V
RTCbat
, drops below V
CC
pin.
The clock oscillator uses a maximum of 300 nanoamps at 2 volts
to maximize the backup time available from the backup source.
You can power the real time clock with either a capacitor or a
battery. Factors to be considered when choosing a backup
power source include the expected duration of power outages
and the cost and reliability trade-off of using a batte ry versus a
capacitor.
If you select a capacitor power source, connect the capacitor to
the V
Capacitor backup time values based on maximum current specs
pin and leave the V
RTCcap
pin unconnected.
RTCbat
are shown below. Nominal times are approximately 3 times
longer.
Capacitor Value Backup Time
0.1 F 72 hours
0.47 F 14 days
1.0 F 30 days
SWITCH
, the real
A capacitor has the obvious advantage of being more reliable
and not containing hazardous materials. The capacitor is
recharged every time the power is turned on so that the real time
clock continues to have the same backup time over years of
operation
If you select a battery power source, connect the battery to the
V
is recommended for this application. The battery capacity should
pin and leave the V
RTCbat
pin unconnected. A 3V lithium
RTCcap
be chosen for the total anticipated cumulative down-time
required over the life of the system.
The real time clock is designed with a diode internally connected
to the V
charged by the circuit.
pin. This prevents the battery from ever being
RTCbat
Stopping and Starting the RTC Oscillator
The OSCEN bit in Calibration register at 0x7FF8 enables RTC
oscillator operation. This bit is nonvolatile and shipped to
customers in the “enabled” state (set to 0). OSCEN should be set
to a 1 to preserve battery life while the system is in storage. This
turns off the oscillator circuit extending the battery life. If the
OSCEN bit goes from disabled to enabled, it typically takes 5
seconds (10 seconds max) for the oscillator to start.
The STK17T88 has the ability to detect oscillator failure due to
loss of backup power. The failure is recorded by the OSCF
(Oscillator Failed bit) of the Flags register (at address 0x7FF0).
When the device is powered on (V
OSCEN bit is checked for “enabled” status. If the OSCEN bit is
goes above V
CC
SWITCH
) the
enabled and the oscillator is not active within 5 ms, the OSCF bit
is set. The user should check for this condit ion and then writ e a
0 to clear the flag. When the OSCF flag bit, the real time clock
registers are reset to the “Base Time” (see the section Setting
the Clock on page 14, the value last written to the real time clock
registers.
The value of OSCF should be reset to 0 when the real time clock
registers are written for the first time. This initializes th e state of
this bit since it may have become set when the system was first
powered on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FF0) to a “1” to enable writes to the Flags register. Write a “0”
to the OSCF bit and then reset the write bit to “0” to disable
writes.
Calibrating The Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 KHz. Clock accuracy depends on the quality
of the crystal specified (usually 35 ppm at 25 C). This error could
equate to 1.53 minutes gain or loss per month. The STK17T88
employs a calibration circuit that can improve the accuracy to
+1/-2 ppm at 25 C. The calibration circuit adds or subtracts
counts from the oscillator divider circuit.
The number of time pulses added or subt racted depends upon
the value loaded into the five calibration bits found in Calibration
register (at 0x7FF8). Adding counts speeds the clock up;
subtracting counts slows the clock down. The Calibration bits
occupy the five lower order bits of the register. These bits can be
set to represent any value between 0 and 31 in binary form. Bit
D5 is a Sign bit, where a “1” indicates positive calib ration a nd a
“0” indicates negative calibration. Calibration occurs during a 64
minute period. The first 62 minutes in the cycle may, once per
Document Number: 001-52040 Rev. *A Page 14 of 22
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STK17T88
minute, have one second either shortened by 128 or lengthened
by 256 oscillator cycles.
If a binary “1” is loaded into the register, only the first 2 minutes
of the 64 minute cycle is modified; if a binary 6 is loaded, the first
12 are affected, and so on. Therefore each calibration step has
the effect of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is +4.068 or
-2.034 ppm of adjustment per calibration step in the Calibration
register.
The calibration register value is determined during system test
by setting the CAL bit in the Flags register (at 0x7FF0) to 1. This
causes the INT pin to toggle at a nominal 512 Hz. This frequency
can be measured with a frequency counter. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
would indicate a +20 ppm error, requiring a -10 (001010) to be
loaded into the Calibration register. Note that setting or changing
the calibration register does not affect the frequency test ou tp ut
frequency.
To set or clear CAL, set the write bit “W” (in the Flags register at
0x7FF0) to a “1” to enable writes to the Flags register. Write a
value to CAL and then reset the write bit to “0” to disable writes.
The default Calibration register value from the factory is 00h. The
user calibration value loaded is retained during a power loss.
Alarm
The alarm function compares a user-programmed alarm
time/date (stored in registers 0x7FF1-5) with the real time clock
time-of-day/date values. When a match occu rs, the alarm flag
(AF) is set and an interrupt is generated if the alarm interrupt is
enabled. The alarm flag is automatica lly reset when the Flags
register is read.
Each of the alarm registers has a match bit as its MSB. Setting
the match bit to a 1 disables this alarm register from the alarm
comparison. When the match bit is 0, the alarm register is
compared with the equivalent real time clock register. Using the
match bits, an alarm can occur as specifically as one particular
second on one day of the month or as freque ntly as once per
minute.
Note The product requires the match bit for seconds (0x7FF2,
bit D7) be set to 0 for proper operation of the Alarm Flag and
Interrupt.
The alarm value should be initialized on power up by so ftware
since the alarm registers are not nonvolatile.
To set or clear the Alarm registers, set the write bit “W” (in the
Flags register at 0x7FF0) to a “1” to enabl e writes to the Ala rm
registers. Write an alarmvalue to the alarm registers and then
reset the write bit to “0” to disable writes.
Watchdog Timer
The watchdog timer is designed to interrupt or reset the
processor should its program get hung in a loop and not respond
in a timely manner. The software must reload the watchdog timer
before it counts down to zero to prevent this interrupt or reset.
The watchdog timer is a free-running-down counter that uses the
32Hz clock (31.25 ms) derived from the crystal oscillator. The
watchdog timer function does not operate unless the oscillator is
running.
The watchdog counter is loaded with a starting value from the
load register and then counts down to zero, setting the watchdog
flag (WDF) and generating an interrupt if the watchdog interrupt
is enabled. The watchdog flag bit is reset when the Flags register
is read. The operating software would normally reload the
counter by setting the watchdog strobe bit (WDS) to 1 within the
timing interval programmed into the load register.
T o use the watchdog timer to reset the processor on timeout, the
INT is tied to processor master reset and Interrupt register is
programmed to 24h to enable interrupts to pulse the reset pin on
timeout.
T o load the watchdog timer, set a new value into the load register
by writing a “0” to the wa tchdog wr ite bit (WDW) o f the watchd og
register (at 0x7FF7). Then load a new value into the load register.
Once the new value is loaded, the watchdog write bit is then set
to 1 to disable watchdog writes. The watchdog strobe bit (WDS)
is set to 1 to load this value into the watchdog timer. Note: Setting
the load register to zero disables the watchdog timer function.
The system software should initialize the watchdog load register
on power up to the desired value since the register is not nonvolatile.
Power Monitor
The STK17T88 provides a power monitor function. The power
monitor is based on an internal band-gap reference circui t that
compares the V
When the power supply drops below V
circuit is switched to the backup supply (battery or capacitor).
When operating from the backup source, no data may be read
or written and the clock functions are no t available to the user.
The clock continues to operate in the background. Updated clock
data is available to the user t
restored to the device.
When the power is lost, the PF flag in the Flags register is set to
indicate the power failure and an interru pt is generated if the
power fail interrupt is enabled (interrupt register=20h). The INT
line would normally be tied to the processor master reset input
to perform power-off reset.
voltage to V
CC
SWITCH
HRECALL
.
, the real time clock
SWITCH
delay after VCC has been
Interrupts
The STK17T88 has a Flags register, Interrupt register, and
interrupt logic that can interrupt the micro controll er or general a
power up master reset signal. There are three potential interrupt
sources: the watchdog timer, the power monitor, and the clock
alarm. Each can be individually enabled to d rive the INT pi n by
setting the appropriate bit in the Interrupt register. In addition,
each has an associated flag bit in the Flags register that the host
processor can read to determine the interrupt source. Two bits in
the interrupt register determine the operation of the INT pin
driver.
Document Number: 001-52040 Rev. *A Page 15 of 22
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STK17T88
Figure 15 is a functional diagram of the interrupt logic.
Figure 15. Interrupt Block Diagram
Watchdog
Timer
Power
Monitor
VINT
Clock
Alarm
WDF
WIE
PF
PFE
AF
AIE
P/L
Pin
Driver
H/L
V
CC
INT
V
SS
Interrupt Register
Watchdog Interrupt Enable (WIE). When set to 1, the watchdog
timer drives the INT pin when a watchdog time-out occurs. When
WIE is set to 0, the watchdog time-out only sets the WDF flag bit.
Alarm Interrupt Enable (AIE). When set to 1, the INT pin is driven
when an alarm match occurs. When set to 0, the alarm match
only sets the AF flag bit.
Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is
driven by a power fail signal from the power monitor. When set
to 0, only the PF flag is set.
High/Low (H/L). When set to a 1, the I NT pin is active high and
the driver mode is push-pull. The INT pin can drive high only
when V
and the drive mode is open-drain. The active low (open drain)
CC>VSWITCH
. When set to a 0, the INT pin is active low
output is maintained even when power is lost.
Pulse/Level (P/L). When set to a 1, the INT pin is driven for
approximately 200 ms when the interrupt occurs. The p ulse is
reset when the Flags register is read. When P/L is set to a 0, the
INT pin is driven high or low (determined by H/L) until the Flags
register is read.
The Interrupt register is loaded with the default value 00h at the
factory. The user should configure the Interrupt register to the
value desired for their desired mode of operation. Once
configured, the value is retained during power failures.
Flags Register
The Flags register has three flag bits: WDF, AF, and PF. These
flags are set by the watchdog time-out, alarm match, or power
fail monitor respectively. The processor can either poll this
register or enable the interrupts to be informed when a flag is set.
The flags are automatically reset once the register is read.
The Flags register is automatically loaded with the value 00h on
power up (with the exception of the OSCF bit).
Document Number: 001-52040 Rev. *A Page 16 of 22
[+] Feedback
RTC Register Map
STK17T88
Register
0x7FFF 10s Years Years Years: 00-99
0x7FFE 0 0 0 10s
0x7FFD 0 0 10s Day of Month Day of Month Day of Month: 01-31
0x7FFC 0 0 0 0 0 Day of Week Day of week: 01-07
0x7FFB 0 0 10s Hours Hours Hours: 00-23
0x7FFA 0 10s Minutes Minutes Minutes: 00-59
0x7FF9 0 10s Seconds Seconds Seconds: 00-59
0x7FF8 OSCEN
0x7FF7 WDS WDW WDT Watchdog*
0x7FF6 WIE[0] AIE[0] PFE[0] 0 H/L [1] P/L [0] 0 0 Interrupts*
0x7FF5 M 0 10s Alarm Date Alarm Day Alarm, Day of Month: 01-31
0x7FF4 M 0 10s Alarm Hours Alarm Hours Alarm, hours: 00-23
0x7FF3 M 10 Alarm Minutes Alarm Minutes Alarm, minutes: 00-59
0x7FF2 M 10 Alarm Seconds Alarm Seconds Alarm, seconds: 00-59
0x7FF1 10s Centuries Centuries Centuries: 00-99
0x7FF0 WDF AF PF OSCF 0 CAL[0] W[0] R[0] Flags*
*A binary value, not a BCD value.
0 - Not implemented, reserved for future use.
Default Settings of nonvolatile Calibration and Interrupt registers from factory
Calibration Register=00h
Interrupt Register=00h
The User should configure to the desired value at startup or during operation and the value is then retained during a power failure.
[ ] designates values shipped from the factory. See Stopping and Starting the RTC Oscillator on page 14.
D7 D6 D5 D4 D3 D2 D1 D0
0Cal
[0]
BCD Format Data
Months
Sign
Function / Range
Months Months: 01-12
Calibration [00000] Calibration values*
Document Number: 001-52040 Rev. *A Page 17 of 22
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STK17T88
Register Map Detail
0x7FFF
0x7FFE
0x7FFD
0x7FFC
0x7FFB
0x7FFA
0x7FF9
0x7FF8
OSCEN Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator is enabled.
Calibration Sign Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Calibration These five bits control the calibration of the clock.
0x7FF7
WDS Watchdog S trobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automat-
D7 D6 D5 D4 D3 D2 D1 D0
10s Years Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble
contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 10s
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 10s Day of month Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from
0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31.
Leap years are automatically adjusted for.
D7 D6 D5 D4 D3 D2 D1 D0
00000 Day of week
Lower nibble contains a value that correlates to day of the week. Day of the wee k is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as t he day is not
integrated with the date.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 10s Hours Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and ope rates
from 0 to 9; upper nibble (two b its) contains the upper digit and operates from 0 to 2. The range for the
register is 0-23.
D7 D6 D5 D4 D3 D2 D1 D0
0 10s Minutes Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59.
D7 D6 D5 D4 D3 D2 D1 D0
0 10s Seconds Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
D7 D6 D5 D4 D3 D2 D1 D0
OSCEN 0 Calibratio
n Sign
Disabling the oscillator saves battery/capacitor power during storage.
D7 D6 D5 D4 D3 D2 D1 D0
WDS WDW WDT
ically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.
Real Time Clock – Years
Real Time Clock – Months
Months
Month
Real Time Clock – Date
Real Time Clock – Day
Real Time Clock – Hours
Real Time Clock – Minutes
Real Time Clock – Seconds
Calibration
Calibration
Watchdog Timer
Document Number: 001-52040 Rev. *A Page 18 of 22
[+] Feedback
Register Map Detail (continued)
WDW W atchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0).
WDT Watchdog time-out selection. The watchdog ti me r int erval i s select ed b y the 6-bit valu e in t hi s regist er. It
0x7FF6
WIE Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the
AIE Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and sets the AF flag. When set
PFIE Power-Fail Enable. When set to 1, a power failure drives the INT pin and sets the PF flag. When set to 0,
0 Reserved for Future Use
H/L High/Low. When set to a 1, the INT pin is driven active high. When set to 0, t he INT pin is open drain,
P/L Pulse/Level. Wh en set to a 1, the INT p in is driven active (determin ed by H/L) by an interrupt source for
0x7FF5
M Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes
0x7FF4
M Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1
0x7FF3
M Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setti ng this bit to 1
0x7FF2
M Match. Setting this bit to 0 causes the seconds’ value to be used in th e alarm match. Se ttin g this bit to 1
0x7FF1 Real Time Clock – Centuries
This allows the user to strobe the watchdog without disturbing the time-out value. Setting this bit to 0 allows
bits 5-0 to be written.
represents a multiplier of the 32 Hz count (31.25 ms). The range or time-out values is 31.25 ms (a setting
of 1) to 2 seconds (setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits
can be written only if the WDW bit was cleared to 0 on a previous cycle.
Interrupt
D7 D6 D5 D4 D3 D2 D1 D0
WIE AIE PFIE ABE H/L P/L 0 0
INT pin and sets the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag.
to 0, the alarm match only sets the AF flag.
a power failure only sets the PF flag.
active low.
approximately 200 ms. When set to a 0, the INT pin is driven to an act ive level (as set by H/L) until t he
Flags register is read.
Alarm – Day
D7 D6 D5 D4 D3 D2 D1 D0
M 0 10s Alarm Date Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
the match circuit to ignore the date value.
Alarm – Hours
D7 D6 D5 D4 D3 D2 D1 D0
M 0 10s Alarm Hours Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
causes the match circuit to ignore the hours value.
Alarm – Minutes
D7 D6 D5 D4 D3 D2 D1 D0
M 10s Alarm Minutes Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
causes the match circuit to ignore the minutes value.
Alarm – Seconds
D7 D6 D5 D4 D3 D2 D1 D0
M 10s Alarm Seconds Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
causes the match circuit to ignore the seconds value.
10s Centuries Centuries
Contains the BCD value of Centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper centuries digit and operates from 0 to 9. The rang e for the register is 0-99
centuries.
STK17T88
Document Number: 001-52040 Rev. *A Page 19 of 22
[+] Feedback
Register Map Detail (continued)
0x7FF0
WDF Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without
AF Alarm Flag. This read-only bit is set to 1 when the time and date match the value s stored in the alarm
PF Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold V
OSCF Oscillator Fail Flag. Set to 1 on power up only if the oscillat or is enable d and not runn ing in the f irst 5ms
CAL Calibration Mode. When set t o 1, a 512Hz squa re wave is output on t he INT pin . When set to 0, the INT
W Write Time. Setting the W bit to 1 freezes updates of the RTC registers. The user ca n then write to the
R Rea d Time. Setting the R bit to 1 captures the current t ime in ho lding regist ers so th at clock updates are
D7 D6 D5 D4 D3 D2 D1 D0
WDF AF PF OSCF 0 CAL W R
being reset by the user. It is cleared to 0 when the Flags register is read or on power up
registers with the match bits = 0. It is cleared when the Flags register is read or on power up
is cleared to 0 when the Flags register is read or on power up.
of operation. This indicates that the RTC backup power failed and the clock value is no longer valid. The
user must reset this bit to 0 to clear this condition.
pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit
to 0 disables writes to the registers and causes the contents of the real time clock registers to be transferred
to the timekeeping counters if the time has changed (a new base time is loaded). The bit defaults to 0 on
power up.
not during the reading process. Set the R bit to 0 to enable the holding register to resume clock updates.
The bit defaults to 0 on power up.
Flags
STK17T88
. It
SWITCH
Commercial and Industrial Ordering Information
STK17T88 - R F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
C - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Lead Finish
F = 100% Sn (Matte Tin) RoHS Compliant
Package:
R = Plastic 48-pin 330 mil SSOP
Speed:
25 - 25 ns
45 - 45 ns
Ordering Codes
Ordering Code Description Access Times (ns) Temperature
STK17T88-RF25 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 Commercial
STK17T88-RF45 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 Commercial
STK17T88-RF25TR 3.3 V 32 Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 Commercial
STK17T88-RF45TR 3.3 V 32 Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 Commercial
STK17T88-RF25I 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 Industrial
STK17T88-RF45I 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 Industrial
STK17T88-RF25ITR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 Industrial
STK17T88-RF45ITR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 Industrial
Document Number: 001-52040 Rev. *A Page 20 of 22
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Package Diagram
STK17T88
Figure 16. 48-Pin SSOP (51-85061)
51-85061-*C
Document Number: 001-52040 Rev. *A Page 21 of 22
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STK17T88
Document History Page
Document Title: STK17T88 32K x 8 AutoStore™ nvSRAM with Real-Time Clock
Document Number: 001- 52040
Rev ECN No.
** 2668660 GVCH/PYRS 03/04/2009 New data sheet
*A 2675319 GVCH 03/17/2009 Corrected typo on page 1 in ‘Description’
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunctio n with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not
assume any liability arising out of the app licati on or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot auth orize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52040 Rev. *A Revised March 17, 2009 Page 22 of 22
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