Cypress STK14D88 User Manual

STK14D88

32Kx8 AutoStore™ nvSRAM

Features

A0 A1 A2 A3 A4 A

10

COLUMN I/O

COLUMN DEC

STATIC RAM

ARRAY

512 x 512

ROW DECODER

INPUT BUFFERS

Quantum Trap

512 x 512

STORE/
RECALL

CONTROL

STORE

RECALL

POWER

CONTROL

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

SOFTWARE

DETECT

G

E
W

HSB

V

CCXVCAP

A0 - A

13

Logic Block Diagram

Description

■ 25, 35, 45 ns Read Access and R/W Cycle Time

■ Unlimited Read/Write Endurance

■ Automatic Nonvolatile STORE on Power Loss

■ Nonvolatile STORE Under Hardware or Software Control

■ Automatic RECALL to SRAM on Power Up

■ Unlimited RECALL Cycles

■ 200K STORE Cycles

■ 20-Year Nonvolatile Data Retention

■ Single 3.0V +20%, -10% Power Supply

■ Commercial, Industrial Temperatures

■ Small Footprint SOIC and SSOP Packages (RoHS-Compliant)

The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap™ storage element included with each
memory cell.

The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.

Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-52037 Rev. ** Revised March 02, 2009

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STK14D88

Pin Configurations

48-Pin SSOP

TOP

V

SS

A

14

A

12

A

7

A

6

DQ

0

DQ

1

V

CC

DQ

2

A

3

A

2

A

1

V

CAP

A

13

A

8

A

9

A

11

A

10

DQ

7

DQ

6

V

SS

A

0

NC

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

NC

E

NC
NC

23
24

A

5

NC

NC
NC
NC

NC

NC

A

4

48
47
46
45

V

CC

HSB

NC
NC

W

NC

NC

DQ

5

DQ

3

DQ

4

G

NC NC

32-SOIC

TOP

V

SS

A

14

A

12

A

7

A

6

DQ

0

V

CAP

A

13

A

8

A

9

A

11

28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A

5

A

4

32
31
30
29

V

CC

HSB
W

A

3

A

2

A

1

A

0

DQ

1

DQ

2

A

10

DQ

7

DQ

5

DQ

3

DQ

4

DQ

6

NCNC

E

G

SSOP

Relative PCB Area Usage

[1]

Note

1. See “Package Diagrams” on page 15 for detailed package size specifications.

Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC

Pin Descriptions

Pin Name I/O Description

A

14-A0

DQ

V

HSB

V

V

Document Number: 001-52037 Rev. ** Page 2 of 17

-DQ

7

0

E

W

G Input Output Enable: The active low G input enables the data output buffers during read cycles.

CC

CAP

SS

NC No Connect Unlabeled pins have no internal connections.

Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array

I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Input Chip Enable: The active low E input selects the device
Input Write Enable: The active low W enables data on the DQ pins to be written to the address location

Power Supply Power: 3.0V, +20%, -10%

I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low

Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to

Power Supply Ground

latched by the falling edge of E

De-asserting G

high caused the DQ pins to tri-state.

external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).

nonvolatile storage elements.

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STK14D88

Absolute Maximum Ratings

Note:

2. The HSB

pin has I

OUT

=-10uA for VOH of 2.4V , this parameter is characterized but not tested

Voltage on Input Relative to Ground.................–0.5V to 4.1V

Voltage on Input Relative to V
Voltage on DQ

or HSB................. ... ..–0.5V to (VCC + 0.5V)

0-7

...........–0.6V to (VCC + 0.5V)

SS

Temperature under Bias............................... –55°C to 125°C

Storage Temperature.................................... –65°C to 140°C

Power Dissipation.............................................................1W

DC Output Current (1 output at a time, 1s duration).....15mA

NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS

θ

5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].

jc

RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS

θ

6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].

jc

DC Characteristics

(VCC = 2.7V-3.6V)

Symbol Parameter

I

CC

I

CC

I

CC

Average VCC Current 65

1

Average VCC Current during

2

STORE

3

Average V
200ns

Current at t

CC

3V, 25°C, Typi ca l

I

CC

I

SB

Average V

4

AutoStore Cycle

V

CC

(Standby, Stable CMOS Input

CAP

Standby Current

Current during

Levels)

I

ILK

I

OLK

V
V
V

IH
IL
OH

Input Leakage Current ±1 ±1 μAV

Off-State Output Leakage Current ±1 ±1 μAV

Input Logic “1” Voltage 2.0 VCC + .5 2.0 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I

[2]

=

AVAV

Commercial Industrial

Min Max Min Max

Note: Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational section s
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

Unit Notes

t

mA
mA
mA

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

Dependent on output loading and

55
50

70
60
55

cycle rate. Values obtained without
output loads.

3 3 mA All Inputs Don’t Care, VCC = max

Average current for duration of
STORE cycle (t

10 10 mA W

All Others Cycling, CMOS Levels

≥ (V

CC

– 0.2V)

STORE

)

Dependent on output loading and
cycle rate. Values obtained without
output loads.

3 3 mA All Inputs Don’t Care

Average current for duration of
STORE cycle (t

STORE

)

33mAE ≥ (VCC – 0.2V)

All Others V

0.2V)

≤ 0.2V or ≥ (VCC –

IN

Standby current level after nonvol­atile cycle complete

= max

CC

V

= VSS to V

IN

= max

CC

V

= VSS to VCC, E or G ≥ VIH

IN

= –2mA

OUT

CC

Document Number: 001-52037 Rev. ** Page 3 of 17

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STK14D88

DC Characteristics (continued)

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times ............................................ <5 ns

Input and Output Timing Reference Levels.................... 1.5V

Output Load..................................See Figure 2 and Figure 3

577

Ω

30 pF

789

Ω

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

577

Ω

5 pF

789

Ω

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

Note

3. These

parameters are guaranteed but not tested.

(VCC = 2.7V-3.6V)

Symbol Parameter

V

OL

T

A

V

CC

V

CAP

DATA
NV

Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 -40 85 °C
Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V +20%, -10%
Storage Capacitance 17 120 17 120 μFBetween V

Data Retention 20 20 K

R

Nonvolatile STORE Operations 200 200 Years @ 55°C

C

AC Test Conditions

[2]

Commercial Industrial

Min Max Min Max

Unit Notes

= 4mA

OUT

pin and VSS, 5V

Rated

CAP

Figure 2. AC Output Loading

Figure 3. AC Output Loading for Tri-state Specs (t

Capacitance

[3]

Description Test Conditions Max Unit Conditions

Input Capacitance TA = 25°C, f = 1 MHz, 7 pF ΔV = 0 to 3V
Output Capacitance 7 pF ΔV = 0 to 3V

Parameter

C

IN

C

OUT

Document Number: 001-52037 Rev. ** Page 4 of 17

, tLZ, t

HZ

WLQZ

, t

WHQZ

, t

, t

GLQX

GHQZ

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STK14D88

SRAM READ Cycles #1 and #2

Notes

4. W

must be high during SRAM READ cycles.

5. Device is continuously selected with E

and G both low.

6. Measured ± 200mV from steady state output voltage.

7. HSB

must remain high during READ and WRITE cycles.

DATA VALID

5

t

AXQX

3

t

AVQV

DQ (DATA OUT)

ADDRESS

2

t

AVAV

2

29

11

7

9

10

8

4

3

6

1

[4]

[5]

[5]

Symbols

ELQV

[4]

tELEH

[5]

t

AVQV
GLQV

[5]

t

AXQX
ELQX

[6]

EHQZ

GLQX

[6]

GHQZ
ELICCH
EHICCL

NO.

1t
2t

AVAV

3t

AVQV

4t
5t

AXQX

6t

7t

8t

9t
10 t
11 t

Parameter

t

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

[3]

t

PA

[3]

t

PS

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 12 15 20 ns
Output Hold after Address Change 3 3 3 ns
Address Change or Chip Enable to

Output Active
Address Change or Chip Disable to

Output Inactive
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

Figure 4. SRAM READ Cycle 1: Address Controlled

STK14D88-25 STK14D88-35 STK14D88-45

Min Max Min Max Min Max#1 #2 Alt.

Unit

333ns

10 13 15 ns

[4, 5, 6]

Document Number: 001-52037 Rev. ** Page 5 of 17

Figure 5. SRAM READ Cycle 2: E Controlled

[4, 7]

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STK14D88

SRAM WRITE Cycle #1 and #2

DATA OUT

E

ADDRESS

W

DATA IN

PREVIOUS DATA

12

t

AVAV

13

t

WHDX

19

t

WHAX

13

t

WLWH

18

t

AVWL

17

t

AVWH

DATA VALID

20

t

WLQZ

15

t

DVWH

HIGH IMPEDANCE

21

t

WHQX

14

t

ELWH

12

t

AVAV

16

t

EHDX

13

t

WLEH

19

t

EHAX

18

t

AVEL

17

t

AVEH

DATA VALID

15

t

DVEH

HIGH IMPEDANCE

14

t

ELEH

DATA OUT

E

ADDRESS

W

DATA IN

Notes

8. If W

is low when E goes low, the outputs remain in the high-impedance state.

9. E

or W must be ≥ VIH during address transitions.

[6, 8]

Symbols

t

AVAV

t

WLEH

t

ELEH

t

DVEH

t

EHDX

t

AVEH

t

AVEL

t

EHAX

t
t
t
t

t

t

t
t
t
t

NO.

12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t

AVAV
WLWH
ELWH
DVWH
WHDX
AVWH

AVWL

WHAX

WLQZ

WHQX

Parameter

Write Cycle Time 25 35 45 ns

WC

Write Pulse Width 20 25 30 ns

WP

Chip Enable to End of Write 20 25 30 ns

CW

Data Set-up to End of Write 10 12 15 ns

DW

Data Hold after End of Write 0 0 0 ns

DH

Address Set-up to End of Write 20 25 30 ns

AW

Address Set-up to Start of Write 0 0 0 ns

AS

Address Hold after End of Write 0 0 0 ns

WR

Write Enable to Output Disable 10 13 15 ns

WZ

Output Active after End of Write 3 3 3 ns

OW

STK14D88-25 STK14D88-35 STK14D88-45

Min Max Min Max Min Max#1 #2 Alt.

Unit

Figure 6. SRAM WRITE Cycle 1: W

Controlled

Figure 7. SRAM WRITE Cycle 2: E Controlled

[8, 9]

[8, 9]

Document Number: 001-52037 Rev. ** Page 6 of 17

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