STK14CA8
128Kx8 AutoStore™ nvSRAM
Features
ROW DECODER INPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWAR E
DETECT
A15 – A
0
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A0 A1 A2 A3 A4 A10 A
11
V
CC
V
CAP
Logic Block Diagram
■
25, 35, 45 ns Read Access and Read/Write Cycle Time
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V + 20%, -10% Operation
■
Commercial and Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvolatile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-51592 Rev. ** Revised March 04, 2009
[+] Feedback
STK14CA8
Pinouts
V
SS
A
14
A
12
A
7
A
6
DQ
0
DQ
1
V
CC
DQ
2
A
3
A
2
A
1
V
CAP
A
13
A
8
A
9
A
11
A
10
DQ
7
DQ
6
V
SS
A
0
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
23
24
A
5
NC
NC
NC
NC
NC
NC
A
4
48
47
46
45
V
CC
HSB
NC
NC
W
NC
NC
DQ
5
DQ
3
DQ
4
G
E
A
16
A
15
Note
1. See Package Diagrams on page 15 for detailed package size specifications.
A
16
A
14
A
12
A
7
DQ
0
DQ
1
DQ
2
A
4
A
2
A
1
V
CAP
A
13
A
8
A
9
A
11
A
10
DQ
7
DQ
6
V
SS
A
0
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
6
A
3
A
5
32
31
30
29
V
CC
HSB
W
DQ
5
DQ
3
DQ
4
G
E
A
15
Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC
Pin Descriptions
Pin Name I/O Description
A16-A
0
-DQ
DQ
7
0
E
V
Document Number: 001-51592 Rev. ** Page 2 of 16
W Input Write Enable: The active low W allows to write the data on the DQ pins to the address location
G Input Output Enable: The active low G input enables the data output buffers during read cycles.
V
CC
HSB
CAP
V
SS
NC No Connect Unlabeled pins have no internal connections.
Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
Input Chip Enable: The active low E input selects the device.
Power Supply Power: 3.0V, +20%, -10%.
I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
Power Supply Ground.
latched by the falling edge of E.
De-asserting G
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
nonvolatile storage elements.
Figure 3. Relative PCB Area Usage
high causes the DQ pins to tri-state.
[1]
[+] Feedback
STK14CA8
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
Voltage on DQ
or HSB......................–0.5V to (VCC + 0.5V)
0-7
...........–0.5V to (VCC + 0.5V)
SS
Temperature under Bias...............................–55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation.............................................................1W
DC Output Current (1 output at a time, 1s duration)....15 mA
DC Characteristics
(VCC = 2.7V to 3.6V)
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θ
5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
jc
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θ
6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
jc
Note: Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational section s
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Symbol Parameter
I
I
I
CC
CC
CC
Average VCC Current 65
1
Average VCC Current during
2
STORE
3
Average V
200 ns
Current at t
CC
3V, 25°C, Typical
I
CC
I
SB
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
NV
DATA
Note The HSB
Average V
4
AutoStor e Cycle
V
Standby Current
CC
(Standby, S table CMOS Levels)
Current during
CAP
Input Leakage Current ±1 ±1 μAV
Off-State Output Leakage
Current
Input Logic “1” Voltage 2.0 VCC+0.3 2.0 VCC+0.3 V All Inputs
Input Logic “0” Voltage VSS–0.5 0.8 VSS–0.5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85
Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V + 0.3V
Storage Capacitance 17 120 17 120 μFBetween V
Nonvolatile STORE operations 200 200 K
C
Data Retention 20 20 Years At 55 °C
R
pin has I
OUT
Commercial Industrial
Min Max Min Max
55
50
Units Notes
70
60
55
mA
t
= 25 ns
AVAV
mA
mA
= 35 ns
t
AVAV
t
= 45 ns
AVAV
Dependent on output loading and cycle
rate. V alues obtained without output loads.
3 3 mA All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (t
STORE
AVAV
=
10 10 mA W ≥ (V
All Other Inputs Cycling at CMOS Levels
CC
– 0.2V)
Dependent on output loading and cycle
rate. V alues obtained without output loads.
3 3 mA All Inputs Don’t Care
Average current for duration of STORE
cycle (t
STORE
33mAE
≥ (
VCC -0.2V)
All Others V
Standby current level after nonvolatile
cycle complete
= max
CC
V
= VSS to V
IN
±1 ±1 μAV
°
C
= max
CC
= VSS to VCC, E or G ≥ VIH
V
IN
= –2 mA
OUT
= 4 mA
OUT
=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested.
)
)
≤
0.2V or ≥ (VCC-0.2V)
IN
CC
pin and VSS, 5V rated.
CAP
Document Number: 001-51592 Rev. ** Page 3 of 16
[+] Feedback
STK14CA8
AC Test Conditions
577 Ohms
30 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
577 Ohms
5 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
Note
2. These parameters are guaranteed but not tested.
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times ................................................. ≤ 5 ns
Input and Output Timing Reference Levels....................1.5V
Output Load..................................See Figure 4 and Figure 5
Capacitance
(TA = 25°C, f = 1.0 MHz)
Symbol Parameter
C
C
IN
OUT
Input Capacitance 7 pF
Output Capacitance 7 pF
[2]
Max Units Conditions
Figure 4. AC Output Loading
Δ
V = 0 to 3V
Δ
V = 0 to 3V
Document Number: 001-51592 Rev. ** Page 4 of 16
Figure 5. AC Output Loading for Tristate Specifications
(t
HZ
, tLZ, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
)
[+] Feedback
STK14CA8
SRAM READ Cycles #1 and #2
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
Notes
3. W
must be high during SRAM READ cycles.
4. Device is continuously selected with E
and G both low
5. Measured ± 200mV from steady state output voltage.
6. HSB
must remain high during READ and WRITE cycles
2
29
11
7
9
10
8
4
3
6
1
NO.
1
2tAVAV
3tAVQV
4
5tAXQX
6
7
8
9
10
11
Symbols
Parameter
STK14CA8-25 STK14CA8-35 STK14CA8-45
#1 #2 Alt. Min Max Min Max Min Max
[3]
[4]
[4]
t
ELQV
t
ELEH
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
t
ELICCH
t
EHICCL
t
ACS
[3]
t
RC
[4]
t
AA
t
OE
[4]
t
OH
t
LZ
[5]
t
HZ
t
OLZ
[5]
t
OHZ
[2]
t
PA
[2]
t
PS
Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 12 15 20 ns
Output Hold after Address Change 3 3 3 ns
Address Change or Chip Enable to
333ns
Output Active
Address Change or Chip Disable to
10 13 15 ns
Output Inactive
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns
Figure 6. SRAM READ Cycle #1: Address Controlled
[3, 4, 6]
Units
Document Number: 001-51592 Rev. ** Page 5 of 16
Figure 7. SRAM READ Cycle #2: E and G Controlled
[3, 6]
[+] Feedback
STK14CA8
SRAM WRITE Cycles #1 and #2
Notes
7. If W
is low when E goes low, the outputs remain in the high impedance state.
8.
E or W must be ≥ V
IH
during address transitions.
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
NO.
12
13
14
15
16
17
18
19
20
21
Symbols
Parameter
STK14CA8-25 STK14CA8-35 STK14CA8-45
#1 #2 Alt. Min Max Min Max Min Max
t
AVAV
t
WLWHtWLEH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
t
WHQX
[5,7]
t
AVAV
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
t
Write Cycle Time 25 35 45 ns
WC
t
Write Pulse Width 20 25 30 ns
WP
t
Chip Enable to End of Write 20 25 30 ns
CW
t
Data Setup to End of Write 10 12 15 ns
DW
t
Data Hold after End of Write 0 0 0 ns
DH
t
Address Setup to End of Write 20 25 30 ns
AW
t
Address Setup to Start of Write 0 0 0 ns
AS
t
Address Hold after End of Write 0 0 0 ns
WR
t
Write Enable to Output Disable 10 1 3 15 ns
WZ
t
Output Active after End of Write 3 3 3 ns
OW
Figure 8. SRAM WRITE Cycle #1: W Controlled
[7,8]
Units
Document Number: 001-51592 Rev. ** Page 6 of 16
Figure 9. SRAM WRITE Cycle #2: E Controlled
[7,8]
[+] Feedback
STK14CA8
AutoStore/POWER UP RECALL
Notes
9. t
HRECALL
starts from the time VCC rises above V
SWITCH
10.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place
11.Industrial Grade devices require maximum 15 ms.
25
23 23
22
22
NO.
22
23
24
25
t
Symbols
Standard Alternate Min Max
t
HRECALL
t
STORE
V
SWITCH
V
CCRISE
t
HLHZ
Power up RECALL Duration 20 ms 9
STORE Cycle Duration 12.5 ms 10, 11
Low Voltage T rigger Level 2.65 V
V
Rise Time 150 μs
CC
Parameter
STK14CA8
Units Notes
Figure 10. AutoStore/POWER UP RECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while V
Document Number: 001-51592 Rev. ** Page 7 of 16
is below V
CC
SWITCH.
[+] Feedback
STK14CA8
Software Controlled STORE/RECALL Cycle
26
26
27
28
29
23 30
26 26
27 28
29
23 30
Notes
12.The software sequence is clocked on the falling edge of E
controlled READs or G controlled READs
13.The six consecutive addresses must be read in the order listed in the Software ST ORE/RECALL Mode Selection Table. W
must be high during all six consecutive cycles.
NO.
Symbols
Parameter
[12,13]
STK14CA8-35 STK14CA8-35 STK14CA8-45
E Cont G Cont Alt Min Max Min Max Min Max
26tAVAV
27tAVELtAVGLtAS
28tELEHtGLGHtCW
29tEHAXtGHAX
30tRECALLtRECALL
t
AVAVtRC
STORE/RECALL Initiation Cycle
25 35 45 ns 13
Time
Address Setup Time 0 0 0 ns
Clock Pulse Width 20 25 30 ns
Address Hold Time 1 1 1 ns
RECALL Duration 50 50 50 μs
Figure 11. Software STORE/RECALL CYCLE: E Controlled
[13]
Units Notes
Figure 12. Software STORE/RECALL CYCLE: G Controlled
Document Number: 001-51592 Rev. ** Page 8 of 16
[13]
[+] Feedback
STK14CA8
Hardware STORE Cycle
32
23
31
33 33
Notes
14.On a hardware STORE initiation, SRAM operation continues to be enabled for time t
DELAY
to allow read/write cycles to complete.
15.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
NO.
31tDELAY
32tHLHX
Symbols
Standard Alternate Min Max
t
HLQZ
Hardware STORE to SRAM Disabled 1 7 0 μs 14
Hardware STORE Pulse Width 15 ns
Soft Sequence Commands
Parameter
Figure 13. Hardware STORE Cycle
STK14CA8
Units Notes
NO.
33tSS
Symbols Parameter STK14CA8 Units Notes
Standard Min Max
Soft Sequence Processing Time 70 μs15, 16
Figure 14. Software Sequence Commands
Document Number: 001-51592 Rev. ** Page 9 of 16
[+] Feedback
STK14CA8
Mode Selection
Notes
17.The six consecutive addresses must be in the order listed. W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
18.While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
19.I/O state depends on the state of G
. The I/O table shown assumes G low
E W G A16-A
0
Mode I/O Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08FC0 Nonvolatile Store Output High Z I
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Active
Active 17, 18, 19
CC2
Active
17, 18, 19
17, 18, 19
17, 18, 19
Document Number: 001-51592 Rev. ** Page 10 of 16
[+] Feedback
STK14CA8
nvSRAM Operation
V
CC
V
CAP
10k Ohm
0.1µF
V
CC
V
CAP
W
nvSRAM
The STK14CA8 nvSRAM has two functional components paired
in the same physical cell. These are the SRAM memory cell and
a nonvolatile QuantumTrap cell. The SRAM memory cell
operates similar to a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the STORE operation),
or from the nonvolatile cell to SRAM (the RECALL operation).
This unique architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL operations, SRAM
READ and WRITE operations are inhibited. The STK14CA8
supports unlimited read and writes similar to a typical SRAM. In
addition, it provides unlimited RECALL operations from the
nonvolatile cells and up to 200K STORE operations.
SRAM READ
The STK14CA8 performs a READ cycle whenever E and G are
low while W
A
0-16
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
initiated by E
whichever is later (READ cycle #2). The data outputs repeatedly
responds to address changes within the t
without the need for transitions on any control input pins, and
remains valid until another address change or until E or G is
brought high, or W
and HSB are high. The address specified on pins
determine which of the 131,072 data bytes are accessed.
(READ cycle #1). If the READ is
and G, the outputs are valid at t
AVQV
or at t
ELQV
access time
AVQV
GLQV
and HSB is brought low.
on page 3 for the size of the capacitor. The voltage on the V
pin is driven to 5V by a charge pump internal to the chip. A pull
up should be placed on W
to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB
signal can be monitored by the system to detect
an AutoStore cycle is in progress.
Figure 15. AutoStore Mode
,
CAP
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E
or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid t
of a W
controlled WRITE or t
controlled WRITE.
It is recommended that G
be kept high during the entire WRITE
before the end of an E
DVEH
cycle to avoid data bus contention on common I/O lines. If G
left low, internal circuitry turns off the output buffers t
goes low.
W
before the end
DVWH
WLQZ
is
after
AutoStore Operation
The STK14CA8 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14CA8.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
CC
operation is initiated with power provided by the V
pin drops below V
pin from VCC. A STORE
CAP
Figure 15 shows the proper connection of the storage capacitor
) for automatic store operation. Refer to DC Characteristics
(V
CAP
pin. This stored
CAP
SWITCH
CAP
capacitor.
to
CC
, the part
Hardware STORE (HSB) Operation
The STK14CA8 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
pin is used to
pin is driven
low, the STK14CA8 conditionally initiates a STORE operation
after t
the SRAM took place since the last STORE or RECALL cycle.
. An actual STORE cycle only begins if a WRITE to
DELAY
The HSB pin has a very resistive pull up and is internally driven
low to indicate a busy condition while the STORE (initiated by
any means) is in progress. This pin should be externally pulled
up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in progress when
HSB
is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB
STK14CA8 continues to allow SRAM operations for t
During t
If a WRITE is in progress when HSB
time t
requested after HSB
, multiple SRAM READ operations may take place.
DELAY
to complete. However, any SRAM WRITE cycles
DELAY
goes low are inhibited until HSB retu rns
is pulled low, it is allowed a
goes low, the
DELAY
high.
If HSB
is not used, it should be left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC<VSWITCH
again exceeds the sense voltage of V
V
CC
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When
, a RECALL
SWITCH
HRECALL
to complete.
.
Document Number: 001-51592 Rev. ** Page 11 of 16
[+] Feedback
STK14CA8
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14CA8
software STORE cycle is initiated by executing sequential E
controlled or G controlled READ cycles from six specific address
locations in exact order. During the ST ORE cycle, previous dat a
is erased and then the new data is programmed into the nonvolatile elements. After a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
To initiate the software STORE cycle, the following READ
sequence must be performed:
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x8FC0 Initiate STORE Cycle
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence
and that G
SRAM is again activated for READ and WRITE operation.
is active. After the t
cycle time is fulfilled, the
STORE
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E
controlled READ operations must be performed:
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the t
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
controlled or G
cycle time, the
RECALL
Data Protection
The STK14CA8 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low voltage condition is detected when
V
CC<VSWITCH
If the STK14CA8 is in a WRITE mode (both E
.
and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E
or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The STK14CA8 is a high speed memory and so must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
and VSS, using leads and traces that are a short
CC
power, ground, and signals reduce circuit noise.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, etc. should always program a unique NV
pattern (for example, complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state such as AutoStore enabled. While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on.)
■
If AutoStore is firmware disabled, it does not reset to “AutoStore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
AutoStore on each reset sequence based on the behavior
desired.
■
The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
nvSRAM internal algorithm calculates V
on this max Vcap value. Customers that want to use a larger
V
time should discuss their V
understand any impact on the V
a t
value specified in this data sheet includes a minimum
cap
value because the
cap
charge time based
cap
value to make sure there is extra store charge and store
cap
RECALL
period.
size selection with Cypress to
cap
voltage level at the end of
cap
Document Number: 001-51592 Rev. ** Page 12 of 16
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STK14CA8
Low Average Active Power
CMOS technology provides the STK14CA8 with the benefit of
power supply current that scales with cycle time. Less current is
drawn as the memory cycle time becomes longer than 50 ns.
Figure 16 shows the relationship between I
READ/WRITE cycle time. Worst case current consumption is
shown for commercial temperature range, VCC=3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14CA8 depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for operations
3. The ratio of READs to WRITEs
4. The operating temperature
5. The VCC Level
6. I/O Loading
Figure 16. Current vs Cycle Time
CC
and
Preventing AutoStore
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations
is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following
sequence of E
be performed:
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x8B45 AutoStore Disable
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed
in a manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following seq uence of E
controlled or G controlled READ operations must be performed:
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x4B46 AutoStore Enable
controlled or G controlled READ operations must
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Document Number: 001-51592 Rev. ** Page 13 of 16
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STK14CA8
Ordering Information
Packing Option
Blank=Tube
TR=Tape and Reel
Temperature Range
Blank=Commercial (0 to +70 C)
I= Industrial (-45 to +85 C)
Access Time
25=25 ns
35=35 ns
45=45 ns
Lead Finish
F=100% Sn (Matte Tin) RoHS Compliant
Package
N=Plastic 32-pin 300 mil SOIC (50 mil pitch)
R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
STK14CA8-R F 45 ITR
Ordering Codes
Part Number Description Access Times Temperature
STK14CA8-NF25 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14CA8-NF35 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14CA8-NF45 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14CA8-NF25TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14CA8-NF35TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14CA8-NF45TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14CA8-RF25 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14CA8-RF35 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14CA8-RF45 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14CA8-RF25TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14CA8-RF35TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14CA8-RF45TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14CA8-NF25I 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Industrial
STK14CA8-NF35I 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Industrial
STK14CA8-NF45I 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Industrial
STK14CA8-NF25ITR 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Industrial
STK14CA8-NF35ITR 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Industrial
STK14CA8-NF45ITR 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Industrial
STK14CA8-RF25I 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Industrial
STK14CA8-RF35I 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Industrial
STK14CA8-RF45I 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Industrial
STK14CA8-RF25ITR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Industrial
STK14CA8-RF35ITR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Industrial
STK14CA8-RF45ITR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Industrial
Document Number: 001-51592 Rev. ** Page 14 of 16
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STK14CA8
Package Diagrams
51-85127 *A
51-85061 *C
Figure 17. 32-Pin 300 mil SOIC (51-85127)
Figure 18. 48-Pin 300 mil SSOP (51-85061)
Document Number: 001-51592 Rev. ** Page 15 of 16
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STK14CA8
Document History Page
Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM
Document Number: 001-51592
Revision ECN
Orig. of
Change
Submission
Date
Description of Change
** 2665610 GVCH/PYRS 02/04/09 New data sheet
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critica l
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of,
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integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spe cified above is prohibited wi thout
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51592 Rev. ** Revised March 04, 2009 Page 16 of 16
AutoStore and QuantumTrap are registered tr ademar ks of Cy press Semico nduct or Corpora tion. All other produc ts and c ompany name s mentioned in this document may be the trademarks of their
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