Cypress STK14CA8 User Manual

STK14CA8

128Kx8 AutoStore™ nvSRAM

Features

ROW DECODER INPUT BUFFERS

COLUMN DEC

G

E
W

COLUMN I/O

POWER

CONTROL

HSB

STORE/
RECALL

CONTROL

SOFTWAR E

DETECT

A15 – A

0

A

5

A

6

A

7

A

8

A

9

A

12

A

13

A

14

A

15

A

16

Quantum Trap

1024 X 1024

STATIC RAM

ARRAY

1024 X 1024

STORE

RECALL

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

A0 A1 A2 A3 A4 A10 A

11

V

CC

V

CAP

Logic Block Diagram

■

25, 35, 45 ns Read Access and Read/Write Cycle Time

■

Unlimited Read/Write Endurance

■

Automatic Nonvolatile STORE on Power Loss

■

Nonvolatile STORE Under Hardware or Software Control

■

Automatic RECALL to SRAM on Power Up

■

Unlimited RECALL Cycles

■

200K STORE Cycles

■

20-Year Nonvolatile Data Retention

■

Single 3.0V + 20%, -10% Operation

■

Commercial and Industrial Temperatures

■

Small Footprint SOIC and SSOP Packages (RoHS Compliant)

Description

The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol­atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.

Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-51592 Rev. ** Revised March 04, 2009

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STK14CA8

Pinouts

V

SS

A

14

A

12

A

7

A

6

DQ

0

DQ

1

V

CC

DQ

2

A

3

A

2

A

1

V

CAP

A

13

A

8

A

9

A

11

A

10

DQ

7

DQ

6

V

SS

A

0

NC

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

NC

NC
NC

23
24

A

5

NC

NC
NC
NC

NC

NC

A

4

48
47
46
45

V

CC

HSB

NC
NC

W

NC
NC

DQ

5

DQ

3

DQ

4

G

E

A

16

A

15

Note

1. See Package Diagrams on page 15 for detailed package size specifications.

A

16

A

14

A

12

A

7

DQ

0

DQ

1

DQ

2

A

4

A

2

A

1

V

CAP

A

13

A

8

A

9

A

11

A

10

DQ

7

DQ

6

V

SS

A

0

28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A

6

A

3

A

5

32
31
30
29

V

CC

HSB
W

DQ

5

DQ

3

DQ

4

G

E

A

15

Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC

Pin Descriptions

Pin Name I/O Description

A16-A

0

-DQ

DQ

7

0

E

V

Document Number: 001-51592 Rev. ** Page 2 of 16

W Input Write Enable: The active low W allows to write the data on the DQ pins to the address location

G Input Output Enable: The active low G input enables the data output buffers during read cycles.

V

CC

HSB

CAP

V

SS

NC No Connect Unlabeled pins have no internal connections.

Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.

I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM.

Input Chip Enable: The active low E input selects the device.

Power Supply Power: 3.0V, +20%, -10%.

I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low

Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to

Power Supply Ground.

latched by the falling edge of E.

De-asserting G

external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).

nonvolatile storage elements.

Figure 3. Relative PCB Area Usage

high causes the DQ pins to tri-state.

[1]

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STK14CA8

Absolute Maximum Ratings

Voltage on Input Relative to Ground.................–0.5V to 4.1V

Voltage on Input Relative to V
Voltage on DQ

or HSB......................–0.5V to (VCC + 0.5V)

0-7

...........–0.5V to (VCC + 0.5V)

SS

Temperature under Bias...............................–55°C to 125°C

Junction Temperature................................... –55°C to 140°C

Storage Temperature.................................... –65°C to 150°C

Power Dissipation.............................................................1W

DC Output Current (1 output at a time, 1s duration)....15 mA

DC Characteristics

(VCC = 2.7V to 3.6V)

NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS

θ

5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].

jc

RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS

θ

6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].

jc

Note: Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational section s
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

Symbol Parameter

I

I

I

CC

CC

CC

Average VCC Current 65

1

Average VCC Current during

2

STORE

3

Average V
200 ns

Current at t

CC

3V, 25°C, Typical

I

CC

I

SB

I

ILK

I

OLK

V

IH

V

IL

V

OH

V

OL

T

A

V

CC

V

CAP

NV
DATA

Note The HSB

Average V

4

AutoStor e Cycle

V

Standby Current

CC

(Standby, S table CMOS Levels)

Current during

CAP

Input Leakage Current ±1 ±1 μAV

Off-State Output Leakage
Current

Input Logic “1” Voltage 2.0 VCC+0.3 2.0 VCC+0.3 V All Inputs
Input Logic “0” Voltage VSS–0.5 0.8 VSS–0.5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85
Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V + 0.3V
Storage Capacitance 17 120 17 120 μFBetween V
Nonvolatile STORE operations 200 200 K

C

Data Retention 20 20 Years At 55 °C

R

pin has I

OUT

Commercial Industrial

Min Max Min Max

55
50

Units Notes

70
60
55

mA

t

= 25 ns

AVAV

mA
mA

= 35 ns

t

AVAV

t

= 45 ns

AVAV

Dependent on output loading and cycle
rate. V alues obtained without output loads.

3 3 mA All Inputs Don’t Care, VCC = max

Average current for duration of STORE
cycle (t

STORE

AVAV

=

10 10 mA W ≥ (V

All Other Inputs Cycling at CMOS Levels

CC

– 0.2V)

Dependent on output loading and cycle
rate. V alues obtained without output loads.

3 3 mA All Inputs Don’t Care

Average current for duration of STORE
cycle (t

STORE

33mAE

≥ (

VCC -0.2V)
All Others V
Standby current level after nonvolatile
cycle complete

= max

CC

V

= VSS to V

IN

±1 ±1 μAV

°

C

= max

CC

= VSS to VCC, E or G ≥ VIH

V

IN

= –2 mA

OUT

= 4 mA

OUT

=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested.

)

)

≤

0.2V or ≥ (VCC-0.2V)

IN

CC

pin and VSS, 5V rated.

CAP

Document Number: 001-51592 Rev. ** Page 3 of 16

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STK14CA8

AC Test Conditions

577 Ohms

30 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

577 Ohms

5 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

Note

2. These parameters are guaranteed but not tested.

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times ................................................. ≤ 5 ns

Input and Output Timing Reference Levels....................1.5V

Output Load..................................See Figure 4 and Figure 5

Capacitance

(TA = 25°C, f = 1.0 MHz)

Symbol Parameter

C
C

IN
OUT

Input Capacitance 7 pF
Output Capacitance 7 pF

[2]

Max Units Conditions

Figure 4. AC Output Loading

Δ

V = 0 to 3V

Δ

V = 0 to 3V

Document Number: 001-51592 Rev. ** Page 4 of 16

Figure 5. AC Output Loading for Tristate Specifications

(t

HZ

, tLZ, t

WLQZ

, t

WHQZ

, t

GLQX

, t

GHQZ

)

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STK14CA8

SRAM READ Cycles #1 and #2

DATA VALID

5

t

AXQX

3

t

AVQV

DQ (DATA OUT)

ADDRESS

2

t

AVAV

Notes

3. W

must be high during SRAM READ cycles.

4. Device is continuously selected with E

and G both low

5. Measured ± 200mV from steady state output voltage.

6. HSB

must remain high during READ and WRITE cycles

2

29

11

7

9

10

8

4

3

6

1

NO.

1
2tAVAV
3tAVQV
4
5tAXQX
6

7

8

9
10
11

Symbols

Parameter

STK14CA8-25 STK14CA8-35 STK14CA8-45

#1 #2 Alt. Min Max Min Max Min Max

[3]

[4]

[4]

t

ELQV

t

ELEH

t

AVQV

t

GLQV

t

AXQX

t

ELQX

t

EHQZ

t

GLQX

t

GHQZ

t

ELICCH

t

EHICCL

t

ACS

[3]

t

RC

[4]

t

AA

t

OE

[4]

t

OH

t

LZ

[5]

t

HZ

t

OLZ

[5]

t

OHZ

[2]

t

PA

[2]

t

PS

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 12 15 20 ns
Output Hold after Address Change 3 3 3 ns
Address Change or Chip Enable to

333ns

Output Active
Address Change or Chip Disable to

10 13 15 ns

Output Inactive
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

Figure 6. SRAM READ Cycle #1: Address Controlled

[3, 4, 6]

Units

Document Number: 001-51592 Rev. ** Page 5 of 16

Figure 7. SRAM READ Cycle #2: E and G Controlled

[3, 6]

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