Cypress STK14C88-5 User Manual
STK14C88-5
256 Kbit (32K x 8) AutoStore nvSRAM
Features
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13
- A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
Functional Description
■ 35 ns and 45 ns access times
■ Hands off automatic STORE on power down with external 68
µF capacitor
■ STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■ RECALL to SRAM initiated by software or power up
■ Unlimited READ, WRITE, and RECALL cycles
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5V+10% operation
■ Military temperature
■ 32-pin (300 mil) CDIP and LCC (450 mil) packages
The Cypress STK14C88-5 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvol atile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB
pin.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-51038 Rev. ** Revised March 02, 2009
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STK14C88-5
Pin Configurations
Figure 1. Pin Diagram: 32-Pin DIP
Figure 2. Pin Diagram: 32-Pin LCC
Pin Definitions
Pin Name Alt IO Type Description
A
0–A14
DQ0-DQ
7
WE
CE
OE
V
SS
V
CC
HSB
V
CAP
W
E
G
Input Ad dress Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Input Chip Enable Input, Active LOW. When LOW, select s the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
HIGH causes the IO pins to tri-state.
Document Number: 001-51038 Rev. ** Page 2 of 17
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STK14C88-5
Device Operation
The STK14C88-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-5 supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK14C88-5 performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until
determines the 32,768 data bytes accessed. When
0–14
(READ cycle 1). If the READ is initiated
or OE, the outputs are valid at t
AA
or at t
ACE
access time without the need for
AA
, whichever
DOE
another address change or until CE or OE is brought HIGH, or
WE
or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
is HIGH. The address inputs must be stable prior to entering
HSB
the WRITE cycle and must remain stable until either CE
or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE
are written into the memory if it has valid tSD, before
0–7
controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, internal circuitry turns off the output buffers t
goes LOW.
HZWE
is left
after WE
AutoStore Operation
The STK14C88-5 stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK14C88-5.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
pin drops below V
CC
pin from VCC. A STORE
CAP
pin. This stored
CAP
SWITCH
CAP
Figure 3 shows the proper connection of the storage capacitor
) for automatic store operation. A charge storage capacitor
(V
CAP
to
CC
, the part
capacitor.
having a capacitor of between 68uF and 220uF (+
6V should be provided. The voltage on the V
5V by a charge pump internal to the chip. A pull up is placed on
WE
to hold it inactive during power up.
20%) rated at
pin is driven to
CAP
Figure 3. AutoStore Mode
In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the
CC
and V
are connected to the
CAP
AutoStore function of the STK14C88-5 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE
cycle.
does not drop below 3.6V during the 10 ms
CC
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB
signal is monitored by the system to detect if an
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
between V
of current between V
, then a 2.2 ohm resistor should be connected
SWITCH
and the system supply to avoid momentary excess
CC
CC
and V
CAP
.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and + 5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
(Figure 4). This is
CAP
disabled. If the STK14C88-5 is operated in this configuration,
references to V
sheet. In this mode, STORE
software control or the HSB
are changed to V
CC
operations are triggered through
pin. To enable or disable Autostore
throughout this data
CAP
using an I/O port pin see “” on page 5. It is not permissible to
change between these three options” on the fly”.
CC
.
Document Number: 001-51038 Rev. ** Page 3 of 17
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STK14C88-5
Figure 4. AutoStore Inhibit Mode
Hardware STORE (HSB) Operation
The STK14C88-5 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB
pin is used to
pin is driven
LOW, the STK14C88-5 conditionally initiates a STORE
operation after t
WRITE to the SRAM takes place since the last STORE or
. An actual STORE cycle only begins if a
DELAY
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress. Pull up this
pin with an external 10K ohm resistor to V
a driver.
if HSB is used as
CAP
SRAM READ and WRITE operations, that are in progress when
HSB
is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB
the STK14C88-5 continues SRAM operations for t
t
, multiple SRAM READ operations take place. If a WRITE
DELAY
is in progress when HSB
is pulled LOW, it allows a time, t
to complete. However, any SRAM WRITE cycles requested af ter
HSB
goes LOW are inhibited until HSB returns HIGH.
goes LOW,
. During
DELAY
DELAY
During any STORE operation, regardless of how it is initiated,
the STK14C88-5 continues to drive the HSB
pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the STK14C88-5 remains disabled until the
HSB
pin returns HIGH.
If HSB
is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
), an internal RECALL request is latched. When V
RESET
SWITCH
HRECALL
, a RECALL
to complete.
CC
If the STK14C88-5 is in a WRITE
RECALL, the SRAM
data is corrupted. To help avoid this
state at the end of power up
situation, a 10 Kohm resistor is connected either be tween WE
and system VCC or between CE and system VCC.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK14C88-5 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE
controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE
t
cycle time is fulfilled, the SRAM is again activated for
STORE
READ and WRITE operation.
is LOW for a valid sequence. After the
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
controlled READ operations is
cycle time, the SRAM is once
RECALL
Document Number: 001-51038 Rev. ** Page 4 of 17
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STK14C88-5
Data Protection
The STK14C88-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
WRITE mode (both CE
is less than V
CC
. If the STK14C88-5 is in a
SWITCH
and WE are low) at power up after a
RECALL or after a STORE, the WRITE is inhibited until a
negative transition on CE or WE is detected. This protects
against inadvertent writes during power up or brown out conditions.
Noise Considerations
The STK14C88-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
CC
and V
using leads and traces that are as short
SS,
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK14C88-5 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage conditions. When V
operations and SRAM WRITEs are inhibited. AutoStore can be
CAP<VSWITCH
completely disabled by tying VCC to ground and applying + 5V
to V
STOREs are only initiated by explicit request using either the
. This is the AutoStore Inhibit mode; in this mode,
CAP
software sequence or the HSB
, all externally initiated STORE
pin.
Figure 5. Current Versus Cycle Time (READ)
Figure 6. Current Versus Cycle Time (WRITE)
Low Average Active Power
CMOS technology provides the STK14C88-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 5 and Figure 6 shows the relationship
between I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK14C88-5
depends on the following items:
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of READs to WRITEs
■ CMOS versus TTL input levels
■ The operating temperature
■ The V
■ IO loading
and READ or WRITE cycle time. Worst case current
CC
level
CC
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it has to overpower the internal pull down device. This
device drives HSB
LOW for 20 μs at the onset of a STORE.
When the STK14C88-5 is connected for AutoStore operation
(system V
and V
attempts to pull HSB
V
, the part stops trying to pull HSB LOW and abort the STORE
IL
attempt.
connected to VCC and a 68 μF capacitor on V
CC
crosses V
CC
on the way down, the STK14C88-5
SWITCH
LOW. If HSB does not actually get below
of at least 2.2V,
OH
CAP
)
Document Number: 001-51038 Rev. ** Page 5 of 17
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STK14C88-5
Best Practices
Notes
1. I/O state assumes OE
< VIL. Activation of nonvolatile cycles does not depend on st ate of OE.
2. HSB
STORE operation occurs only if an SRAM WRITE has been done since the last nonvola tile cycle. Afte r the STORE (if any) comp letes, the par t goes into standby
mode, inhibiting all operations until HSB
rises.
3. CE
and OE LOW and WE HIGH for output behavior.
4. The six consecutive addresses must be in the order listed. WE
must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
5. While there are 15 addresses on the STK14C88-5, only the lower 14 are used to control software modes.
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■ The V
and a maximum value size. Best practice is to meet this
value specified in this data sheet includes a minimum
CAP
requirement and not exceed the maximum V
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to use a larger
V
value to make sure there is extra store charge should
CAP
discuss their V
any impact on the V
period.
size selection with Cypress to understand
CAP
voltage level at the end of a t
CAP
Table 1. Hardware Mode Selection
CE WE HSB A13–A0 Mode IO Power
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z
L H H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
L H H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
value because
CAP
Active
I
Active I
Active
[1]
[2]
CC2
[1, 3, 4, 5]
CC2
[1, 3, 4, 5]
RECALL
Document Number: 001-51038 Rev. ** Page 6 of 17
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