Cypress STK14C88-5 User Manual

STK14C88-5

256 Kbit (32K x 8) AutoStore nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

13

- A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

Functional Description

■ 35 ns and 45 ns access times

■ Hands off automatic STORE on power down with external 68

µF capacitor

■ STORE to QuantumTrap™ nonvolatile elements is initiated by

software, hardware, or AutoStore™ on power down

■ RECALL to SRAM initiated by software or power up

■ Unlimited READ, WRITE, and RECALL cycles

■ 1,000,000 STORE cycles to QuantumTrap

■ 100 year data retention to QuantumTrap

■ Single 5V+10% operation

■ Military temperature

■ 32-pin (300 mil) CDIP and LCC (450 mil) packages

The Cypress STK14C88-5 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvol atile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB

pin.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-51038 Rev. ** Revised March 02, 2009

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STK14C88-5

Pin Configurations

Figure 1. Pin Diagram: 32-Pin DIP

Figure 2. Pin Diagram: 32-Pin LCC

Pin Definitions

Pin Name Alt IO Type Description

A

0–A14

DQ0-DQ

7

WE

CE
OE

V

SS

V

CC

HSB

V

CAP

W

E
G

Input Ad dress Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.
Input Chip Enable Input, Active LOW. When LOW, select s the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

HIGH causes the IO pins to tri-state.

Document Number: 001-51038 Rev. ** Page 2 of 17

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STK14C88-5

Device Operation

The STK14C88-5 nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-5 supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to one million STORE
operations.

SRAM Read

The STK14C88-5 performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until

determines the 32,768 data bytes accessed. When

0–14

(READ cycle 1). If the READ is initiated

or OE, the outputs are valid at t

AA

or at t

ACE

access time without the need for

AA

, whichever

DOE

another address change or until CE or OE is brought HIGH, or
WE

or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the WRITE cycle and must remain stable until either CE

or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, internal circuitry turns off the output buffers t
goes LOW.

HZWE

is left

after WE

AutoStore Operation

The STK14C88-5 stores data to nvSRAM using one of three
storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK14C88-5.

During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V

pin drops below V

CC

pin from VCC. A STORE

CAP

pin. This stored

CAP

SWITCH

CAP

Figure 3 shows the proper connection of the storage capacitor

) for automatic store operation. A charge storage capacitor

(V

CAP

to

CC

, the part

capacitor.

having a capacitor of between 68uF and 220uF (+
6V should be provided. The voltage on the V
5V by a charge pump internal to the chip. A pull up is placed on
WE

to hold it inactive during power up.

20%) rated at

pin is driven to

CAP

Figure 3. AutoStore Mode

In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the

CC

and V

are connected to the

CAP

AutoStore function of the STK14C88-5 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE

cycle.

does not drop below 3.6V during the 10 ms

CC

To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB

signal is monitored by the system to detect if an

AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc

reaches V
between V
of current between V

, then a 2.2 ohm resistor should be connected

SWITCH

and the system supply to avoid momentary excess

CC

CC

and V

CAP

.

AutoStore Inhibit mode

If an automatic STORE on power loss is not required, then V
is tied to ground and + 5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is

(Figure 4). This is

CAP

disabled. If the STK14C88-5 is operated in this configuration,
references to V
sheet. In this mode, STORE
software control or the HSB

are changed to V

CC

operations are triggered through

pin. To enable or disable Autostore

throughout this data

CAP

using an I/O port pin see “” on page 5. It is not permissible to
change between these three options” on the fly”.

CC

.

Document Number: 001-51038 Rev. ** Page 3 of 17

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STK14C88-5

Figure 4. AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

The STK14C88-5 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
request a hardware STORE cycle. When the HSB

pin is used to

pin is driven
LOW, the STK14C88-5 conditionally initiates a STORE
operation after t
WRITE to the SRAM takes place since the last STORE or

. An actual STORE cycle only begins if a

DELAY

RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress. Pull up this
pin with an external 10K ohm resistor to V
a driver.

if HSB is used as

CAP

SRAM READ and WRITE operations, that are in progress when
HSB

is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB
the STK14C88-5 continues SRAM operations for t
t

, multiple SRAM READ operations take place. If a WRITE

DELAY

is in progress when HSB

is pulled LOW, it allows a time, t
to complete. However, any SRAM WRITE cycles requested af ter
HSB

goes LOW are inhibited until HSB returns HIGH.

goes LOW,

. During

DELAY

DELAY

During any STORE operation, regardless of how it is initiated,
the STK14C88-5 continues to drive the HSB

pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the STK14C88-5 remains disabled until the
HSB

pin returns HIGH.

If HSB

is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

), an internal RECALL request is latched. When V

RESET

SWITCH

HRECALL

, a RECALL

to complete.

CC

If the STK14C88-5 is in a WRITE
RECALL, the SRAM

data is corrupted. To help avoid this

state at the end of power up

situation, a 10 Kohm resistor is connected either be tween WE
and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK14C88-5 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE

controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE
t

cycle time is fulfilled, the SRAM is again activated for

STORE

READ and WRITE operation.

is LOW for a valid sequence. After the

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

controlled READ operations is

cycle time, the SRAM is once

RECALL

Document Number: 001-51038 Rev. ** Page 4 of 17

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STK14C88-5

Data Protection

The STK14C88-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
WRITE mode (both CE

is less than V

CC

. If the STK14C88-5 is in a

SWITCH

and WE are low) at power up after a
RECALL or after a STORE, the WRITE is inhibited until a
negative transition on CE or WE is detected. This protects
against inadvertent writes during power up or brown out condi­tions.

Noise Considerations

The STK14C88-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of

CC

and V

using leads and traces that are as short

SS,

power, ground, and signals reduce circuit noise.

Hardware Protect

The STK14C88-5 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi­tions. When V
operations and SRAM WRITEs are inhibited. AutoStore can be

CAP<VSWITCH

completely disabled by tying VCC to ground and applying + 5V
to V
STOREs are only initiated by explicit request using either the

. This is the AutoStore Inhibit mode; in this mode,

CAP

software sequence or the HSB

, all externally initiated STORE

pin.

Figure 5. Current Versus Cycle Time (READ)

Figure 6. Current Versus Cycle Time (WRITE)

Low Average Active Power

CMOS technology provides the STK14C88-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 5 and Figure 6 shows the relationship
between I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK14C88-5
depends on the following items:

■ The duty cycle of chip enable

■ The overall cycle rate for accesses

■ The ratio of READs to WRITEs

■ CMOS versus TTL input levels

■ The operating temperature

■ The V

■ IO loading

and READ or WRITE cycle time. Worst case current

CC

level

CC

Preventing Store

The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it has to overpower the internal pull down device. This
device drives HSB

LOW for 20 μs at the onset of a STORE.
When the STK14C88-5 is connected for AutoStore operation
(system V
and V
attempts to pull HSB
V

, the part stops trying to pull HSB LOW and abort the STORE

IL

attempt.

connected to VCC and a 68 μF capacitor on V

CC

crosses V

CC

on the way down, the STK14C88-5

SWITCH

LOW. If HSB does not actually get below

of at least 2.2V,

OH

CAP

)

Document Number: 001-51038 Rev. ** Page 5 of 17

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STK14C88-5

Best Practices

Notes

1. I/O state assumes OE

< VIL. Activation of nonvolatile cycles does not depend on st ate of OE.

2. HSB

STORE operation occurs only if an SRAM WRITE has been done since the last nonvola tile cycle. Afte r the STORE (if any) comp letes, the par t goes into standby

mode, inhibiting all operations until HSB

rises.

3. CE

and OE LOW and WE HIGH for output behavior.

4. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

5. While there are 15 addresses on the STK14C88-5, only the lower 14 are used to control software modes.

nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:

■ The nonvolatile cells in an nvSRAM are programmed on the

test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system

manufacturing test to ensure these system routines work
consistently.

■ Power up boot firmware routines should rewrite the nvSRAM

into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).

■ The V

and a maximum value size. Best practice is to meet this

value specified in this data sheet includes a minimum

CAP

requirement and not exceed the maximum V
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to use a larger
V

value to make sure there is extra store charge should

CAP

discuss their V
any impact on the V
period.

size selection with Cypress to understand

CAP

voltage level at the end of a t

CAP

Table 1. Hardware Mode Selection

CE WE HSB A13–A0 Mode IO Power

H X H X Not Selected Output High Z Standby

L H H X Read SRAM Output Data
L L H X Write SRAM Input Data Active

X X L X Nonvolatile STORE Output High Z

L H H 0x0E38

0x31C7
0x03E0
0x3C1F

0x303F

0x0FC0

L H H 0x0E38

0x31C7
0x03E0
0x3C1F

0x303F

0x0C63

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile STORE

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile RECALL

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

value because

CAP

Active

I

Active I

Active

[1]

[2]

CC2

[1, 3, 4, 5]

CC2

[1, 3, 4, 5]

RECALL

Document Number: 001-51038 Rev. ** Page 6 of 17

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STK14C88-5

Maximum Ratings

Notes

6. V

CC

reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V

CAP

if VCC is connected to ground.

7. CE

> VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Temperature under Bias.............................–55°C to +125°C

Voltage on Input Relative to GND.....................–0.5V to 7.0V

Voltage on Input Relative to Vss............–0.6V to V

CC

+ 0.5V

Voltage on DQ

or HSB .......................–0.5V to Vcc + 0.5V

0-7

Power Dissipation..........................................................1.0W

DC output Current (1 output at a time, 1s duration) ....15 mA

Operating Range

Range Ambient Temperature V

Military -55°C to +125°C 4.5V to 5.5V

CC

DC Electrical Characteristics

Over the operating range (VCC = 4.5V to 5.5V)

[6]

Parameter Description Test Conditions Min Max Unit

I

CC1

Average VCC Current tRC = 35 ns

t

= 45 ns

RC

Dependent on output loading and cycle rate. Values obtained

85
70

without output loads.
I

= 0 mA.

OUT

I

CC2

I

CC3

I

CC4

I

SB1

I

SB2

[7]

[7]

Average VCC Current
during STORE

Average VCC Current at
t

= 200 ns, 5V, 25°C

RC

Typical
Average V

during AutoStore Cycle

CAP

Current

VCC Standby Current
(Standby, Cycling TTL
Input Levels)

All Inputs Do Not Care, VCC = Max
Average current for duration t

> (VCC – 0.2V). All other inputs cycling.

WE
Dependent on output loading and cycle rate. Values obtained
without output loads.

All Inputs Do Not Care, VCC = Max
Average current for duration t

tRC = 35 ns, CE > V
tRC = 45 ns, CE > V

IH
IH

VCC Standby Current CE > (VCC – 0.2V). All others V

Standby current level after nonvolatile cycle is complete.

STORE

STORE

< 0.2V or > (VCC – 0.2V).

IN

3mA

10 mA

2mA

26
23

1.5 mA

Inputs are static. f = 0 MHz.
I
I

V

V

V
V
V

V

IX
OZ

IH

IL

OH
OL
BL

CAP

Input Leakage Current VCC = Max, VSS < V
Off State Output Leakage

VCC = Max, VSS < V

Current

< V

IN

CC

< VCC, CE or OE > V

IN

or WE < V

IH

-1 +1 μA

IL

-5 +5 μA

Input HIGH Voltage 2.2 VCC +

0.5

Input LOW Voltage VSS –

0.8 V

0.5
Output HIGH Voltage I
Output LOW Voltage I
Logic ‘0’ Voltage on HSB

Output
Storage Capacitor Between V

= –4 mA 2.4 V

OUT

= 8 mA 0.4 V

OUT

I

= 3 mA 0.4 V

OUT

pin and Vss, 6V rated. 68 µF +20% nom. 54 260 uF

CAP

mA
mA

mA
mA

V

Data Retention and Endurance

Parameter Description Min Unit

DATA

R

NV

C

Document Number: 001-51038 Rev. ** Page 7 of 17

Data Retention 100 Years
Nonvolatile STORE Operations 1,000 K

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STK14C88-5

Capacitance

5.0V

Output

30 pF

R1 963

Ω

R2

512

Ω

5.0V

Output

5 pF

R1 963

Ω

R2

512

Ω

For Tri-state Specs

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <

5 ns

Input and Output Timing Reference Levels.................... 1.5V

Note

8. These parameters are guaranteed by design and are not tested.

In the following table, the capacitance parameters are listed.

[8]

Parameter Description Test Conditions Max Unit

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 0 to 3.0V

Output Capacitance 7pF

CC

5pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

[8]

Parameter Description Test Conditions 32-CDIP 32-LCC Unit

Θ

Θ

Thermal Resistance

JA

(Junction to Ambient)
Thermal Resistance

JC

(Junction to Case)

Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.

TBD TBD °C/W

TBD TBD °C/W

Figure 7. AC Test Loads

AC Test Conditions

Document Number: 001-51038 Rev. ** Page 8 of 17

[+] Feedback

STK14C88-5

AC Switching Characteristics

W

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Notes

9. WE

and HSB must be HIGH during SRAM Read cycles.

10.Device is continuously selected with CE

and OE both Low.

11.Measured ±200 mV from steady state output voltage.

SRAM Read Cycle

Parameter

Cypress

Parameter

t

ACE

[9]

t

RC

[10]

t

AA

t

DOE

[10]

t

OHA

[11]

t

LZCE

[11]

t

HZCE

[11]

t

LZOE

[11]

t

HZOE

[8]

t

PU

[8]

t

PD

t
t

t
t

t
t
t
t
t
t
t

Alt

ELQV
AVAV, tELEH

AVQV
GLQV

AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL

Chip Enable Access Time 35 45 ns
Read Cycle Time 35 45 ns

Address Access Time 35 45 ns
Output Enable to Data Valid 15 20 ns

Output Hold After Address Change 5 5 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 13 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 13 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 35 45 ns

Switching Waveforms

Figure 8. SRAM Read Cycle 1: Address Controlled

Description

35 ns 45 ns

Min Max Min Max

[9, 10]

Unit

Document Number: 001-51038 Rev. ** Page 9 of 17

Figure 9. SRAM Read Cycle 2: CE and OE Controlled

[9]

[+] Feedback

STK14C88-5

SRAM Write Cycle

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

12.If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

13.HSB

must be high during SRAM WRITE cycles.

14.

CE

or WE must be greater than VIH during address transitions.

Parameter

Cypress

Parameter

t

WC

t

PWE

t

SCE

t

SD

t

HD

t

AW

t

SA

t

HA

[11,12]

t

HZWE

[11]

t

LZWE

t
t
t
t
t
t
t
t
t

t

Alt

AVAV
WLWH, tWLEH
ELWH, tELEH
DVWH, tDVEH
WHDX, tEHDX
AVWH, tAVEH
AVWL, tAVEL
WHAX, tEHAX
WLQZ

WHQX

Switching Waveforms

35 ns 45 ns

Description

Min Max Min Max

Unit

Write Cycle Time 35 45 ns
Write Pulse Width 25 30 ns
Chip Enable To End of Write 25 30 ns
Data Setup to End of Write 12 15 ns
Data Hold After End of Write 0 0 ns
Address Setup to End of Write 25 30 ns
Address Setup to Start of Write 0 0 ns
Address Hold After End of Write 0 0 ns
Write Enable to Output Disable 13 15 ns

Output Active After End of Write 5 5 ns

Figure 10. SRAM Write Cycle 1: WE Controlled

[13, 14]

Document Number: 001-51038 Rev. ** Page 10 of 17

Figure 11. SRAM Write Cycle 2: CE Controlled

[13, 14]

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STK14C88-5

AutoStore or Power Up RECALL

WE

Notes

15.t

HRECALL

starts from the time VCC rises above V

SWITCH

.

16.CE

and OE low and WE high for output behavior.

17.HSB

is asserted low for 1us when V

CAP

drops through V

SWITCH

. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store

takes place.

Parameter Alt Description

t

HRECALL

t

STORE

t

DELAY

V

SWITCH

V

RESET

t

VCCRISE

[13]

t

VSBL

[15]

[16]

[16]

t

RESTORE

t

HLHZ

t

HLQZ , tBLQZ

Power up RECALL Duration 550 μs
STORE Cycle Duration 10 ms
Time Allowed to Complete SRAM Cycle 1 μs
Low Voltage Trigger Level 4.0 4.5 V

Low Voltage Reset Level 3.6 V
VCC Rise Time 150 μs
Low Voltage Trigger (V

Switching Waveforms

Figure 12. AutoStore/Power Up RECALL

STK14C88-5

Min Max

) to HSB low 300 ns

SWITCH

Unit

Document Number: 001-51038 Rev. ** Page 11 of 17

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STK14C88-5

Software Controlled ST ORE/RECALL Cycle

t

RC

t

RC

t

SA

t

SCE

t

HACE

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

CE

OE

DQ (DATA)

Notes

18.The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

19.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

[16]

t

RC

[18, 19]

t

SA

[18, 19]

t

CW

t

HACE

t

RECALL

[18, 19]

t

AVAV

t

AVEL

t

ELEH

t

ELAX

STORE/RECALL Initiation Cycle Time 35 45 ns
Address Setup Time 0 0 ns
Clock Pulse Width 25 30 ns
Address Hold Time 20 20 ns
RECALL Duration 20 20 μs

[19]

Switching Waveforms

Figure 13. CE Controlled Software STORE/RECALL Cycle

35 ns 45 ns

Min Max Min Max

[19]

Unit

Document Number: 001-51038 Rev. ** Page 12 of 17

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STK14C88-5

Hardware STORE Cycle

Note

20.t

DHSB

is only applicable after t

STORE

is complete.

Parameter Alt Description

t

DHSB

t

PHSB

t

HLBL

[16, 20]

t

RECOVER, tHHQX

t

HLHX

Hardware STORE High to Inhibit Off 700 ns
Hardware STORE Pulse Width 15 ns

Hardware STORE Low to STORE Busy 300 ns

Switching Waveforms

Figure 14. Hardware STORE Cycle

STK14C88-5

Min Max

Unit

Document Number: 001-51038 Rev. ** Page 13 of 17

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STK14C88-5

Ordering Information

Speed:
35 - 35 ns
45 - 45 ns

Package:
C = Ceramic 32-pin 300 mil DIP

Part Numbering Nomenclature
STK14C88 - 5 C 35 M

Temperature Range:

M - Military (-55 to 125°C)

K
L = Ceramic 32-pin LLC

= Ceramic 32-pin 300 mil DIP (Solder dip finish)

Retention / Endurance

5 = Military (10 years or 10

5

cycles)

Speed

(ns)

35 STK14C88-5C35M 001-51694 32-pin CDIP (300 mil) Military

45 STK14C88-5C45M 001-51694 32-pin CDIP (300 mil)

The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts

Ordering Code Package Diagram Package Type

STK14C88-5K35M 001-51694 32-pin CDIP (300 mil)
STK14C88-5L35M 51-80068 32-pin LCC (450 mil)

STK14C88-5K45M 001-51694 32-pin CDIP (300 mil)
STK14C88-5L45M 51-80068 32-pin LCC (450mil)

Operating

Range

Document Number: 001-51038 Rev. ** Page 14 of 17

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STK14C88-5

Package Diagram

001-51694 **

Figure 15. 32-Pin (300-Mil) Side Braze DIL (001-51694)

Document Number: 001-51038 Rev. ** Page 15 of 17

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STK14C88-5

Package Diagram (continued)

51-80068-**

Figure 16. 32-Pad (450-Mil) LCC (51-80068)

Document Number: 001-51038 Rev. ** Page 16 of 17

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STK14C88-5

Document History Page

Document Title: STK14C88-5 256 Kbit (32K x 8) AutoStore nvSRAM
Document Number: 001-51038

Rev ECN No.

Orig. of

Change

Submission

Date

Description of Change

** 2666844 GVCH/PYRS 03/02/09 New data sheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales

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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intend ed to be used for medical ,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjuncti on with a Cypress
integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Code except as specifi ed above is prohib ited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not
assume any liability arising out of the app licati on or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot auth orize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-51038 Rev. ** Revised March 02, 2009 Page 17 of 17

AutoStore and Quant umTrap are registered trad emarks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be th e trademarks of their re spective
holders.

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