Cypress STK12C68-5 User Manual

STK12C68-5 (SMD5962-94599)

64 Kbit (8K x 8) AutoStore nvSRAM

Features

Logic Block Diagram

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

0

- A

12

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Functional Description

■ 35 ns and 55 ns access times

■ Hands off automatic STORE on power down with external

68 µF capacitor

■ STORE to QuantumTrap™ nonvolatile elements is initiated

by software, hardware, or AutoStore™ on power down

■ RECALL to SRAM initiated by software or power up

■ Unlimited Read, Write, and Recall cycles

■ 1,000,000 STORE cycles to QuantumTrap

■ 100 year data retention to QuantumTrap

■ Single 5V+10% operation

■ Military temperature

■ 28-pin (300mil) CDIP and 28-pad LCC packages

The Cypress STK12C68-5 is a fast static RAM with a nonvol­atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the ST ORE and
RECALL operations are also available under software control.
A hardware STORE is initiated with the HSB

pin.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-51026 Rev. ** Revised March 02, 2009

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STK12C68-5 (SMD5962-94599)

Pinouts

Figure 1. Pin Diagram - 28-Pin DIP

Figure 2. Pin Diagram - 28-Pin LLC

Pin Definitions

Pin Name Alt IO Type Description

A0–A

12

DQ

-DQ

0

7

WE

CE

OE

V

V

SS
CC

W

E

G

HSB

V

CAP

Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, dat a on the IO

pins is written to the specific address location.

Input Chip Enable Input, Active LOW. When LOW , select s the chip. When HIGH, deselects the

chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

HIGH causes the IO pins to tri-state.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in

progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-51026 Rev. ** Page 2 of 18

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STK12C68-5 (SMD5962-94599)

Device Operation

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The STK12C68-5 nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68-5 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to one million STORE
operations.

SRAM Read

The STK12C68-5 performs a Read cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the Read is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (Read cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE

or HSB is brought LOW.

determines the 8,192 data bytes accessed. When

0–12

(Read cycle 1). If the Read is initiated

or OE, the outputs are valid at t

AA

or at t

ACE

access time without the need for

AA

, whichever

DOE

During normal operation, the device draws current from VCC to
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V

pin drops below V

CC

pin from VCC. A STORE

CAP

pin. This stored

CAP

, the part

SWITCH

capacitor.

CAP

Figure 3 shows the proper connection of the storage capacitor

) for automatic store operation. A charge storage capacitor

(V

CAP

between 68 µF and 220 µF (+
The voltage on the V
internal to the chip. A pull up is placed on WE

20%) rated at 6V must be provided.

pin is driven to 5V by a charge pump

CAP

to hold it inactive

during power up.

Figure 3. AutoStore Mode

SRAM Write

A Write cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the Write cycle and must remain stable until either CE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE
internal circuitry turns off the output buffers t
LOW.

HZWE

AutoStore Operation

The STK12C68-5 stores data to nvSRAM using one of three
storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68-5.

or WE

is left LOW ,

after WE goes

In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the

CC

and V

are connected to the

CAP

AutoStore function of the STK12C68-5 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE

cycle.

does not drop below 3.6V during the 10 ms

CC

To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull up resistor is shown connected to HSB

. The HSB

signal is monitored by the system to detect if an AutoStore cycle
is in progress.

Document Number: 001-51026 Rev. ** Page 3 of 18

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STK12C68-5 (SMD5962-94599)

Figure 4. AutoStore Inhibit Mode

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During any STORE operation, regardless of how it is initiated,
the STK12C68-5 continues to drive the HSB

pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the STK12C68-5 remains
disabled until the HSB

pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <
V

), an internal RECALL request is latched. When V

RESET

once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

If the STK12C68-5 is in a Write
RECALL, the SRAM

data is corrupted. To help avoid this

state at the end of power up

HRECALL

SWITCH

, a RECALL

to complete.

CC

situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK12C68-5 software
STORE cycle is initiated by executing sequential CE
Read cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile

If the power supply drops faster than 20 us/volt before Vcc
reaches V
between V
excess of current between V

, then a 2.2 ohm resistor must be connected

SWITCH

and the system supply to avoid momentary

CC

CC

and V

CAP

.

AutoStore Inhibit Mode

If an automatic STORE on power loss is not required, then V
is tied to ground and +5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK12C68-5 is operated in this configuration,
references to V
sheet. In this mode, STORE
software control or the HSB

are changed to V

CC

operations are triggered through

pin. T o enable or disable Autostore
using an IO port pin see Preventing Store on page 5. It is not
permissible to change between these three options “on the
fly”.

(Figure 4). This is

CAP

throughout this data

CAP

data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output
are disabled until the cycle is completed.

Because a sequence of Reads from specific addresses is
used for STORE initiation, it is important that no other Read or
Write accesses intervene in the sequence. If they intervene,
the sequence is aborted and no STORE or RECALL takes
place.

CC

To initiate the software STORE cycle, the following Read
sequence is performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

3. Read address 0x0AAA, Valid READ

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0F, Initiate STORE cycle

Hardware STORE (HSB) Operation

The STK12C68-5 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
to request a hardware STORE cycle. When the HSB
driven LOW, the STK12C68-5 conditionally initiates a STORE
operation after t
Write to the SRAM takes place since the last STORE or
RECALL cycle. The HSB
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress.

. An actual STORE cycle only begins if a

DELAY

pin also acts as an open drain driver

SRAM Read and Write operations, that are in progress when
HSB

is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB
the STK12C68-5 continues SRAM operations for t
During t
a Write is in progress when HSB
time, t
requested after HSB

, multiple SRAM Read operations take place. If

DELAY

to complete. However, any SRAM Write cycles

DELAY

goes LOW are inhibited until HSB returns

is pulled LOW, it allows a

HIGH.

pin is used

pin is

goes LOW,

DELAY

The software sequence is clocked with CE
or OE

controlled Reads. When the sixth address in the
sequence is entered, the STORE cycle commences and the
chip is disabled. It is important that Read cycles and not Write
cycles are used in the sequence. It is not necessary that OE
is LOW for a valid sequence. After the t
fulfilled, the SRAM is again activated for Read and Write

STORE

operation.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner
similar to the software STORE initiation. To initiate the

.

RECALL cycle, the following sequence of CE
operations is performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

3. Read address 0x0AAA, Valid READ

controlled

controlled Reads

cycle time is

controlled Read

Document Number: 001-51026 Rev. ** Page 4 of 18

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STK12C68-5 (SMD5962-94599)

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0E, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for Read and Write operations. The RECALL operation

cycle time, the SRAM is again

RECALL

does not alter the data in the nonvolatile elements. The nonvol­atile data can be recalled an unlimited number of times.

Data Protection

The STK12C68-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and Write operations. The low voltage condition is detected
when V
mode (both CE

is less than V

CC

and WE are low) at power up after a RECALL or

. If the STK12C68-5 is in a Write

SWITCH

after a STORE, the Write is inhibited until a negative transition
on CE or WE is detected. This protects against inadve rtent writes
during power up or brown out conditions.

Noise Considerations

The STK12C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.

using leads and traces that are as short

SS,

Figure 5. Current Versus Cycle Time (Read)

Figure 6. Current Versus Cycle Time (Write)

Hardware Protect

The STK12C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi ­tions. When V
operations and SRAM Writes are inhibited. AutoStore can be

CAP<VSWITCH

, all externally initiated STORE

completely disabled by tying VCC to ground and applying +5V to
V

. This is the AutoStore Inhibit mode; in this mode, STOREs

CAP

are only initiated by explicit request using either the software
sequence or the HSB pin.

Low Average Active Power

CMOS technology provides the STK12C68-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 5 and Figure 6 shows the relationship
between I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK12C68-5
depends on the following items:

■ The duty cycle of chip enable

■ The overall cycle rate for accesses

■ The ratio of Reads to Writes

■ CMOS versus TTL input levels

■ The operating temperature

■ The V

and Read or Write cycle time. Worst case current

CC

level

CC

Preventing Store

The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it must overpower the internal pull down device. Thi s
device drives HSB

LOW for 20 μs at the onset of a STORE.
When the STK12C68-5 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on V
and V
attempts to pull HSB
V
attempt.

crosses V

CC

, the part stops trying to pull HSB LOW and abort the STORE

IL

on the way down, the STK12C68-5

SWITCH

LOW. If HSB does not actually get below

of at least 2.2V,

OH

CAP

)

Document Number: 001-51026 Rev. ** Page 5 of 18

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STK12C68-5 (SMD5962-94599)

Best Practices

Notes

1. HSB

STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby

mode, inhibiting all operations until HSB

rises.

2. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

3. IO state assumes OE

< VIL. Activation of nonvolatile cycles does not depend on state of OE .

nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, experience gained working with hundreds of applica­tions has resulted in the following suggestions as best
practices:

■ The nonvolatile cells in an nvSRAM are programmed on the

test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF , A5, or 5A.
The end product’s firmware must not assume that an NV

■ Power up boot firmware routines must rewrite the nvSRAM

into the desired state. While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the nvSRAM
into the desired state as a safeguard against events that
might flip the bit inadvertently (program bugs, incoming
inspection routines, and so on).

■ The Vcap value specified in this data sheet includes a

minimum and a maximum value size. The best practice is to
meet this requirement and not exceed the maximum Vcap
value because the higher inrush currents may reduce the
reliability of the internal pass transistor. Customers who want
to use a larger Vcap value to make sure there is extra store

charge must discuss their Vcap size selection with Cypress.
array is in a set programmed state. Routines that check
memory content values to determine first time system config­uration, cold or warm boot status, and so on must always

program a unique NV pattern (for example, complex 4-byte
pattern of 46 E6 49 53 hex or more random bytes) as part of
the final system manufacturing test to ensure these system
routines work consistently.

Table 1. Hardware Mode Selection

CE WE HSB A12–A0 Mode IO Power

H X H X Not Selected Output High Z Standby

L H H X Read SRAM Output Data Active
L L H X Write SRAM Input Data Active

X X L X Nonvolatile STORE Output High Z I

L H H 0x0000

0x1555

0x0AAA

0x1FFF
0x10F0
0x0F0F

L H H 0x0000

0x1555

0x0AAA

0x1FFF
0x10F0
0x0F0E

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile STORE

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile RECALL

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

Output Data
Output Data
Output Data
Output Data
Output Data

Output High Z

CC2

Active I

Active

[1]

CC2

[2, 3]

[3]

[2, 3]

Document Number: 001-51026 Rev. ** Page 6 of 18

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