Cypress STK12C68 User Manual

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STK12C68

64 Kbit (8K x 8) AutoStore nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

Logic Block Diagram

■

25 ns, 35 ns, and 45 ns access times

■

Hands off automatic STORE on power down with external 68 µF capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited Read, Write, and Recall cycles

■

1,000,000 STORE cycles to QuantumTrap

■

100 year data retention to QuantumTrap

■

Single 5V+10% operation

■

Commercial and industrial temperatures

■

228-pin (330mil) SOIC, 28-pin (300mil) PDIP, 28-pin (600mil) PDIP packages

■

28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages

■

RoHS compliance

Functional Description

The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent n onvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB

pin.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600 Document Number: 001-51027 Rev. ** Revised January 30, 2009

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STK12C68

Pin Configurations

Figure 1. 28-Pin SOIC/DIP a nd LLC

Pin Definitions

Pin Name Alt IO Type Description

0–A12

-DQ

CE E OE

HSB

CAP

Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location. Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW . The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-51027 Rev. ** Page 2 of 20

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STK12C68

Device Operation

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The STK12C68 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations.

SRAM Read

The STK12C68 performs a Read cycle whenever CE and OE are LOW while WE pins A

0–12

Read is initiated by an address transition, the outputs are valid after a delay of t or OE, the outputs are valid at t (Read cycle 2). The data outputs repeatedly respond to address changes within the t tions on any control input pins, and remains valid until a nother address change or until CE or OE is brought HIGH, or WE or HSB

is brought LOW.

and HSB are HIGH. The address specified on

determines the 8,192 data bytes accessed. When the

(Read cycle 1). If the Read is initiated by CE

access time without the need for transi-

ACE

or at t

, whichever is later

DOE

During normal operation, the device draws current from VCC to charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation. If the voltage on the V automatically disconnects the V operation is initiated with power provided by the V

pin drops below V

pin from VCC. A STORE

CAP

pin. This stored

CAP

, the part

SWITCH

capacitor.

CAP

Figure 2 shows the proper connection of the storage capacitor

) for automatic store operation. A charge storage capacitor

CAP

between 68 µF and 220 µF (+ provided. The voltage on the V pump internal to the chip. A pull up is placed on WE

20%) rated at 6V should be

pin is driven to 5V by a charge

CAP

to hold it

inactive during power up.

Figure 2. AutoStore Mode

SRAM Write

A Write cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB the Write cycle and must remain stable until either CE goes HIGH at the end of the cycle. The data on the common IO pins DQ the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines. If OE internal circuitry turns off the ou tput buff ers t LOW.

HZWE

AutoStore Operation

The STK12C68 stores data to nvSRAM using one of three storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68.

or WE

is left LOW,

after WE goes

In system power mode, both V +5V power supply without the 68 μF capacitor. In this mode, the

and V

are connected to the

CAP

AutoStore function of the STK12C68 operates on the stored system charge as power goes down. The user must, however, guarantee that V STORE

cycle.

does not drop below 3.6V during the 10 ms

To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations are ignored, unless at least one Write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a Write operation has taken place. An optional pull up resistor is shown connected to HSB

. The HSB

signal is monitored by the system to detect if an AutoStore cycle is in progress.

Document Number: 001-51027 Rev. ** Page 3 of 20

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STK12C68

Figure 3. AutoStore Inhibit Mode

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During any STORE operation, regardless of how it is initiated, the STK12C68 continues to drive the HSB

pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68 remains disabled until the HSB

returns HIGH.

is not used, it is left unconnected.

If HSB

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC < V once again exceeds the sense voltage of V cycle is automatically initiated and takes t

If the STK12C68 is in a Write RECALL, the SRAM

), an internal RECALL request is latched. When V

RESET

SWITCH

HRECALL

state at the end of power up

data is corrupted. To help avoid this

, a RECALL

to complete.

situation, a 10 Kohm resistor is connected either be tween WE and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK12C68 software STORE cycle is initiated by executing sequential CE cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is

If the power supply drops faster than 20 us/volt before Vcc reaches V between V of current between V

, then a 2.2 ohm resistor should be connected

SWITCH

and the system supply to avoid momentary excess

and V

CAP

AutoStore Inhibit Mode

If an automatic STORE on power loss is not required, then V is tied to ground and +5V is applied to V the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK12C68 is operated in this configuration, references to V In this mode, STORE control or the HSB

are changed to V

operations are triggered through software

pin. To enable or disable Autostore using an

throughout this data sheet.

CAP

I/O port pin see Preventing Store on page 5. It is not permissible to change between these three options “on the fly”.

(Figure3). This is

CAP

first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed.

Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following Read sequence is performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

3. Read address 0x0AAA, Valid READ

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0F, Initiate STORE cycle

Hardware STORE (HSB) Operation

The STK12C68 provides the HSB pin for controlling and request a hardware STORE cycle. When the HSB

LOW, the STK12C68 conditionally initiates a STORE operation after t SRAM takes place since the last STORE or RECALL cycle. The HSB LOW to indicate a busy condition, while the STORE (initiated by

. An actual STORE cycle only begins if a Write to the

DELAY

pin also acts as an open drain driver that is internally driven

acknowledging the STORE operations. The HSB

any means) is in progress. SRAM Read and Write operations, that are in progress when

is driven LOW by any means, are given time to complete

HSB before the STORE operation is initiated. After HSB the STK12C68 continues SRAM operations for t

, multiple SRAM Read operations take place. If a Write is

DELAY

in progress when HSB

is pulled LOW, it allows a time, t

complete. However, any SRAM Write cycles requested after

goes LOW are inhibited until HSB returns HIGH.

HSB

pin is used to

pin is driven

goes LOW,

DELAY

. During

DELAY

The software sequence is clocked with CE

controlled Reads. When the sixth address in the sequence

OE is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE a valid sequence. After the t SRAM is again activated for Read and Write operation.

cycle time is fulfilled, the

STORE

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE performed:

1. Read address 0x0000, Valid READ

2. Read address 0x1555, Valid READ

controlled Read operations is

controlled Read

controlled Reads or

is LOW for

Document Number: 001-51027 Rev. ** Page 4 of 20

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STK12C68

3. Read address 0x0AAA, Valid READ

4. Re ad address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0E, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the t ready for Read and Write operations. The RECALL operation

cycle time, the SRAM is again

RECALL

does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.

Data Protection

The STK12C68 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when VCC is less than V and WE are low) at power up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE

. If the STK12C68 is in a Write mode (both CE

SWITCH

or WE is detected. This protects against inadvertent writes during power up or brown out conditions.

Noise Considerations

The STK12C68 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between V as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.

and V

using leads and traces that are as short

SS,

■

The VCC level

■

IO loading

Figure 4. Current Versus Cycle Time (Read)

Figure 5. Current Versus Cycle Time (Write)

Hardware Protect

The STK12C68 offers hardware protection again st inadvertent STORE operation and SRAM Writes during low voltage condi tions. When V operations and SRAM Writes are inhibited. AutoStore can be

CAP<VSWITCH

, all externally initiated STORE

completely disabled by tying VCC to ground and applying +5V to V

. This is the AutoStore Inhibit mode; in this mode, STOREs

CAP

are only initiated by explicit request using either the software sequence or the HSB

pin.

Low Average Active Power

CMOS technology provides the STK12C68 the benefit of drawing significantly less c urrent when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between I Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK12C68 depends on the following items:

■

The duty cycle of chip enable

■

The overall cycle rate for accesses

■

The ratio of Reads to Writes

■

CMOS versus TTL input levels

■

The operating temperature

and

Preventing Store

The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a V because it must overpower the internal pull down device. Thi s device drives HSB

LOW for 20 μs at the onset of a STORE. When the STK12C68 is connected for AutoStore operation (system V and V attempts to pull HSB V

, the part stops trying to pull HSB LOW and abort the STORE

attempt.

connected to VCC and a 68 μF capacitor on V

crosses V

on the way down, the STK12C68

SWITCH

LOW. If HSB does not actually get below

of at least 2.2V,

CAP

)

Document Number: 001-51027 Rev. ** Page 5 of 20

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STK12C68

Best Practices

Notes

1. HSB

STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the p art goes into standby

mode, inhibiting all operations until HSB

rises.

2. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

3. I/O state assumes OE

< VIL. Activation of nonvolatile cycles does not depend on state of OE.

nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

■

The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46

manufacturing test to ensure these system routines work consistently.

■

Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on).

■

The Vcap value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Cypress.

E6 49 53 hex or more random bytes) as part of the final system

Table 1. Hardware Mode Selection

CE WE HSB A12–A0 Mode IO Power

H X H X Not Selected Output High Z Standby

L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active

X X L X Nonvolatile STORE Output High Z I

L H H 0x0000

0x1555

0x0AAA

0x1FFF 0x10F0 0x0F0F

L H H 0x0000

0x1555

0x0AAA

0x1FFF 0x10F0 0x0F0E

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile STORE

Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM

Nonvolatile RECALL

Output Data Output Data Output Data Output Data Output Data

Output High Z

Output Data Output Data Output Data Output Data Output Data

Output High Z

CC2

Active I

Active

[1]

CC2

[2, 3]

[3]

[2, 3]

Document Number: 001-51027 Rev. ** Page 6 of 20

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STK12C68

Maximum Ratings

Notes

4. V

reference levels throughout this data sheet refe r to VCC if that is where the power supply connection is made, or V

CAP

if VCC is connected to ground.

5. CE

> VIH does not produce standby current levels until any nonvolat ile cycle in progress has timed out.

Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Temperature under Bias............................. –55°C to +125°C

Voltage on Input Relative to GND.....................–0.5V to 7.0V

Voltage on Input Relative to Vss............–0.6V to V

DC Electrical Characteristics

Over the operating range (VCC = 4.5V to 5.5V)

+ 0.5V

[4]

Voltage on DQ

Power Dissipation..........................................................1.0W

DC output Current (1 output at a time, 1s duration) .... 15 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 4.5V to 5.5V Industrial -40°C to +85°C 4.5V to 5.5V

or HSB .......................–0.5V to Vcc + 0.5V

0-7

Parameter Description Test Conditions Min Max Unit

CC1

Average VCC Current tRC = 25 ns

= 35 ns

= 45 ns

Dependent on output loading and cycle rate. Values obtained

85 75 65

mA mA mA

without output loads. I

= 0 mA.

OUT

CC2

CC3

CC4

SB1

SB2

V V V V

IL OH OL BL

CAP

Average VCC Current during STORE

Average VCC Current at t

= 200 ns, 5V, 25°C

Typical Average V

during AutoStore Cycle

[5]

VCC Standby Current (Standby, Cycling TTL

CAP

Current

Input Levels)

[5]

VCC Standby Current CE > (VCC – 0.2V). All others V

Input Leakage Current VCC = Max, VSS < V Input Leakage Current VCC = Max, VSS < V Off State Output

Leakage Current Input HIGH Voltage 2.2 VCC +

Input LOW Voltage VSS – 0.5 0.8 V Output HIGH Voltage I Output LOW Voltage I Logic ‘0’ Voltage on

Output

HSB Storage Capacitor Between Vcap pin and Vss, 6V rated. 68 µF +20% nom. 54 260 µF

All Inputs Do Not Care, VCC = Max Average current for duration t

> (VCC – 0.2V). All other inputs cycling.

STORE

Dependent on output loading and cycle rate. Values obtained without output loads.

All Inputs Do Not Care, VCC = Max Average current for duration t

tRC = 25 ns, CE > V tRC = 35 ns, CE > V tRC = 45 ns, CE > V

– 0.2V). Standby current level after

nonvolatile cycle is complete.

IH IH IH

Inputs are static. f = 0 MHz.

IN IN

VCC = Max, VSS < V

= –4 mA 2.4 V

OUT

= 8 mA 0.4 V

OUT

= 3 mA 0.4 V

OUT

STORE

< 0.2V or >

< V

< VCC, CE or OE > V

Commercial 1.5 mA

Industrial 2.5 mA

-1 +1 μA

or WE < V

-5 +5 μA

3mA

10 mA

2mA

27 24 20

mA mA mA

0.5

Document Number: 001-51027 Rev. ** Page 7 of 20

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STK12C68

Data Retention and Endurance

5.0V

Output

30 pF

R1 963Ω

512Ω

5.0V

Output

5 pF

R1 963

512

For Tri-state Specs

Input Pulse Levels..................................................0 V to 3 V

Input Rise and Fall Times (10% to 90%)...................... <

5 ns

Input and Output Timing Reference Levels.......................1.5

Note

6. These parameters are guaranteed by design and are not tested.

Parameter Description Min Unit

DATA NV

Data Retention 100 Years Nonvolatile STORE Operations 1,000 K

Capacitance

In the following table, the capacitance parameters are listed.

Parameter Description Test Conditions Max Unit

C C

IN OUT

Input Capacitance TA = 25°C, f = 1 MHz,

= 0 to 3.0 V

Output Capacitance 7pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter Description Test Conditions 28-SOIC

Thermal Resis-

tance (Junction to Ambient)

Thermal Resis-

tance (Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51.

Figure 6. AC Test Loads

[6]

8pF

[6]

28-PDIP

(300 mil)

46.55 45.16 55.84 46.1 95.31 °C/W

27.95 31.62 25.74 5.01 9.01 °C/W

28-PDIP

(600 mil)

28-CDIP 28-LCC Unit

AC Test Conditions

Document Number: 001-51027 Rev. ** Page 8 of 20

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STK12C68

AC Switching Characteristics

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Notes

7. WE

and HSB must be High during SRAM Read cycles.

8. Device is continuously selected with CE

and OE both Low.

9. Measured ±200 mV from steady state output voltage.

SRAM Read Cycle

Parameter

Cypress

Parameter

ACE

[7]

[8]

DOE

[8]

OHA

[9]

LZCE

[9]

HZCE

[9]

LZOE

[9]

HZOE

[6]

Alt

ELQV

AVAV, tELEH

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

Chip Enable Access Time 25 35 45 ns Read Cycle Time 25 35 45 ns Address Access Time 25 35 45 ns Output Enable to Data Valid 10 15 20 ns Output Hold After Address Change 5 5 5 ns Chip Enable to Output Active 5 5 5 ns Chip Disable to Output Inactive 10 10 12 ns Output Enable to Output Active 0 0 0 ns Output Disable to Output Inactive 10 10 12 ns Chip Enable to Power Active 0 0 0 ns Chip Disable to Power Standby 25 35 45 ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled

Description

25 ns 35 ns 45 ns

Min Max Min Max Min Max

[7, 8]

Unit

Document Number: 001-51027 Rev. ** Page 9 of 20

Figure 8. SRAM Read Cycle 2: CE and OE Controlled

[7]

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STK12C68

SRAM Write Cycle

SCE

PWE

HZWE

LZWE

ADDRESS

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

SCE

PWE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

10.If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

11. HSB

must be high during SRAM Write cycles.

12.

or WE must be greater than VIH during address transitions.

Parameter

Cypress

Parameter

PWE

SCE

[9,10]

HZWE

[9]

LZWE

AVAV

WLWH, tWLEH

ELWH, tELEH

DVWH, tDVEH

WHDX, tEHDX

AVWH, tAVEH

AVWL, tAVEL

WHAX, tEHAX

WLQZ

WHQX

Alt

Switching Waveforms

25 ns 35 ns 45 ns

Description

Min Max Min Max Min Max

Unit

Write Cycle Time 25 35 45 ns Write Pulse Width 20 25 30 ns Chip Enable To End of Write 20 25 30 ns Data Setup to End of Write 10 12 15 ns Data Hold After End of Write 0 0 0 ns Address Setup to End of Write 20 25 30 ns Address Setup to Start of Write 0 0 0 ns Address Hold After End of Write 0 0 0 ns Write Enable to Output Disable 10 13 14 ns Output Active After End of Write 5 5 5 ns

Figure 9. SRAM Write Cycle 1: WE Controlled

[11, 12]

Document Number: 001-51027 Rev. ** Page 10 of 20

Figure 10. SRAM Write Cycle 2: CE Controlled

[11, 12]

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STK12C68

AutoStore or Power Up RECALL

Notes

13.t

HRECALL

starts from the time VCC rises above V

SWITCH

14.CE

and OE low for output behavior.

15.CE

and OE low and WE high for output behavior.

16.HSB

is asserted low for 1us when V

CAP

drops through V

SWITCH

. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store

takes place.

Parameter Alt Description

HRECALL

STORE

DELAY

SWITCH

RESET

VCCRISE

VSBL

[13]

[14, 15, 16]

[9, 15]

[11]

RESTORE

HLHZ

HLQZ , tBLQZ

Power up RECALL Duration 550 STORE Cycle Duration 10 ms Time Allowed to Complete SRAM Cycle 1 Low Voltage Trigger Level 4.0 4.5 V Low Voltage Reset Level 3.9 V VCC Rise Time 150 Low Voltage Trigger (V

Switching Waveform

Figure 11. AutoStore/Power Up RECALL

STK12C68

Min Max

) to HSB Low 300 ns

SWITCH

Unit

Document Number: 001-51027 Rev. ** Page 11 of 20

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STK12C68

Software Controlled STORE/RECALL Cycle

SCE

HACE

STORE

/ t

RECALL

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

DQ (DATA)

Notes

17.The software sequence is clocked on the falling edge of CE

without involving OE (double clocking aborts the sequence).

18.The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

[14]

[17]

HACE

RECALL

[17]

AVAV

AVEL

ELEH

ELAX

STORE/RECALL Initiation Cycle Time 25 35 45 ns Address Setup Time 0 0 0 ns Clock Pulse Width 20 25 30 ns Address Hold Time 20 20 20 ns RECALL Duration 20 20 20

[18]

25 ns 35 ns 45 ns

Min Max Min Max Min Max

Unit

Switching Waveform

Figure 12. CE Controlled Software STORE/RECALL Cycle

[18]

Document Number: 001-51027 Rev. ** Page 12 of 20

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STK12C68

Hardware STORE Cycle

Note

19.t

DHSB

is only applicable after t

STORE

is complete.

Parameter Alt Description

[9, 14]

STORE

DHSB

PHSB

HLBL

[14, 19]

HLHZ

RECOVER, tHHQX

HLHX

STORE Cycle Duration 10 ms Hardware STORE High to Inhibit Off 700 ns Hardware STORE Pulse Width 15 ns Hardware STORE Low to STORE Busy 300 ns

Switching Waveform

Figure 13. Hardware STORE Cycle

STK12C68

Min Max

Unit

Document Number: 001-51027 Rev. ** Page 13 of 20

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STK12C68

Part Numbering nomenclature

Packaging Option: TR = Tape and Reel Blank = Tube

Speed: 25 - 25 ns 35 - 35 ns

Package: S = Plastic 28-pin 330 mil SOIC

STK12C68 - S F 45 I TR

Temperature Range: C - Commercial (0 to 70° C)

P W = Plastic 28-pin 600 mil DIP C = Ceramic 28-pin 300 mil DIP

L = Ceramic 28-pin LLC

= Plastic 28-pin 300 mil DIP

Lead Finish F = 100% Sn (Matte Tin)

45 - 45 ns

I - Industrial (-40 to 85°C)

Ordering Information

Speed (n s) Ordering Code Package Diagram Package Type Operating Range

25 STK12C68-SF25TR 001-85058 28-pin SOIC (330 mil) Commercial

STK12C68-SF25 001-85058 28-pin SOIC (330 mil) STK12C68-PF25 001-85014 28-pi n PDIP (300 mil) STK12C68-WF25 001-85017 28-pin PDIP (600 mil) STK12C68-SF25ITR 001-85058 28-pin SOIC (330 mil) Industrial

35 STK12C68-C35 001-51695 28-pin CDIP (300 mil) Commercial

Document Number: 001-51027 Rev. ** Page 14 of 20

STK12C68-SF25I 001-85058 28-pin SOIC (330 mil) STK12C68-PF25I 001-85014 28-pin PDIP (300 mil) STK12C68-WF25I 001-85017 28-pin PDIP (600 mil)

STK12C68-L35 001-51696 28-pi n LCC (350 mil) STK12C68-C35I 001-51695 28-pin CDIP (300 mil) Industrial STK12C68-L35I 001-51696 28-pin LCC (350 mil)

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STK12C68

Ordering Information

Speed (n s) Ordering Code Package Diagram Package Type Operating Range

45 STK12C68-SF45TR 001-85058 28-pin SOIC (330 mil) Commercial

STK12C68-SF45 001-85058 28-pin SOIC (330 mil) STK12C68-PF45 001-85014 28-pi n PDIP (300 mil) STK12C68-WF45 001-85017 28-pin PDIP (600 mil) STK12C68-C45 001-51695 28-pin CDIP (300 mil) STK12C68-L45 001-51696 28-pi n LCC (350 mil) STK12C68-SF45ITR 001-85058 28-pin SOIC (330 mil) Industrial STK12C68-SF45I 001-85058 28-pin SOIC (330 mil) STK12C68-PF45I 001-85014 28-pin PDIP (300 mil) STK12C68-WF45I 001-85017 28-pin PDIP (600 mil) STK12C68-C45I 001-51695 28-pin CDIP (300 mil) STK12C68-L45I 001-51696 28-pin LCC (350 mil)

All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts

(continued)

Document Number: 001-51027 Rev. ** Page 15 of 20

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STK12C68

Package Diagrams

51-85058 *A

51-85014 *D

Figure 14. 28-Pin (330 Mil) SOIC (51-85058)

Figure 15. 28-Pin (300 Mil) PDIP (51-85014)

Document Number: 001-51027 Rev. ** Page 16 of 20

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STK12C68

Package Diagrams

51-85017 *B

(continued)

Figure 16. 28-Pin (600 Mil) PDIP (51-85017)

Document Number: 001-51027 Rev. ** Page 17 of 20

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STK12C68

Package Diagrams

001-51695 **

(continued)

Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695)

Document Number: 001-51027 Rev. ** Page 18 of 20

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STK12C68

Package Diagrams

1. ALL D IMEN SION A RE IN INCH ES AN D MILLIM ETER S [MIN/M AX]

2. JEDEC 95 OUTLINE# MO-041

3. PACKAGE WEIGHT : TBD

001-51696 **

(continued)

Figure 18. 28-Pad (350 Mil) LCC (001-51696)

Document Number: 001-51027 Rev. ** Page 19 of 20

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STK12C68

Document History Page

Document Title: STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM Document Number: 001-51027

Rev. ECN No.

Orig. of

Change

Submission

Date

Description of Change

** 2606744 GVCH 01/30/2009 New data sheet

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© Cypress Semiconductor Corporation, 2006- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted no r inte nd ed to be used fo r medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written ag re em en t wi t h C ypr ess. Fu rth er mor e, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spe cified above is prohibited wi thout the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-51027 Rev. ** Revised January 30, 2009 Page 20 of 20

AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective holders.

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Cypress STK12C68 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Pin Configurations

Pin Definitions

Device Operation

SRAM Read

SRAM Write

AutoStore Operation

Hardware RECALL (Power Up)

Software STORE

AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

Software RECALL

Data Protection

Noise Considerations

Hardware Protect

Low Average Active Power

Preventing Store

Best Practices

Maximum Ratings

DC Electrical Characteristics

Operating Range

Data Retention and Endurance

Capacitance

Thermal Resistance

AC Test Conditions

SRAM Read Cycle

SRAM Write Cycle

AutoStore or Power Up RECALL

Software Controlled STORE/RECALL Cycle

Switching Waveform

Part Numbering nomenclature

Ordering Information

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Products

PSoC Solutions