S29GL01GP
S29GL512P
S29GL256P
S29GL128P
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash
with 90 nm MirrorBit Process Technology
General Description
The Cypress S29GL01G/512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These devices
offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that
allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than
standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density,
better performance and lower power consumption.
Distinctive Characteristics
Single 3V read/program/erase (2.7-3.6 V)
Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and
outputs are determined by voltage on V
to V
90 nm MirrorBit process technology
8-word/16-byte page read buffer
32-word/64-byte write buffer reduces overall programming time for
Secured Silicon Sector region
Uniform 64 Kword/128 Kbyte Sector Architecture
100,000 erase cycles per sector typical
CC
multiple-word updates
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the
customer
– S29GL01GP: One thousand twenty-four sectors
– S29GL512P: Five hundred twelve sectors
– S29GL256P: Two hundred fifty-six sectors
– S29GL128P: One hundred twenty-eight sectors
input. VIO range is 1.65
IO
20-year data retention typical
Offered Packages
– 56-pin TSOP
– 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase
operations
Write operation status bits indicate program and erase operation
completion
Unlock Bypass Program command to reduce programming time
Support for CFI (Common Flash Interface)
Persistent and Password methods of Advanced Sector Protection
WP#/ACC input
– Accelerates programming time (when V
throughput during system production
– Protects first or last sector regardless of sector protection
settings
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
is applied) for greater
HH
Performance Characteristics
Maximum Read Access Times (ns)
Density Voltage Range (1)
Regulated V
128 & 256 Mb
VersatileIO V
Regulated V
512 Mb
VersatileIO V
Regulated V
1 Gb
VersatileIO V
Notes
1. Access times are dependent on V
See Ordering Information page for further details.
Regulated V
Full V
CC
VersatileIO V
2. Contact a sales representative for availability.
: VCC = 3.0–3.6 V.
CC
: V
= VIO = 2.7–3.6 V.
CC
: VIO = 1.65–VCC, VCC = 2.7–3.6 V.
IO
CC
CC
IO
CC
CC
IO
CC
CC
IO
and VIO operating ranges.
CC
Random Access
Time (t
100/110 100/110
)
ACC
90
110 110
100
110 110
120 120
110
120 120
130 130
Page Access Time
(t
)
PACC
25
25
25
CE# Access Time
(tCE)
90
100
110
OE# Access Time
(tOE)
25Full V
25Full V
25Full V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-00886 Rev. *B Revised May 22, 2017
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
Current Consumption (typical values)
Random Access Read (f = 5 MHz) 30 mA
8-Word Page Read (f = 10 MHz) 1 mA
Program/Erase 50 mA
Standby 1 µA
Program & Erase Times (typical values)
Single Word Programming 60 µs
Effective Write Buffer Programming (V
Effective Write Buffer Programming (V
Sector Erase Time (64 Kword Sector) 0.5 s
) Per Word 15 µs
CC
) Per Word 13.5 µs
HH
Document Number: 002-00886 Rev. *B Page 2 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
Contents
1. Ordering Information................................................... 4
2. Input/Output Descriptions & Logic Symbol .............. 6
3. Block Diagram.............................................................. 7
4. Physical Dimensions/Connection Diagrams............. 8
4.1 Related Documents ....................................................... 8
4.2 Special Handling Instructions for BGA Package............ 8
4.3 LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm . 9
4.4 TS056—56-Pin Standard Thin Small Outline Package
(TSOP)......................................................................... 11
5. Additional Resources................................................ 12
5.1 Application Notes ......................................................... 12
5.2 Specification Bulletins .................................................. 12
5.3 Hardware and Software Support.................................. 12
5.4 Contacting Cypress...................................................... 12
6. Product Overview ...................................................... 13
6.1 Memory Map ................................................................ 13
7. Device Operations ..................................................... 15
7.1 Device Operation Table ............................................... 15
7.2 Word/Byte Configuration.............................................. 16
7.3 Versatile IO
7.4 Read ............................................................................ 16
7.5 Page Read Mode......................................................... 16
7.6 Autoselect .................................................................... 17
7.7 Program/Erase Operations .......................................... 21
7.8 Write Operation Status................................................. 32
7.9 Writing Commands/Command Sequences.................. 36
8. Advanced Sector Protection/Unprotection ............. 38
8.1 Lock Register ............................................................... 39
8.2 Persistent Protection Bits............................................. 39
8.3 Persistent Protection Bit Lock Bit................................. 41
8.4 Password Protection Method....................................... 41
8.5 Advanced Sector Protection Software Examples ........ 44
8.6 Hardware Data Protection Methods............................. 44
9. Power Conservation Modes...................................... 45
9.1 Standby Mode.............................................................. 45
9.2 Automatic Sleep Mode................................................. 45
9.3 Hardware RESET# Input Operation............................. 45
9.4 Output Disable (OE#)................................................... 45
10. Secured Silicon Sector Flash Memory Region ....... 46
10.1 Factory Locked Secured Silicon Sector....................... 46
10.2 Customer Lockable Secured Silicon Sector................. 47
10.3 Secured Silicon Sector Entry/Exit Command
Sequences ................................................................... 47
11. Electrical Specifications............................................ 49
11.1 Absolute Maximum Ratings ......................................... 49
11.2 Operating Ranges........................................................ 50
11.3 Test Conditions............................................................ 50
11.4 Key to Switching Waveforms ....................................... 51
11.5 Switching Waveforms .................................................. 51
11.6 DC Characteristics....................................................... 52
Document Number: 002-00886 Rev. *B Page 3 of 83
TM
(VIO) Control ......................................... 16
11.7 AC Characteristics........................................................ 53
12. Appendix ..................................................................... 64
12.1 Command Definitions.................................................... 64
12.2 Common Flash Memory Interface................................. 73
13. Advance Information on S29GL-S Eclipse 65 nm
MirrorBit Power-On and Warm Reset Timing........... 77
14. Document History....................................................... 79
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
1. Ordering Information
The ordering part number is formed by a valid combination of the following:
S29GL01GP 12 F F I 01 0
PACKING TYPE
0 = Tray (standard (Note 5))
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER (V
01 = V
02 = V
V1 = V
V2 = V
R1= V
R2= V
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
C = Commercial (0°C to +85°C)
PACKAGE MATERIALS SET
A= Pb (Note 1)
F= Pb-free
PACKAGE TYPE
T = 56-pin Thin Small Outline Package (TSOP) Standard Pinout(TSO56)
F = 64-ball Fortified Ball Grid Array, 1.0 mm pitch package (LAA064)
SPEED OPTION
90 = 90 ns
10 = 100 ns
11 = 110 ns
12 = 120 ns
13 = 130 ns
= VCC = 2.7 to 3.6 V, highest address sector protected
IO
= VCC = 2.7 to 3.6 V, lowest address sector protected
IO
= 1.65 to VCC, VCC = 2.7 to 3.6 V, highest address sector protected
IO
= 1.65 to VCC, VCC = 2.7 to 3.6 V, lowest address sector protected
IO
= VCC = 3.0 to 3.6 V, highest address sector protected
IO
= VCC = 3.0 to 3.6 V, lowest address sector protected
IO
range, protection when WP# =VIL)
IO
DEVICE NUMBER/DESCRIPTION
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
3.0 Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured on 90 nm MirrorBit
technology
®
process
Recommended Combinations
Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to
confirm availability of specific recommended combinations and to check on newly released combinations.
Document Number: 002-00886 Rev. *B Page 4 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
S29GL-P Valid Combinations
Base Part
Number
S29GL01GP
S29GL512P
S29GL128P,
S29GL256P
Notes
1. Contact a local sales representative for availability.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from ordering part number.
4. Operating Temperature range: I = Industrial (–40°C to +85°C)
5. Type 0 is standard. Specify other options as required.
Speed Package (2)(3) T emperature (4) Model Number
11
TA (1), TF
13 V1, V2
11
FA (1), FF
13 V1, V2
10
TA (1), TF
12 V1, V2
10
FA (1), FF
12 V1, V2
90
TA (1), TF
11 V1, V2
90
FA (1), FF
11 V1, V2
C = Commercial (0°C to +85°C)
I, C R1, R2
I
I, C R1, R2
I
I, C R1, R2
I
I, C R1, R2
I
I, C R1, R2
I
I, C R1, R2
I
01, 02
01, 02
01, 02
01, 02
01, 02
01, 02
Packing Type
(5)
0, 3 12
0, 2, 3 12
0, 3 11
0, 2, 3 11
0, 3 10, 11
0, 2, 3 10, 11
Document Number: 002-00886 Rev. *B Page 5 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
2. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Input/Output Descriptions
Symbol T ype Description
Address lines for GL01GP
A25–A0 Input
DQ14–DQ0 I/O Data input/output.
DQ15/A-1 I/O
CE# Input Chip Enable.
OE# Input Output Enable.
WE# Input Write Enable.
V
CC
V
IO
V
SS
NC No Connect Not connected internally.
RY/BY# Output
BYTE# Input
RESET# Input Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC Input
Supply Device Power Supply.
Supply Versatile IO Input.
Supply Ground.
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At V
is actively erasing or programming. At High Z, the device is in ready.
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-DQ7 are
active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and
data I/O pins DQ0-DQ15 are active.
Write Protect/Acceleration Input. At V
sectors. At V
Should be at V
V
.
IH
, accelerates programming; automatically places device in unlock bypass mode.
HH
for all other conditions. WP# has an internal pull-up; when unconnected, WP# is at
IH
, disables program and erase functions in the outermost
IL
, the device
IL
Document Number: 002-00886 Rev. *B Page 6 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
3. Block Diagram
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
V
CC
V
SS
V
IO
WE#
WP#/ACC
BYTE#
CE#
OE#
STB
STB
DQ15–DQ0
Sector Switches
RY/BY#
RESET#
Data
Y-Gating
Cell Matrix
Address Latch
A
Max
**–A0 (A-
** A
Max
GL01GP=A25, A
Max
GL512P = A24, A
Max
GL256P = A23, A
Max
GL128P = A22
Figure 3.1 S29GL-P Block Diagram
Document Number: 002-00886 Rev. *B Page 7 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
4. Physical Dimensions/Connection Diagrams
A2 C2 D2 E2 F2 G2 H2
A3 C3 D3 E3 F3 G3 H3
A4 C4 D4 E4 F4 G4 H4
A5 C5 D5 E5 F5 G5 H5
A6 C6 D6 E6 F6 G6 H6
A7 C7 D7 E7 F7 G7 H7
DQ15/A-1
V
SS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE#
V
SS
CE#A0A1A2A4A3
A1 C1 D1 E1 F1 G1 H1
NC NCV
IO
NCNCNCNCNC
A8 C8
B2
B3
B4
B5
B6
B7
B1
B8 D8 E8 F8 G8 H8
A25
NC
A24V
SS
V
IO
A23A22NC
NC on S29GL128P
NC on S29GL256P
NC on S29GL512P
Top View, Balls Facing Down
This section shows the I/O designations and package specifications for the S29GL-P family.
4.1 Related Documents
The following documents contain information relating to the S29GL-P devices. Click on the title or go to www.cypress.com download
the PDF file, or request a copy from your sales office.
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2 Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Figure 4.1 64-ball Fortified Ball Grid Array
Document Number: 002-00886 Rev. *B Page 8 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
4.3 LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm
3354 \ 16-038.12d
PACKAGE LAA 064
JEDEC N/A
13.00 mm x 11.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.40 PROFILE HEIGHT
A1 0.40 --- --- STANDOFF
A2 0.60 --- --- BODY THICKNESS
D 13.00 BSC. BODY SIZE
E 11.00 BSC. BODY SIZE
D1 7.00 BSC. MATRIX FOOTPRINT
E1 7.00 BSC. MATRIX FOOTPRINT
MD 8 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
N 64 BALL COUNT
φb 0.50 0.60 0.70 BALL DIAMETER
eD 1.00 BSC. BALL PITCH - D DIRECTION
eE 1.00 BSC. BALL PITCH - E DIRECTION
SD / SE 0.50 BSC. SOLDER BALL PLACEMENT
NONE DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
Figure 4.2 LAA064—64ball Fortified Ball Grid Array (FBGA), 11 x 13 mm
Document Number: 002-00886 Rev. *B Page 9 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
Figure 4.3 56-pin Standard TSOP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
A24
A25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
23
24
25
26
27
28
A4
A3
A2
A1
NC
NC
34
33
32
31
30
29
OE#
V
SS
CE#
A0
NC
V
IO
NC on S29GL512P
NC on S29GL256P
NC on S29GL128P
Document Number: 002-00886 Rev. *B Page 10 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
4.4 TS056—56-Pin Standard Thin Small Outline Package (TSOP)
NOTES:
1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
4 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
5 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
6 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
7 LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
8 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3160\38.10A
MO-142 (B) EC
TS 56
NOM.
---
---
1.00
1.20
0.15
1.05
MAX.
---
MIN.
0.95
0.20 0.230.17
0.22 0.270.17
--- 0.160.10
--- 0.210.10
20.00 20.2019.80
14.00 14.1013.90
0.60 0.700.50
-8˚0˚
--- 0.200.08
56
18.40 18.5018.30
0.05
0.50 BASIC
E
R
b1
JEDEC
PACKAGE
SYMBOL
A
A2
A1
D1
D
c1
c
b
e
L
N
O
Figure 4.4 56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm
Document Number: 002-00886 Rev. *B Page 11 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
5. Additional Resources
Visit www.cypress.com to obtain the following related documents:
5.1 Application Notes
The following is a list of application notes related to this product. All Cypress application notes are available at http://
www.cypress.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx
Using the Operation Status Bits in AMD Devices
Understanding Page Mode Flash Memory Devices
MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read
Common Flash Interface Version 1.4 Vendor Specific Extensions
MirrorBit
Taking Advantage of Page Mode Read on the MCF5407 Coldfire
Migration to S29GL128N and S29GL256N based on 110nm MirrorBit
Optimizing Program/Erase Times
Practical Guide to Endurance and Data Retention
Configuring FPGAs using Cypress S29GL-N Flash
Connecting Cypress™ Flash Memory to a System Address Bus
Connecting Unused Data Lines of MirrorBit
Reset Voltage and Timing Requirements for MirrorBit
Versatile IO: DQ and Enhanced
®
Flash Memory Write Buffer Programming and Page Buffer Read
®
®
Flash
®
Flash
Technology
5.2 Specification Bulletins
Contact your local sales office for details.
5.3 Hardware and Software Support
Downloads and related information on Flash device support is available at
http://www.cypress.com/Support/Pages/DriversSoftware.aspx
Cypress low-level drivers
Enhanced Flash drivers
Flash file system
Downloads and related information on simulation modeling and CAD modeling support is available at
http://www.cypress.com/Support/Pages/SimulationModels.aspx
VHDL and Verilog
IBIS
ORCAD
5.4 Contacting Cypress
Obtain the latest list of company locations and contact information on our web site at
http://www.cypress.com/About/Pages/Locations.aspx
Document Number: 002-00886 Rev. *B Page 12 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
6. Product Overview
The S29GL-P family consists of 1 Gb, 512 Mb, 256 Mb and 128 Mb, 3.0-volt-only, page mode Flash devices optimized for today’s
embedded designs that demand a large storage array and rich functionality. These devices are manufactured using 90 nm MirrorBit
technology. These products offer uniform 64 Kword (128 Kbyte) uniform sectors and feature VersatileIO control, allowing control and
I/O signals to operate from 1.65 V to V
Single word programming or a 32-word programming buffer for an increased programming speed
Program Suspend/Resume and Erase Suspend/Resume
Advanced Sector Protection methods for protecting sectors as required
128 words/256 bytes of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is
One Time Programmable.
6.1 Memory Map
The S29GL-P devices consist of uniform 64 Kword (128 Kbyte) sectors organized as shown in Table –Table .
S29GL01GP Sector & Memory Address Map
Uniform Sector
Size Sector Count Sector Range Address Range (16-bit) Notes
64 Kword/128 Kbyte 1024
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are
not explicitly listed (such as SA001-SA1022) have sector starting and ending addresses that form the same pattern as all other sectors of that size.
For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
. Additional features include:
CC
SA00 0000000h - 000FFFFh Sector Starting Address
: :
SA1023 3FF0000H - 3FFFFFFh Sector Ending Address
S29GL512P Sector & Memory Address Map
Sector
Uniform Sector Size Sector Count
64 Kword/128 Kbyte 512
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are
not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that the same pattern as all other sectors of that size. For
example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
S29GL256P Sector & Memory Address Map
Uniform Sector
Size
64 Kword/
128 Kbyte
Sector
Count
256
Sector
Range Address Range (16-bit) Notes
SA00 0000000h - 000FFFFh Sector Starting Address
: :
SA255 0FF0000H - 0FFFFFFh Sector Ending Address
Range Address Range (16-bit) Notes
SA00 0000000h - 000FFFFh Sector Starting Address
: :
SA511 1FF0000H - 1FFFFFFh Sector Ending Address
Document Number: 002-00886 Rev. *B Page 13 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are
not explicitly listed (such as SA001-SA254) have sector starting and ending addresses that form the same pattern as all other sectors of that size.
For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
S29GL128P Sector & Memory Address Map
Uniform Sector
Size
64 Kword/
128 Kbyte
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are
not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that form the same pattern as all other sectors of that size.
For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
Sector
Count
128
Sector
Range Address Range (16-bit) Notes
SA00 0000000h - 000FFFFh Sector Starting Address
: :
SA127 07F0000 - 7FFFFF Sector Ending Address
Document Number: 002-00886 Rev. *B Page 14 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
7. Device Operations
This section describes the read, program, erase, handshaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
registers (see Table through Table ). The command register itself does not occupy any addressable memory location; rather, it is
composed of latches that store the commands, along with the address and data information needed to execute the command. The
contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device.
Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in
which case the system must pull the RESET# pin low or power cycle the device to return the device to the reading array data mode.
7.1 Device Operation Table
The device must be setup appropriately for each operation. Table describes the required state of each control pin for any particular
operation.
Device Operations
Addresses
Operation CE# OE# WE# RESET# WP#/ACC
(Note 1) DQ0–DQ7
Read L L H H X A
Write (Program/
Erase)
Accelerated Program L H L H V
Standby
LHL H(Note 2) A
HH
V
CC
± 0.3
V
XX
V
CC
± 0.3
V
H X High-Z High-Z High-Z
IN
IN
A
IN
D
OUT
(Note 3) (Note 3)
(Note 3) (Note 3)
DQ8–DQ15
BYTE#= V
D
OUT
BYTE#= V
IH
DQ8–DQ14
= High-Z,
DQ15 = A-1
Output Disable L H H H X X High-Z High-Z High-Z
Reset X X X L X X High-Z High-Z High-Z
Legend
L = Logic Low = V
Notes
1. Addresses are AMax:A0 in word mode; A
2. If WP# = V
unconnected, WP# is at V
depending on version ordered.)
or D
3. D
IN
, H = Logic High = VIH, VHH = 11.5–12.5V, X = Don’t Care, AIN = Address In, DIN = Data In, D
IL
:A-1 in byte mode.
Max
, on the outermost sector remains protected. If WP# = VIH, the outermost sector is unprotected. WP# has an internal pull-up; when
IL
as required by command sequence, data polling, or sector protect algorithm.
OUT
. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected
IH
= Data Out
OUT
IL
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7.2 Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic
‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.3 Versatile IOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on all inputs
and outputs (address, control, and DQ signals). VIO range is 1.65 to V
device.
For example, a V
V devices on the same data bus.
of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3
IO
. See Ordering Information on page 4 for V
CC
options on this
IO
7.4 Read
All memories require access time to output array data. In a read operation, data is read from one memory location at a time.
Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs
to arrive with the address on its inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system
must first assert a valid address on Amax-A0, while driving OE# and CE# to V
on the falling edge of CE#. Data will appear on DQ15-DQ0 after address access time (t
addresses to valid output data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE)
has elapsed from the falling edge of OE#, assuming the t
access time has been meet.
ACC
. WE# must remain at VIH. All addresses are latched
IL
), which is equal to the delay from stable
ACC
7.5 Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides
faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page
is selected by the higher address bits A(max)-A3. Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific
word within a page. The microprocessor supplies the specific word location.
The random or initial page access is equal to t
the microprocessor falls within that page) is equivalent to t
the access time is t
the “intra-read page” addresses.
or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing
ACC
or tCE and subsequent page read accesses (as long as the locations specified by
ACC
. When CE# is de-asserted and reasserted for a subsequent access,
PAC C
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7.6 Autoselect
The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes
output from the internal register (separate from the memory array) on DQ7-DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm (see Table ). The
Autoselect codes can also be accessed in-system.
There are two methods to access autoselect codes. One uses the autoselect command, the other applies V
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins must be
as shown in Table .
To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read
mode.
The Autoselect command may not be written while the device is actively programming or erasing.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously
in Erase Suspend).
It is recommended that A9 apply V
to VIH/VIL before power-down the VCC/VIO.
See Table on page 65 for command sequence details.
When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table to
Table ). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment
may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the
command register.
after power-up sequence is completed. In addition, it is recommended that A9 apply from VID
ID
on address pin A9.
ID
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Autoselect Codes, (High Voltage Method)
Description CE# OE# WE#
Manufacturer ID:
Cypress Product
Cycle 1
Cycle 2 H H L 22 X 28h
Cycle 3 H H H 22 X 01h
Device ID
S29GL01GP
Cycle 1
Cycle 2 H H L 22 X 23h
Cycle 3 H H H 22 X 01h
Device ID
S29GL512P
Cycle 1
Cycle 2 H H L 22 X 22h
Cycle 3 H H H 22 X 01h
Device ID
S29GL256P
Cycle 1
Cycle 2 H H L 22 X 21h
Cycle 3 H H H 22 X 01h
Device ID
S29GL128P
Sector Group
Protection
Verification
Secured Silicon
Sector Indicator Bit
(DQ7), WP# protects
highest address
sector
Secured Silicon
Sector Indicator Bit
(DQ7), WP# protects
lowest address
sector
Legend
L = Logic Low = V
IL
LLH X XV
LLH X XV
LLH X XV
LLH X XVIDXLX
LLH X XVIDXLX
LLHSAXVIDXLXLHL X X
LLH X XV
LLH X XV
, H = Logic High = VIH, SA = Sector Address, X = Don’t care. VID = 11.5V to 12.5V
Ama
x to
A16
A1
4
to
A1
0A9
ID
ID
ID
ID
ID
DQ8 to DQ15
A3
A8
to
A7 A6
X L X L L L 00 X 01h
XLX
XLX
XLXLHH X X
XLXLHH X X
A5
to
to
A2 A1 A0
A4
LLH 22 X 7Eh
LLH 22 X 7Eh
LLH 22 X 7Eh
LLH 22 X 7Eh
BYTE
#= V
BYTE
# = V
IH
IL
00h (unprotected)
DQ7 to DQ0
01h (protected),
99h (factory
locked),
19h (not factory
locked)
89h (factory
locked),
09h (not factory
locked)
Autoselect Addresses in System
Description Address Read Data (word/byte mode)
Manufacturer ID Base + 00h xx01h/1h
Device ID, Word 1 Base + 01h 227Eh/7Eh
2228h/28h (GL01GP)
Device ID, Word 2 Base + 0Eh
2223h/23h (GL512P)
2222h/22h (GL256P)
2221h/21h (GL128P)
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Autoselect Addresses in System
Description Address Read Data (word/byte mode)
Device ID, Word 3 Base + 0Fh 2201h/01h
Secure Device
Verify
Sector Protect
Verify
Base + 03h
(SA) + 02h xx01h/01h = Locked, xx00h/00h = Unlocked
For S29GLxxxPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S29GLxxxPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
Software Functions and Sample Code
Autoselect Entry in System
(LLD Function = lld_AutoselectEntryCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 0x00AAh
Unlock Cycle 2 Write Base + 555h Base + 2AAh 0x0055h
Autoselect Command Write Base + AAAh Base + 555h 0x0090h
Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Byte
Cycle Operation
Autoselect Exit Command Write base + XXXh base + XXXh 0x00F0h
Note
1. Any offset within the device works.
2. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Cypress Low
Level Driver User’s Guide (available on www.cypress.com) for general information on Cypress Flash memory software development
guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
Address
Word
Address Data
manuf_id = *( (UINT16 *)base_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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7.7 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following
sections.
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing address, command, and data.
Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles
within the command sequence. See Section 7.7.8 for details on the Unlock Bypass function.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode.
The system can determine the status of the program operation by reading the DQ status bits. Refer to the Write Operation Status
on page 32 for information on these status bits.
An “0” cannot be programmed back to a “1.” A succeeding read shows that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program/Erase are ignored except the Suspend commands.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command
sequence should be reinitiated once the device has returned to the read mode to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word programming operation. See Write Buffer
Programming on page 23 when using the write buffer.
Programming to the same word address multiple times without intervening erases is permitted.
7.7.1 Single Word Programming
Single word programming mode is one method of programming the Flash. In this mode, four Flash command write cycles are used
to program an individual Flash address. The data for this programming operation could be 8 or 16-bits wide.
While the single word programming method is supported by most Cypress devices, in general Single Word Programming is not
recommended for devices that support Write Buffer Programming. See Table on page 65 for the required bus cycles and Figure 7.1
for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched.
The system can determine the status of the program operation by reading the DQ status bits. Refer to Write Operation Status
on page 32 for information on these status bits.
During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the
device has returned to the read mode, to ensure data integrity.
Programming to the same address multiple times continuously (for example, “walking” a bit within a word) is permitted.
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Figure 7.1 Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Program Command:
Address 555h, Data A0h
Program Data to Address:
PA , P D
Unlock Cycle 1
Unlock Cycle 2
Setup Command
Program Address (PA),
Program Data (PD)
FAIL. Issue reset command
to return to read array mode.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Ye s
Ye s
No
No
Polling Status
= Busy?
Polling Status
= Done?
Error condition
(Exceeded Timing Limits)
PASS. Device is in
read mode.
Software Functions and Sample Code
Single Word/Byte Program
(LLD Function = lld_ProgramCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Write Base + 555h Base + 2AAh 0055h
Program Setup Write Base + AAAh Base + 555h 00A0h
Program Write Byte Address Word Address Data
Note
Base = Base Address.
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The following is a C source code example of using the single word program function. Refer to the Cypress Low Level Driver User’s
Guide (available on www.cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: Program Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (UINT16 *)pa ) = data; /* write data to be programmed */
/* Poll for program completion */
7.7.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster
effective word programming time than the standard “word” programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. At this point, the system writes the number of “word locations
minus 1” that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many
write buffer addresses are loaded with data and therefore when to expect the “Program Buffer to Flash” confirm command. The
number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of
locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed,
and selects the “write-buffer-page” address. All subsequent address/data pairs must fall within the elected write-buffer-page.
The “write-buffer-page” is selected by using the addresses A
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer
Programming cannot be performed across multiple “write-buffer-pages.” This also means that Write Buffer Programming cannot be
performed across multiple sectors. If the system attempts to load programming data outside of the selected “write-buffer-page”, the
operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter is decremented for every data
load operation. Also, the last data loaded at a location before the “Program Buffer to Flash” confirm command is the data
programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more
than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the
specified number of write buffer locations have been loaded, the system must then write the “Program Buffer to Flash” command at
the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The Write Operation
Status bits should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store
an address in memory because the system can load the last address location, issue the program confirm command at the last
loaded address location, and then check the write operation status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be
monitored to determine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume commands. Upon
successful completion of the Write Buffer Programming operation, the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address” during the “write buffer
data loading” stage of the operation.
Writing anything other than the Program to Buffer Flash Command after the specified number of “data load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”), DQ6 = TOGGLE, DQ5 = 0.
This indicates that the Write Buffer Programming Operation was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is
required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,
autoselect, and CFI functions are unavailable when a program operation is in progress.
MAX
–A5.
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Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling
multiple write buffer programming operations on the same write buffer address range without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be programmed.
Software Functions and Sample Code
Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 555h Base + 2AAh 0055h
3 Write Buffer Load Command Write Sector Address 0025h
4 Write Word Count Write Sector Address Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words (1 to 64 bytes).
5 to 36 Load Buffer Word N Write Program Address, Word N Word N
Last Write Buffer to Flash Write Sector Address 0029h
Notes
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Cypress Low Level Driver User’s
Guide (available on www.cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */
/* NOTES: Write buffer programming limited to 16 words. */
/* All addresses to be written to the flash in */
/* one operation must be within the same flash */
/* page. A flash page begins at addresses */
/* evenly divisible by 0x20. */
UINT16 *src = source_of_data; /* address of source data */
UINT16 *dst = destination_of_data; /* flash destination address */
UINT16 wc = words_to_program -1; /* word count (minus 1) */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */
*( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */
for (i=0;i<=wc;i++)
{
*dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */
}
*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */
/* poll for completion */
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write buffer abort reset */
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Figure 7.2 Write Buffer Programming Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Issue
Write Buffer Load Command:
Address SA, Data 25h
Load Word Count to Program
Program Data to Address:
SA, wc
Unlock Cycle 1
Unlock Cycle 2
wc = number of words – 1
Ye s
Ye s
Ye s
Ye s
Ye s
No
No
No
No
No
wc = 0?
Write Buffer
Abort Desired?
Write Buffer
Abort?
Polling Status
= Done?
Error?
FAIL. Issue reset command
to return to read array mode.
Write to a Different
Sector Address to Cause
Write Buffer Abort
PASS. Device is in
read mode.
Confirm command:
SA = 0x29h
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Write Next Word,
Decrement wc:
wc = wc – 1
RESET. Issue Write Buffer
Abort Reset Command
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7.7.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table on page 65 and Figure 7.3.) The device
does not require the system to preprogram a sector prior to erase. The Embedded Erase algorithm automatically programs and
verifies the entire memory to an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the
erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations.
After the command sequence is written, the sector erase time-out t
addresses may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from
one sector to all sectors. The time between these additional cycles must be less than 50 µs. Any sector erase address and
command following the exceeded time-out (50 µs) may or may not be accepted. Any command other than Sector Erase or Erase
Suspend during the time-out period resets that sector to the read mode. The system can monitor DQ3 to determine if the sector
erase timer has timed out (See Section 7.8.6.) The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the sector returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing sector. Refer to Section 7.8
for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should
be reinitiated once that sector has returned to reading array data, to ensure the sector is properly erased.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles
within the command sequence. See Section 7.7.8 for details on the Unlock Bypass function.
Figure 7.3 illustrates the algorithm for the erase operation. Refer to Section 11.7.5 for parameters and timing diagrams.
Software Functions and Sample Code
Sector Erase
(LLD Function = lld_SectorEraseCmd)
(50 µs) occurs. During the time-out period, additional sector
SEA
Operatio
Cycle Description
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 555h Base + 2AAh 0055h
3 Setup Command Write Base + AAAh Base + 555h 0080h
4 Unlock Write Base + AAAh Base + 555h 00AAh
5 Unlock Write Base + 555h Base + 2AAh 0055h
6 Sector Erase Command Write Sector Address Sector Address 0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within 50 µs.
The following is a C source code example of using the sector erase function. Refer to the Cypress Low Level Driver User’s Guide
(available on www.cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */
*( (UINT16 *)sector_address ) = 0x0030; /* write sector erase command */
n Byte Address Word Address Data
Document Number: 002-00886 Rev. *B Page 25 of 83
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